drivers/clk/qcom/gcc-mdm9607.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-mdm9607.h>
  18
  19 #include "common.h"
  20 #include "clk-regmap.h"
  21 #include "clk-alpha-pll.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26 #include "gdsc.h"
  27
  28 enum {
  29         P_XO,
  30         P_BIMC,
  31         P_GPLL0,
  32         P_GPLL1,
  33         P_GPLL2,
  34         P_SLEEP_CLK,
  35 };
  36
  37 static struct clk_alpha_pll gpll0_early = {
  38         .offset = 0x21000,
  39         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  40         .clkr = {
  41                 .enable_reg = 0x45000,
  42                 .enable_mask = BIT(0),
  43                 .hw.init = &(struct clk_init_data)
  44                 {
  45                         .name = "gpll0_early",
  46                         .parent_data = &(const struct clk_parent_data){
  47                                 .fw_name = "xo",
  48                         },
  49                         .num_parents = 1,
  50                         .ops = &clk_alpha_pll_ops,
  51                 },
  52         },
  53 };
  54
  55 static struct clk_alpha_pll_postdiv gpll0 = {
  56         .offset = 0x21000,
  57         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
  58         .clkr.hw.init = &(struct clk_init_data)
  59         {
  60                 .name = "gpll0",
  61                 .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw },
  62                 .num_parents = 1,
  63                 .ops = &clk_alpha_pll_postdiv_ops,
  64         },
  65 };
  66
  67 static const struct parent_map gcc_xo_gpll0_map[] = {
  68         { P_XO, 0 },
  69         { P_GPLL0, 1 },
  70 };
  71
  72 static const struct clk_parent_data gcc_xo_gpll0[] = {
  73         { .fw_name = "xo" },
  74         { .hw = &gpll0.clkr.hw },
  75 };
  76
  77 static struct clk_pll gpll1 = {
  78         .l_reg = 0x20004,
  79         .m_reg = 0x20008,
  80         .n_reg = 0x2000c,
  81         .config_reg = 0x20010,
  82         .mode_reg = 0x20000,
  83         .status_reg = 0x2001c,
  84         .status_bit = 17,
  85         .clkr.hw.init = &(struct clk_init_data){
  86                 .name = "gpll1",
  87                 .parent_data = &(const struct clk_parent_data){
  88                         .fw_name = "xo",
  89                 },
  90                 .num_parents = 1,
  91                 .ops = &clk_pll_ops,
  92         },
  93 };
  94
  95 static struct clk_regmap gpll1_vote = {
  96         .enable_reg = 0x45000,
  97         .enable_mask = BIT(1),
  98         .hw.init = &(struct clk_init_data){
  99                 .name = "gpll1_vote",
 100                 .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw },
 101                 .num_parents = 1,
 102                 .ops = &clk_pll_vote_ops,
 103         },
 104 };
 105
 106 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
 107         { P_XO, 0 },
 108         { P_GPLL0, 1 },
 109         { P_GPLL1, 2 },
 110         { P_SLEEP_CLK, 6 },
 111 };
 112
 113 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
 114         { .fw_name = "xo" },
 115         { .hw = &gpll0.clkr.hw },
 116         { .hw = &gpll1_vote.hw },
 117         { .fw_name = "sleep_clk" },
 118 };
 119
 120 static struct clk_alpha_pll gpll2_early = {
 121         .offset = 0x25000,
 122         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 123         .clkr = {
 124                 .enable_reg = 0x45000,
 125                 .enable_mask = BIT(3), /* Yeah, apparently it's not 2 */
 126                 .hw.init = &(struct clk_init_data)
 127                 {
 128                         .name = "gpll2_early",
 129                         .parent_data = &(const struct clk_parent_data){
 130                                 .fw_name = "xo",
 131                         },
 132                         .num_parents = 1,
 133                         .ops = &clk_alpha_pll_ops,
 134                 },
 135         },
 136 };
 137
 138 static struct clk_alpha_pll_postdiv gpll2 = {
 139         .offset = 0x25000,
 140         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 141         .clkr.hw.init = &(struct clk_init_data)
 142         {
 143                 .name = "gpll2",
 144                 .parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw },
 145                 .num_parents = 1,
 146                 .ops = &clk_alpha_pll_postdiv_ops,
 147         },
 148 };
 149
 150 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
 151         { P_XO, 0 },
 152         { P_GPLL0, 1 },
 153         { P_GPLL2, 2 },
 154 };
 155
 156 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
 157         { .fw_name = "xo" },
 158         { .hw = &gpll0.clkr.hw },
 159         { .hw = &gpll2.clkr.hw },
 160 };
 161
 162 static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = {
 163         { P_XO, 0 },
 164         { P_GPLL0, 1 },
 165         { P_GPLL1, 2 },
 166         { P_GPLL2, 3 },
 167 };
 168
 169 static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = {
 170         { .fw_name = "xo" },
 171         { .hw = &gpll0.clkr.hw },
 172         { .hw = &gpll1_vote.hw },
 173         { .hw = &gpll2.clkr.hw },
 174 };
 175
 176 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
 177         F(19200000, P_XO, 1, 0, 0),
 178         F(50000000, P_GPLL0, 16, 0, 0),
 179         F(100000000, P_GPLL0, 8, 0, 0),
 180         { }
 181 };
 182
 183 static struct clk_rcg2 apss_ahb_clk_src = {
 184         .cmd_rcgr = 0x46000,
 185         .hid_width = 5,
 186         .parent_map = gcc_xo_gpll0_map,
 187         .freq_tbl = ftbl_apss_ahb_clk,
 188         .clkr.hw.init = &(struct clk_init_data){
 189                 .name = "apss_ahb_clk_src",
 190                 .parent_data = gcc_xo_gpll0,
 191                 .num_parents = 2,
 192                 .ops = &clk_rcg2_ops,
 193         },
 194 };
 195
 196 static struct clk_pll bimc_pll = {
 197         .l_reg = 0x23004,
 198         .m_reg = 0x23008,
 199         .n_reg = 0x2300c,
 200         .config_reg = 0x23010,
 201         .mode_reg = 0x23000,
 202         .status_reg = 0x2301c,
 203         .status_bit = 17,
 204         .clkr.hw.init = &(struct clk_init_data){
 205                 .name = "bimc_pll",
 206                 .parent_data = &(const struct clk_parent_data){
 207                         .fw_name = "xo",
 208                 },
 209                 .num_parents = 1,
 210                 .ops = &clk_pll_ops,
 211         },
 212 };
 213
 214 static struct clk_regmap bimc_pll_vote = {
 215         .enable_reg = 0x45000,
 216         .enable_mask = BIT(3),
 217         .hw.init = &(struct clk_init_data){
 218                 .name = "bimc_pll_vote",
 219                 .parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw },
 220                 .num_parents = 1,
 221                 .ops = &clk_pll_vote_ops,
 222         },
 223 };
 224
 225 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
 226         { P_XO, 0 },
 227         { P_GPLL0, 1 },
 228         { P_BIMC, 2 },
 229 };
 230
 231 static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
 232         { .fw_name = "xo" },
 233         { .hw = &gpll0.clkr.hw },
 234         { .hw = &bimc_pll_vote.hw },
 235 };
 236
 237 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 238         F(19200000, P_XO, 1, 0, 0),
 239         F(50000000, P_GPLL0, 16, 0, 0),
 240         F(100000000, P_GPLL0, 8, 0, 0),
 241         { }
 242 };
 243
 244 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 245         .cmd_rcgr = 0x27000,
 246         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 247         .hid_width = 5,
 248         .parent_map = gcc_xo_gpll0_bimc_map,
 249         .clkr.hw.init = &(struct clk_init_data){
 250                 .name = "pcnoc_bfdcd_clk_src",
 251                 .parent_data = gcc_xo_gpll0_bimc,
 252                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
 253                 .ops = &clk_rcg2_ops,
 254                 .flags = CLK_IS_CRITICAL,
 255         },
 256 };
 257
 258 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
 259         .cmd_rcgr = 0x26004,
 260         .hid_width = 5,
 261         .parent_map = gcc_xo_gpll0_bimc_map,
 262         .clkr.hw.init = &(struct clk_init_data){
 263                 .name = "system_noc_bfdcd_clk_src",
 264                 .parent_data = gcc_xo_gpll0_bimc,
 265                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
 266                 .ops = &clk_rcg2_ops,
 267         },
 268 };
 269
 270 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
 271         F(19200000, P_XO, 1, 0, 0),
 272         F(50000000, P_GPLL0, 16, 0, 0),
 273         { }
 274 };
 275
 276 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 277         .cmd_rcgr = 0x200c,
 278         .hid_width = 5,
 279         .parent_map = gcc_xo_gpll0_map,
 280         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 281         .clkr.hw.init = &(struct clk_init_data){
 282                 .name = "blsp1_qup1_i2c_apps_clk_src",
 283                 .parent_data = gcc_xo_gpll0,
 284                 .num_parents = 2,
 285                 .ops = &clk_rcg2_ops,
 286         },
 287 };
 288
 289 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
 290         F(960000, P_XO, 10, 1, 2),
 291         F(4800000, P_XO, 4, 0, 0),
 292         F(9600000, P_XO, 2, 0, 0),
 293         F(16000000, P_GPLL0, 10, 1, 5),
 294         F(19200000, P_XO, 1, 0, 0),
 295         F(25000000, P_GPLL0, 16, 1, 2),
 296         F(50000000, P_GPLL0, 16, 0, 0),
 297         { }
 298 };
 299
 300 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 301         .cmd_rcgr = 0x2024,
 302         .mnd_width = 8,
 303         .hid_width = 5,
 304         .parent_map = gcc_xo_gpll0_map,
 305         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 306         .clkr.hw.init = &(struct clk_init_data){
 307                 .name = "blsp1_qup1_spi_apps_clk_src",
 308                 .parent_data = gcc_xo_gpll0,
 309                 .num_parents = 2,
 310                 .ops = &clk_rcg2_ops,
 311         },
 312 };
 313
 314 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 315         .cmd_rcgr = 0x3000,
 316         .hid_width = 5,
 317         .parent_map = gcc_xo_gpll0_map,
 318         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 319         .clkr.hw.init = &(struct clk_init_data){
 320                 .name = "blsp1_qup2_i2c_apps_clk_src",
 321                 .parent_data = gcc_xo_gpll0,
 322                 .num_parents = 2,
 323                 .ops = &clk_rcg2_ops,
 324         },
 325 };
 326
 327 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 328         .cmd_rcgr = 0x3014,
 329         .mnd_width = 8,
 330         .hid_width = 5,
 331         .parent_map = gcc_xo_gpll0_map,
 332         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 333         .clkr.hw.init = &(struct clk_init_data){
 334                 .name = "blsp1_qup2_spi_apps_clk_src",
 335                 .parent_data = gcc_xo_gpll0,
 336                 .num_parents = 2,
 337                 .ops = &clk_rcg2_ops,
 338         },
 339 };
 340
 341 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 342         .cmd_rcgr = 0x4000,
 343         .hid_width = 5,
 344         .parent_map = gcc_xo_gpll0_map,
 345         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 346         .clkr.hw.init = &(struct clk_init_data){
 347                 .name = "blsp1_qup3_i2c_apps_clk_src",
 348                 .parent_data = gcc_xo_gpll0,
 349                 .num_parents = 2,
 350                 .ops = &clk_rcg2_ops,
 351         },
 352 };
 353
 354 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 355         .cmd_rcgr = 0x4024,
 356         .mnd_width = 8,
 357         .hid_width = 5,
 358         .parent_map = gcc_xo_gpll0_map,
 359         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 360         .clkr.hw.init = &(struct clk_init_data){
 361                 .name = "blsp1_qup3_spi_apps_clk_src",
 362                 .parent_data = gcc_xo_gpll0,
 363                 .num_parents = 2,
 364                 .ops = &clk_rcg2_ops,
 365         },
 366 };
 367
 368 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 369         .cmd_rcgr = 0x5000,
 370         .hid_width = 5,
 371         .parent_map = gcc_xo_gpll0_map,
 372         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 373         .clkr.hw.init = &(struct clk_init_data){
 374                 .name = "blsp1_qup4_i2c_apps_clk_src",
 375                 .parent_data = gcc_xo_gpll0,
 376                 .num_parents = 2,
 377                 .ops = &clk_rcg2_ops,
 378         },
 379 };
 380
 381 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 382         .cmd_rcgr = 0x5024,
 383         .mnd_width = 8,
 384         .hid_width = 5,
 385         .parent_map = gcc_xo_gpll0_map,
 386         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 387         .clkr.hw.init = &(struct clk_init_data){
 388                 .name = "blsp1_qup4_spi_apps_clk_src",
 389                 .parent_data = gcc_xo_gpll0,
 390                 .num_parents = 2,
 391                 .ops = &clk_rcg2_ops,
 392         },
 393 };
 394
 395 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 396         .cmd_rcgr = 0x6000,
 397         .hid_width = 5,
 398         .parent_map = gcc_xo_gpll0_map,
 399         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 400         .clkr.hw.init = &(struct clk_init_data){
 401                 .name = "blsp1_qup5_i2c_apps_clk_src",
 402                 .parent_data = gcc_xo_gpll0,
 403                 .num_parents = 2,
 404                 .ops = &clk_rcg2_ops,
 405         },
 406 };
 407
 408 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 409         .cmd_rcgr = 0x6024,
 410         .mnd_width = 8,
 411         .hid_width = 5,
 412         .parent_map = gcc_xo_gpll0_map,
 413         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 414         .clkr.hw.init = &(struct clk_init_data){
 415                 .name = "blsp1_qup5_spi_apps_clk_src",
 416                 .parent_data = gcc_xo_gpll0,
 417                 .num_parents = 2,
 418                 .ops = &clk_rcg2_ops,
 419         },
 420 };
 421
 422 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 423         .cmd_rcgr = 0x7000,
 424         .hid_width = 5,
 425         .parent_map = gcc_xo_gpll0_map,
 426         .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
 427         .clkr.hw.init = &(struct clk_init_data){
 428                 .name = "blsp1_qup6_i2c_apps_clk_src",
 429                 .parent_data = gcc_xo_gpll0,
 430                 .num_parents = 2,
 431                 .ops = &clk_rcg2_ops,
 432         },
 433 };
 434
 435 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 436         .cmd_rcgr = 0x7024,
 437         .mnd_width = 8,
 438         .hid_width = 5,
 439         .parent_map = gcc_xo_gpll0_map,
 440         .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
 441         .clkr.hw.init = &(struct clk_init_data){
 442                 .name = "blsp1_qup6_spi_apps_clk_src",
 443                 .parent_data = gcc_xo_gpll0,
 444                 .num_parents = 2,
 445                 .ops = &clk_rcg2_ops,
 446         },
 447 };
 448
 449 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
 450         F(3686400, P_GPLL0, 1, 72, 15625),
 451         F(7372800, P_GPLL0, 1, 144, 15625),
 452         F(14745600, P_GPLL0, 1, 288, 15625),
 453         F(16000000, P_GPLL0, 10, 1, 5),
 454         F(19200000, P_XO, 1, 0, 0),
 455         F(24000000, P_GPLL0, 1, 3, 100),
 456         F(25000000, P_GPLL0, 16, 1, 2),
 457         F(32000000, P_GPLL0, 1, 1, 25),
 458         F(40000000, P_GPLL0, 1, 1, 20),
 459         F(46400000, P_GPLL0, 1, 29, 500),
 460         F(48000000, P_GPLL0, 1, 3, 50),
 461         F(51200000, P_GPLL0, 1, 8, 125),
 462         F(56000000, P_GPLL0, 1, 7, 100),
 463         F(58982400, P_GPLL0, 1, 1152, 15625),
 464         F(60000000, P_GPLL0, 1, 3, 40),
 465         { }
 466 };
 467
 468 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 469         .cmd_rcgr = 0x2044,
 470         .mnd_width = 16,
 471         .hid_width = 5,
 472         .parent_map = gcc_xo_gpll0_map,
 473         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 474         .clkr.hw.init = &(struct clk_init_data){
 475                 .name = "blsp1_uart1_apps_clk_src",
 476                 .parent_data = gcc_xo_gpll0,
 477                 .num_parents = 2,
 478                 .ops = &clk_rcg2_ops,
 479         },
 480 };
 481
 482 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 483         .cmd_rcgr = 0x3034,
 484         .mnd_width = 16,
 485         .hid_width = 5,
 486         .parent_map = gcc_xo_gpll0_map,
 487         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 488         .clkr.hw.init = &(struct clk_init_data){
 489                 .name = "blsp1_uart2_apps_clk_src",
 490                 .parent_data = gcc_xo_gpll0,
 491                 .num_parents = 2,
 492                 .ops = &clk_rcg2_ops,
 493         },
 494 };
 495
 496 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 497         .cmd_rcgr = 0x4044,
 498         .mnd_width = 16,
 499         .hid_width = 5,
 500         .parent_map = gcc_xo_gpll0_map,
 501         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 502         .clkr.hw.init = &(struct clk_init_data){
 503                 .name = "blsp1_uart3_apps_clk_src",
 504                 .parent_data = gcc_xo_gpll0,
 505                 .num_parents = 2,
 506                 .ops = &clk_rcg2_ops,
 507         },
 508 };
 509
 510 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 511         .cmd_rcgr = 0x5044,
 512         .mnd_width = 16,
 513         .hid_width = 5,
 514         .parent_map = gcc_xo_gpll0_map,
 515         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 516         .clkr.hw.init = &(struct clk_init_data){
 517                 .name = "blsp1_uart4_apps_clk_src",
 518                 .parent_data = gcc_xo_gpll0,
 519                 .num_parents = 2,
 520                 .ops = &clk_rcg2_ops,
 521         },
 522 };
 523
 524 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 525         .cmd_rcgr = 0x6044,
 526         .mnd_width = 16,
 527         .hid_width = 5,
 528         .parent_map = gcc_xo_gpll0_map,
 529         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 530         .clkr.hw.init = &(struct clk_init_data){
 531                 .name = "blsp1_uart5_apps_clk_src",
 532                 .parent_data = gcc_xo_gpll0,
 533                 .num_parents = 2,
 534                 .ops = &clk_rcg2_ops,
 535         },
 536 };
 537
 538 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 539         .cmd_rcgr = 0x6044,
 540         .mnd_width = 16,
 541         .hid_width = 5,
 542         .parent_map = gcc_xo_gpll0_map,
 543         .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
 544         .clkr.hw.init = &(struct clk_init_data){
 545                 .name = "blsp1_uart6_apps_clk_src",
 546                 .parent_data = gcc_xo_gpll0,
 547                 .num_parents = 2,
 548                 .ops = &clk_rcg2_ops,
 549         },
 550 };
 551
 552 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
 553         F(50000000, P_GPLL0, 16, 0, 0),
 554         F(80000000, P_GPLL0, 10, 0, 0),
 555         F(100000000, P_GPLL0, 8, 0, 0),
 556         F(160000000, P_GPLL0, 5, 0, 0),
 557         { }
 558 };
 559
 560 static struct clk_rcg2 crypto_clk_src = {
 561         .cmd_rcgr = 0x16004,
 562         .hid_width = 5,
 563         .parent_map = gcc_xo_gpll0_map,
 564         .freq_tbl = ftbl_gcc_crypto_clk,
 565         .clkr.hw.init = &(struct clk_init_data){
 566                 .name = "crypto_clk_src",
 567                 .parent_data = gcc_xo_gpll0,
 568                 .num_parents = 2,
 569                 .ops = &clk_rcg2_ops,
 570         },
 571 };
 572
 573 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
 574         F(19200000, P_XO, 1, 0, 0),
 575         { }
 576 };
 577
 578 static struct clk_rcg2 gp1_clk_src = {
 579         .cmd_rcgr = 0x8004,
 580         .mnd_width = 8,
 581         .hid_width = 5,
 582         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
 583         .freq_tbl = ftbl_gcc_gp1_3_clk,
 584         .clkr.hw.init = &(struct clk_init_data){
 585                 .name = "gp1_clk_src",
 586                 .parent_data = gcc_xo_gpll0_gpll1_sleep,
 587                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
 588                 .ops = &clk_rcg2_ops,
 589         },
 590 };
 591
 592 static struct clk_rcg2 gp2_clk_src = {
 593         .cmd_rcgr = 0x09004,
 594         .mnd_width = 8,
 595         .hid_width = 5,
 596         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
 597         .freq_tbl = ftbl_gcc_gp1_3_clk,
 598         .clkr.hw.init = &(struct clk_init_data){
 599                 .name = "gp2_clk_src",
 600                 .parent_data = gcc_xo_gpll0_gpll1_sleep,
 601                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
 602                 .ops = &clk_rcg2_ops,
 603         },
 604 };
 605
 606 static struct clk_rcg2 gp3_clk_src = {
 607         .cmd_rcgr = 0x0a004,
 608         .mnd_width = 8,
 609         .hid_width = 5,
 610         .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
 611         .freq_tbl = ftbl_gcc_gp1_3_clk,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "gp3_clk_src",
 614                 .parent_data = gcc_xo_gpll0_gpll1_sleep,
 615                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
 616                 .ops = &clk_rcg2_ops,
 617         },
 618 };
 619
 620 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
 621         F(64000000, P_GPLL0, 12.5, 0, 0),
 622         { }
 623 };
 624
 625 static struct clk_rcg2 pdm2_clk_src = {
 626         .cmd_rcgr = 0x44010,
 627         .hid_width = 5,
 628         .parent_map = gcc_xo_gpll0_map,
 629         .freq_tbl = ftbl_gcc_pdm2_clk,
 630         .clkr.hw.init = &(struct clk_init_data){
 631                 .name = "pdm2_clk_src",
 632                 .parent_data = gcc_xo_gpll0,
 633                 .num_parents = 2,
 634                 .ops = &clk_rcg2_ops,
 635         },
 636 };
 637
 638 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
 639         F(144000, P_XO, 16, 3, 25),
 640         F(400000, P_XO, 12, 1, 4),
 641         F(20000000, P_GPLL0, 10, 1, 4),
 642         F(25000000, P_GPLL0, 16, 1, 2),
 643         F(50000000, P_GPLL0, 16, 0, 0),
 644         F(100000000, P_GPLL0, 8, 0, 0),
 645         F(177770000, P_GPLL0, 4.5, 0, 0),
 646         F(200000000, P_GPLL0, 4, 0, 0),
 647         { }
 648 };
 649
 650 static struct clk_rcg2 sdcc1_apps_clk_src = {
 651         .cmd_rcgr = 0x42004,
 652         .mnd_width = 8,
 653         .hid_width = 5,
 654         .parent_map = gcc_xo_gpll0_map,
 655         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
 656         .clkr.hw.init = &(struct clk_init_data){
 657                 .name = "sdcc1_apps_clk_src",
 658                 .parent_data = gcc_xo_gpll0,
 659                 .num_parents = 2,
 660                 .ops = &clk_rcg2_floor_ops,
 661         },
 662 };
 663
 664 static struct clk_rcg2 sdcc2_apps_clk_src = {
 665         .cmd_rcgr = 0x43004,
 666         .mnd_width = 8,
 667         .hid_width = 5,
 668         .parent_map = gcc_xo_gpll0_map,
 669         .freq_tbl = ftbl_gcc_sdcc_apps_clk,
 670         .clkr.hw.init = &(struct clk_init_data){
 671                 .name = "sdcc2_apps_clk_src",
 672                 .parent_data = gcc_xo_gpll0,
 673                 .num_parents = 2,
 674                 .ops = &clk_rcg2_floor_ops,
 675         },
 676 };
 677
 678 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
 679         F(155000000, P_GPLL2, 6, 0, 0),
 680         F(310000000, P_GPLL2, 3, 0, 0),
 681         F(400000000, P_GPLL0, 2, 0, 0),
 682         { }
 683 };
 684
 685 static struct clk_rcg2 apss_tcu_clk_src = {
 686         .cmd_rcgr = 0x1207c,
 687         .hid_width = 5,
 688         .parent_map = gcc_xo_gpll0_gpll1_gpll2_map,
 689         .freq_tbl = ftbl_gcc_apss_tcu_clk,
 690         .clkr.hw.init = &(struct clk_init_data){
 691                 .name = "apss_tcu_clk_src",
 692                 .parent_data = gcc_xo_gpll0_gpll1_gpll2,
 693                 .num_parents = 4,
 694                 .ops = &clk_rcg2_ops,
 695         },
 696 };
 697
 698 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
 699         F(19200000, P_XO, 1, 0, 0),
 700         F(57140000, P_GPLL0, 14, 0, 0),
 701         F(69565000, P_GPLL0, 11.5, 0, 0),
 702         F(133330000, P_GPLL0, 6, 0, 0),
 703         F(177778000, P_GPLL0, 4.5, 0, 0),
 704         { }
 705 };
 706
 707 static struct clk_rcg2 usb_hs_system_clk_src = {
 708         .cmd_rcgr = 0x41010,
 709         .hid_width = 5,
 710         .parent_map = gcc_xo_gpll0_map,
 711         .freq_tbl = ftbl_gcc_usb_hs_system_clk,
 712         .clkr.hw.init = &(struct clk_init_data){
 713                 .name = "usb_hs_system_clk_src",
 714                 .parent_data = gcc_xo_gpll0,
 715                 .num_parents = 2,
 716                 .ops = &clk_rcg2_ops,
 717         },
 718 };
 719
 720 static const struct freq_tbl ftbl_usb_hsic_clk_src[] = {
 721         F(480000000, P_GPLL2, 1, 0, 0),
 722         { }
 723 };
 724
 725 static struct clk_rcg2 usb_hsic_clk_src = {
 726         .cmd_rcgr = 0x3d018,
 727         .hid_width = 5,
 728         .parent_map = gcc_xo_gpll0_gpll2_map,
 729         .freq_tbl = ftbl_usb_hsic_clk_src,
 730         .clkr.hw.init = &(struct clk_init_data){
 731                 .name = "usb_hsic_clk_src",
 732                 .parent_data = gcc_xo_gpll0_gpll2,
 733                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
 734                 .ops = &clk_rcg2_ops,
 735         },
 736 };
 737
 738 static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = {
 739         F(9600000, P_XO, 2, 0, 0),
 740         { }
 741 };
 742
 743 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
 744         .cmd_rcgr = 0x3d030,
 745         .hid_width = 5,
 746         .parent_map = gcc_xo_gpll0_map,
 747         .freq_tbl = ftbl_usb_hsic_io_cal_clk_src,
 748         .clkr.hw.init = &(struct clk_init_data){
 749                 .name = "usb_hsic_io_cal_clk_src",
 750                 .parent_data = gcc_xo_gpll0,
 751                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 752                 .ops = &clk_rcg2_ops,
 753         },
 754 };
 755
 756 static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = {
 757         F(19200000, P_XO, 1, 0, 0),
 758         F(57140000, P_GPLL0, 14, 0, 0),
 759         F(133330000, P_GPLL0, 6, 0, 0),
 760         F(177778000, P_GPLL0, 4.5, 0, 0),
 761         { }
 762 };
 763
 764 static struct clk_rcg2 usb_hsic_system_clk_src = {
 765         .cmd_rcgr = 0x3d000,
 766         .hid_width = 5,
 767         .parent_map = gcc_xo_gpll0_map,
 768         .freq_tbl = ftbl_usb_hsic_system_clk_src,
 769         .clkr.hw.init = &(struct clk_init_data){
 770                 .name = "usb_hsic_system_clk_src",
 771                 .parent_data = gcc_xo_gpll0,
 772                 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
 773                 .ops = &clk_rcg2_ops,
 774         },
 775 };
 776
 777 static struct clk_branch gcc_blsp1_ahb_clk = {
 778         .halt_reg = 0x1008,
 779         .halt_check = BRANCH_HALT_VOTED,
 780         .clkr = {
 781                 .enable_reg = 0x45004,
 782                 .enable_mask = BIT(10),
 783                 .hw.init = &(struct clk_init_data){
 784                         .name = "gcc_blsp1_ahb_clk",
 785                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
 786                         .num_parents = 1,
 787                         .ops = &clk_branch2_ops,
 788                 },
 789         },
 790 };
 791
 792 static struct clk_branch gcc_blsp1_sleep_clk = {
 793         .halt_reg = 0x1004,
 794         .clkr = {
 795                 .enable_reg = 0x1004,
 796                 .enable_mask = BIT(0),
 797                 .hw.init = &(struct clk_init_data){
 798                         .name = "gcc_blsp1_sleep_clk",
 799                         .parent_data = &(const struct clk_parent_data){
 800                                 .fw_name = "sleep_clk",
 801                         },
 802                         .num_parents = 1,
 803                         .flags = CLK_SET_RATE_PARENT,
 804                         .ops = &clk_branch2_ops,
 805                 },
 806         },
 807 };
 808
 809 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
 810         .halt_reg = 0x2008,
 811         .clkr = {
 812                 .enable_reg = 0x2008,
 813                 .enable_mask = BIT(0),
 814                 .hw.init = &(struct clk_init_data){
 815                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
 816                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
 817                         .num_parents = 1,
 818                         .flags = CLK_SET_RATE_PARENT,
 819                         .ops = &clk_branch2_ops,
 820                 },
 821         },
 822 };
 823
 824 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
 825         .halt_reg = 0x2004,
 826         .clkr = {
 827                 .enable_reg = 0x2004,
 828                 .enable_mask = BIT(0),
 829                 .hw.init = &(struct clk_init_data){
 830                         .name = "gcc_blsp1_qup1_spi_apps_clk",
 831                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
 832                         .num_parents = 1,
 833                         .flags = CLK_SET_RATE_PARENT,
 834                         .ops = &clk_branch2_ops,
 835                 },
 836         },
 837 };
 838
 839 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
 840         .halt_reg = 0x3010,
 841         .clkr = {
 842                 .enable_reg = 0x3010,
 843                 .enable_mask = BIT(0),
 844                 .hw.init = &(struct clk_init_data){
 845                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
 846                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
 847                         .num_parents = 1,
 848                         .flags = CLK_SET_RATE_PARENT,
 849                         .ops = &clk_branch2_ops,
 850                 },
 851         },
 852 };
 853
 854 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
 855         .halt_reg = 0x300c,
 856         .clkr = {
 857                 .enable_reg = 0x300c,
 858                 .enable_mask = BIT(0),
 859                 .hw.init = &(struct clk_init_data){
 860                         .name = "gcc_blsp1_qup2_spi_apps_clk",
 861                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
 862                         .num_parents = 1,
 863                         .flags = CLK_SET_RATE_PARENT,
 864                         .ops = &clk_branch2_ops,
 865                 },
 866         },
 867 };
 868
 869 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
 870         .halt_reg = 0x4020,
 871         .clkr = {
 872                 .enable_reg = 0x4020,
 873                 .enable_mask = BIT(0),
 874                 .hw.init = &(struct clk_init_data){
 875                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
 876                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
 877                         .num_parents = 1,
 878                         .flags = CLK_SET_RATE_PARENT,
 879                         .ops = &clk_branch2_ops,
 880                 },
 881         },
 882 };
 883
 884 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
 885         .halt_reg = 0x401c,
 886         .clkr = {
 887                 .enable_reg = 0x401c,
 888                 .enable_mask = BIT(0),
 889                 .hw.init = &(struct clk_init_data){
 890                         .name = "gcc_blsp1_qup3_spi_apps_clk",
 891                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
 892                         .num_parents = 1,
 893                         .flags = CLK_SET_RATE_PARENT,
 894                         .ops = &clk_branch2_ops,
 895                 },
 896         },
 897 };
 898
 899 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
 900         .halt_reg = 0x5020,
 901         .clkr = {
 902                 .enable_reg = 0x5020,
 903                 .enable_mask = BIT(0),
 904                 .hw.init = &(struct clk_init_data){
 905                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
 906                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
 907                         .num_parents = 1,
 908                         .flags = CLK_SET_RATE_PARENT,
 909                         .ops = &clk_branch2_ops,
 910                 },
 911         },
 912 };
 913
 914 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
 915         .halt_reg = 0x501c,
 916         .clkr = {
 917                 .enable_reg = 0x501c,
 918                 .enable_mask = BIT(0),
 919                 .hw.init = &(struct clk_init_data){
 920                         .name = "gcc_blsp1_qup4_spi_apps_clk",
 921                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
 922                         .num_parents = 1,
 923                         .flags = CLK_SET_RATE_PARENT,
 924                         .ops = &clk_branch2_ops,
 925                 },
 926         },
 927 };
 928
 929 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
 930         .halt_reg = 0x6020,
 931         .clkr = {
 932                 .enable_reg = 0x6020,
 933                 .enable_mask = BIT(0),
 934                 .hw.init = &(struct clk_init_data){
 935                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
 936                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
 937                         .num_parents = 1,
 938                         .flags = CLK_SET_RATE_PARENT,
 939                         .ops = &clk_branch2_ops,
 940                 },
 941         },
 942 };
 943
 944 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
 945         .halt_reg = 0x601c,
 946         .clkr = {
 947                 .enable_reg = 0x601c,
 948                 .enable_mask = BIT(0),
 949                 .hw.init = &(struct clk_init_data){
 950                         .name = "gcc_blsp1_qup5_spi_apps_clk",
 951                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
 952                         .num_parents = 1,
 953                         .flags = CLK_SET_RATE_PARENT,
 954                         .ops = &clk_branch2_ops,
 955                 },
 956         },
 957 };
 958
 959 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
 960         .halt_reg = 0x7020,
 961         .clkr = {
 962                 .enable_reg = 0x7020,
 963                 .enable_mask = BIT(0),
 964                 .hw.init = &(struct clk_init_data){
 965                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
 966                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
 967                         .num_parents = 1,
 968                         .flags = CLK_SET_RATE_PARENT,
 969                         .ops = &clk_branch2_ops,
 970                 },
 971         },
 972 };
 973
 974 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
 975         .halt_reg = 0x701c,
 976         .clkr = {
 977                 .enable_reg = 0x701c,
 978                 .enable_mask = BIT(0),
 979                 .hw.init = &(struct clk_init_data){
 980                         .name = "gcc_blsp1_qup6_spi_apps_clk",
 981                         .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
 982                         .num_parents = 1,
 983                         .flags = CLK_SET_RATE_PARENT,
 984                         .ops = &clk_branch2_ops,
 985                 },
 986         },
 987 };
 988
 989 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
 990         .halt_reg = 0x203c,
 991         .clkr = {
 992                 .enable_reg = 0x203c,
 993                 .enable_mask = BIT(0),
 994                 .hw.init = &(struct clk_init_data){
 995                         .name = "gcc_blsp1_uart1_apps_clk",
 996                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
 997                         .num_parents = 1,
 998                         .flags = CLK_SET_RATE_PARENT,
 999                         .ops = &clk_branch2_ops,
1000                 },
1001         },
1002 };
1003
1004 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1005         .halt_reg = 0x302c,
1006         .clkr = {
1007                 .enable_reg = 0x302c,
1008                 .enable_mask = BIT(0),
1009                 .hw.init = &(struct clk_init_data){
1010                         .name = "gcc_blsp1_uart2_apps_clk",
1011                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1012                         .num_parents = 1,
1013                         .flags = CLK_SET_RATE_PARENT,
1014                         .ops = &clk_branch2_ops,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1020         .halt_reg = 0x403c,
1021         .clkr = {
1022                 .enable_reg = 0x403c,
1023                 .enable_mask = BIT(0),
1024                 .hw.init = &(struct clk_init_data){
1025                         .name = "gcc_blsp1_uart3_apps_clk",
1026                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1027                         .num_parents = 1,
1028                         .flags = CLK_SET_RATE_PARENT,
1029                         .ops = &clk_branch2_ops,
1030                 },
1031         },
1032 };
1033
1034 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1035         .halt_reg = 0x503c,
1036         .clkr = {
1037                 .enable_reg = 0x503c,
1038                 .enable_mask = BIT(0),
1039                 .hw.init = &(struct clk_init_data){
1040                         .name = "gcc_blsp1_uart4_apps_clk",
1041                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1042                         .num_parents = 1,
1043                         .flags = CLK_SET_RATE_PARENT,
1044                         .ops = &clk_branch2_ops,
1045                 },
1046         },
1047 };
1048
1049 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1050         .halt_reg = 0x603c,
1051         .clkr = {
1052                 .enable_reg = 0x603c,
1053                 .enable_mask = BIT(0),
1054                 .hw.init = &(struct clk_init_data){
1055                         .name = "gcc_blsp1_uart5_apps_clk",
1056                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1057                         .num_parents = 1,
1058                         .flags = CLK_SET_RATE_PARENT,
1059                         .ops = &clk_branch2_ops,
1060                 },
1061         },
1062 };
1063
1064 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1065         .halt_reg = 0x703c,
1066         .clkr = {
1067                 .enable_reg = 0x703c,
1068                 .enable_mask = BIT(0),
1069                 .hw.init = &(struct clk_init_data){
1070                         .name = "gcc_blsp1_uart6_apps_clk",
1071                         .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1072                         .num_parents = 1,
1073                         .flags = CLK_SET_RATE_PARENT,
1074                         .ops = &clk_branch2_ops,
1075                 },
1076         },
1077 };
1078
1079 static struct clk_branch gcc_boot_rom_ahb_clk = {
1080         .halt_reg = 0x1300c,
1081         .halt_check = BRANCH_HALT_VOTED,
1082         .clkr = {
1083                 .enable_reg = 0x45004,
1084                 .enable_mask = BIT(7),
1085                 .hw.init = &(struct clk_init_data){
1086                         .name = "gcc_boot_rom_ahb_clk",
1087                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1088                         .num_parents = 1,
1089                         .ops = &clk_branch2_ops,
1090                 },
1091         },
1092 };
1093
1094 static struct clk_branch gcc_crypto_ahb_clk = {
1095         .halt_reg = 0x16024,
1096         .halt_check = BRANCH_HALT_VOTED,
1097         .clkr = {
1098                 .enable_reg = 0x45004,
1099                 .enable_mask = BIT(0),
1100                 .hw.init = &(struct clk_init_data){
1101                         .name = "gcc_crypto_ahb_clk",
1102                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1103                         .num_parents = 1,
1104                         .flags = CLK_SET_RATE_PARENT,
1105                         .ops = &clk_branch2_ops,
1106                 },
1107         },
1108 };
1109
1110 static struct clk_branch gcc_crypto_axi_clk = {
1111         .halt_reg = 0x16020,
1112         .halt_check = BRANCH_HALT_VOTED,
1113         .clkr = {
1114                 .enable_reg = 0x45004,
1115                 .enable_mask = BIT(1),
1116                 .hw.init = &(struct clk_init_data){
1117                         .name = "gcc_crypto_axi_clk",
1118                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1119                         .num_parents = 1,
1120                         .flags = CLK_SET_RATE_PARENT,
1121                         .ops = &clk_branch2_ops,
1122                 },
1123         },
1124 };
1125
1126 static struct clk_branch gcc_crypto_clk = {
1127         .halt_reg = 0x1601c,
1128         .halt_check = BRANCH_HALT_VOTED,
1129         .clkr = {
1130                 .enable_reg = 0x45004,
1131                 .enable_mask = BIT(2),
1132                 .hw.init = &(struct clk_init_data){
1133                         .name = "gcc_crypto_clk",
1134                         .parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw },
1135                         .num_parents = 1,
1136                         .flags = CLK_SET_RATE_PARENT,
1137                         .ops = &clk_branch2_ops,
1138                 },
1139         },
1140 };
1141
1142 static struct clk_branch gcc_gp1_clk = {
1143         .halt_reg = 0x08000,
1144         .clkr = {
1145                 .enable_reg = 0x08000,
1146                 .enable_mask = BIT(0),
1147                 .hw.init = &(struct clk_init_data){
1148                         .name = "gcc_gp1_clk",
1149                         .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1150                         .num_parents = 1,
1151                         .flags = CLK_SET_RATE_PARENT,
1152                         .ops = &clk_branch2_ops,
1153                 },
1154         },
1155 };
1156
1157 static struct clk_branch gcc_gp2_clk = {
1158         .halt_reg = 0x09000,
1159         .clkr = {
1160                 .enable_reg = 0x09000,
1161                 .enable_mask = BIT(0),
1162                 .hw.init = &(struct clk_init_data){
1163                         .name = "gcc_gp2_clk",
1164                         .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1165                         .num_parents = 1,
1166                         .flags = CLK_SET_RATE_PARENT,
1167                         .ops = &clk_branch2_ops,
1168                 },
1169         },
1170 };
1171
1172 static struct clk_branch gcc_gp3_clk = {
1173         .halt_reg = 0x0a000,
1174         .clkr = {
1175                 .enable_reg = 0x0a000,
1176                 .enable_mask = BIT(0),
1177                 .hw.init = &(struct clk_init_data){
1178                         .name = "gcc_gp3_clk",
1179                         .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1180                         .num_parents = 1,
1181                         .flags = CLK_SET_RATE_PARENT,
1182                         .ops = &clk_branch2_ops,
1183                 },
1184         },
1185 };
1186
1187 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1188         .halt_reg = 0x49000,
1189         .clkr = {
1190                 .enable_reg = 0x49000,
1191                 .enable_mask = BIT(0),
1192                 .hw.init = &(struct clk_init_data){
1193                         .name = "gcc_mss_cfg_ahb_clk",
1194                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1195                         .num_parents = 1,
1196                         .flags = CLK_SET_RATE_PARENT,
1197                         .ops = &clk_branch2_ops,
1198                 },
1199         },
1200 };
1201
1202 static struct clk_branch gcc_pdm2_clk = {
1203         .halt_reg = 0x4400c,
1204         .clkr = {
1205                 .enable_reg = 0x4400c,
1206                 .enable_mask = BIT(0),
1207                 .hw.init = &(struct clk_init_data){
1208                         .name = "gcc_pdm2_clk",
1209                         .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1210                         .num_parents = 1,
1211                         .flags = CLK_SET_RATE_PARENT,
1212                         .ops = &clk_branch2_ops,
1213                 },
1214         },
1215 };
1216
1217 static struct clk_branch gcc_pdm_ahb_clk = {
1218         .halt_reg = 0x44004,
1219         .clkr = {
1220                 .enable_reg = 0x44004,
1221                 .enable_mask = BIT(0),
1222                 .hw.init = &(struct clk_init_data){
1223                         .name = "gcc_pdm_ahb_clk",
1224                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1225                         .num_parents = 1,
1226                         .flags = CLK_SET_RATE_PARENT,
1227                         .ops = &clk_branch2_ops,
1228                 },
1229         },
1230 };
1231
1232 static struct clk_branch gcc_prng_ahb_clk = {
1233         .halt_reg = 0x13004,
1234         .halt_check = BRANCH_HALT_VOTED,
1235         .clkr = {
1236                 .enable_reg = 0x45004,
1237                 .enable_mask = BIT(8),
1238                 .hw.init = &(struct clk_init_data){
1239                         .name = "gcc_prng_ahb_clk",
1240                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1241                         .num_parents = 1,
1242                         .flags = CLK_SET_RATE_PARENT,
1243                         .ops = &clk_branch2_ops,
1244                 },
1245         },
1246 };
1247
1248 static struct clk_branch gcc_sdcc1_ahb_clk = {
1249         .halt_reg = 0x4201c,
1250         .clkr = {
1251                 .enable_reg = 0x4201c,
1252                 .enable_mask = BIT(0),
1253                 .hw.init = &(struct clk_init_data){
1254                         .name = "gcc_sdcc1_ahb_clk",
1255                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1256                         .num_parents = 1,
1257                         .flags = CLK_SET_RATE_PARENT,
1258                         .ops = &clk_branch2_ops,
1259                 },
1260         },
1261 };
1262
1263 static struct clk_branch gcc_sdcc1_apps_clk = {
1264         .halt_reg = 0x42018,
1265         .clkr = {
1266                 .enable_reg = 0x42018,
1267                 .enable_mask = BIT(0),
1268                 .hw.init = &(struct clk_init_data){
1269                         .name = "gcc_sdcc1_apps_clk",
1270                         .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1271                         .num_parents = 1,
1272                         .flags = CLK_SET_RATE_PARENT,
1273                         .ops = &clk_branch2_ops,
1274                 },
1275         },
1276 };
1277
1278 static struct clk_branch gcc_sdcc2_ahb_clk = {
1279         .halt_reg = 0x4301c,
1280         .clkr = {
1281                 .enable_reg = 0x4301c,
1282                 .enable_mask = BIT(0),
1283                 .hw.init = &(struct clk_init_data){
1284                         .name = "gcc_sdcc2_ahb_clk",
1285                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1286                         .num_parents = 1,
1287                         .flags = CLK_SET_RATE_PARENT,
1288                         .ops = &clk_branch2_ops,
1289                 },
1290         },
1291 };
1292
1293 static struct clk_branch gcc_sdcc2_apps_clk = {
1294         .halt_reg = 0x43018,
1295         .clkr = {
1296                 .enable_reg = 0x43018,
1297                 .enable_mask = BIT(0),
1298                 .hw.init = &(struct clk_init_data){
1299                         .name = "gcc_sdcc2_apps_clk",
1300                         .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1301                         .num_parents = 1,
1302                         .flags = CLK_SET_RATE_PARENT,
1303                         .ops = &clk_branch2_ops,
1304                 },
1305         },
1306 };
1307
1308 static struct clk_rcg2 bimc_ddr_clk_src = {
1309         .cmd_rcgr = 0x32004,
1310         .hid_width = 5,
1311         .parent_map = gcc_xo_gpll0_bimc_map,
1312         .clkr.hw.init = &(struct clk_init_data){
1313                 .name = "bimc_ddr_clk_src",
1314                 .parent_data = gcc_xo_gpll0_bimc,
1315                 .num_parents = 3,
1316                 .ops = &clk_rcg2_ops,
1317                 .flags = CLK_GET_RATE_NOCACHE,
1318         },
1319 };
1320
1321 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1322         .halt_reg = 0x49004,
1323         .clkr = {
1324                 .enable_reg = 0x49004,
1325                 .enable_mask = BIT(0),
1326                 .hw.init = &(struct clk_init_data){
1327                         .name = "gcc_mss_q6_bimc_axi_clk",
1328                         .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
1329                         .num_parents = 1,
1330                         .flags = CLK_SET_RATE_PARENT,
1331                         .ops = &clk_branch2_ops,
1332                 },
1333         },
1334 };
1335
1336 static struct clk_branch gcc_apss_tcu_clk = {
1337         .halt_reg = 0x12018,
1338         .halt_check = BRANCH_HALT_VOTED,
1339         .clkr = {
1340                 .enable_reg = 0x4500c,
1341                 .enable_mask = BIT(1),
1342                 .hw.init = &(struct clk_init_data){
1343                         .name = "gcc_apss_tcu_clk",
1344                         .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
1345                         .num_parents = 1,
1346                         .ops = &clk_branch2_ops,
1347                 },
1348         },
1349 };
1350
1351 static struct clk_branch gcc_smmu_cfg_clk = {
1352         .halt_reg = 0x12038,
1353         .halt_check = BRANCH_HALT_VOTED,
1354         .clkr = {
1355                 .enable_reg = 0x4500c,
1356                 .enable_mask = BIT(12),
1357                 .hw.init = &(struct clk_init_data){
1358                         .name = "gcc_smmu_cfg_clk",
1359                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1360                         .num_parents = 1,
1361                         .flags = CLK_SET_RATE_PARENT,
1362                         .ops = &clk_branch2_ops,
1363                 },
1364         },
1365 };
1366
1367 static struct clk_branch gcc_qdss_dap_clk = {
1368         .halt_reg = 0x29084,
1369         .halt_check = BRANCH_HALT_VOTED,
1370         .clkr = {
1371                 .enable_reg = 0x45004,
1372                 .enable_mask = BIT(19),
1373                 .hw.init = &(struct clk_init_data){
1374                         .name = "gcc_qdss_dap_clk",
1375                         .parent_data = &(const struct clk_parent_data){
1376                                 .fw_name = "xo",
1377                         },
1378                         .num_parents = 1,
1379                         .ops = &clk_branch2_ops,
1380                 },
1381         },
1382 };
1383
1384 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
1385         .halt_reg = 0x4102c,
1386         .clkr = {
1387                 .enable_reg = 0x4102c,
1388                 .enable_mask = BIT(0),
1389                 .hw.init = &(struct clk_init_data){
1390                         .name = "gcc_usb2a_phy_sleep_clk",
1391                         .parent_data = &(const struct clk_parent_data){
1392                                 .fw_name = "sleep_clk",
1393                         },
1394                         .num_parents = 1,
1395                         .flags = CLK_SET_RATE_PARENT,
1396                         .ops = &clk_branch2_ops,
1397                 },
1398         },
1399 };
1400
1401 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
1402         .halt_reg = 0x41030,
1403         .halt_check = BRANCH_HALT,
1404         .clkr = {
1405                 .enable_reg = 0x41030,
1406                 .enable_mask = BIT(0),
1407                 .hw.init = &(struct clk_init_data){
1408                         .name = "gcc_usb_hs_phy_cfg_ahb_clk",
1409                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1410                         .num_parents = 1,
1411                         .flags = CLK_SET_RATE_PARENT,
1412                         .ops = &clk_branch2_ops,
1413                 },
1414         },
1415 };
1416
1417 static struct clk_branch gcc_usb_hs_ahb_clk = {
1418         .halt_reg = 0x41008,
1419         .clkr = {
1420                 .enable_reg = 0x41008,
1421                 .enable_mask = BIT(0),
1422                 .hw.init = &(struct clk_init_data){
1423                         .name = "gcc_usb_hs_ahb_clk",
1424                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1425                         .num_parents = 1,
1426                         .flags = CLK_SET_RATE_PARENT,
1427                         .ops = &clk_branch2_ops,
1428                 },
1429         },
1430 };
1431
1432 static struct clk_branch gcc_usb_hs_system_clk = {
1433         .halt_reg = 0x41004,
1434         .clkr = {
1435                 .enable_reg = 0x41004,
1436                 .enable_mask = BIT(0),
1437                 .hw.init = &(struct clk_init_data){
1438                         .name = "gcc_usb_hs_system_clk",
1439                         .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
1440                         .num_parents = 1,
1441                         .flags = CLK_SET_RATE_PARENT,
1442                         .ops = &clk_branch2_ops,
1443                 },
1444         },
1445 };
1446
1447 static struct clk_branch gcc_apss_ahb_clk = {
1448         .halt_reg = 0x4601c,
1449         .halt_check = BRANCH_HALT_VOTED,
1450         .clkr = {
1451                 .enable_reg = 0x45004,
1452                 .enable_mask = BIT(14),
1453                 .hw.init = &(struct clk_init_data){
1454                         .name = "gcc_apss_ahb_clk",
1455                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1456                         .num_parents = 1,
1457                         .ops = &clk_branch2_ops,
1458                 },
1459         },
1460 };
1461
1462 static struct clk_branch gcc_apss_axi_clk = {
1463         .halt_reg = 0x4601c,
1464         .halt_check = BRANCH_HALT_VOTED,
1465         .clkr = {
1466                 .enable_reg = 0x45004,
1467                 .enable_mask = BIT(13),
1468                 .hw.init = &(struct clk_init_data){
1469                         .name = "gcc_apss_axi_clk",
1470                         .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1471                         .num_parents = 1,
1472                         .ops = &clk_branch2_ops,
1473                 },
1474         },
1475 };
1476
1477 static struct clk_regmap *gcc_mdm9607_clocks[] = {
1478         [GPLL0] = &gpll0.clkr,
1479         [GPLL0_EARLY] = &gpll0_early.clkr,
1480         [GPLL1] = &gpll1.clkr,
1481         [GPLL1_VOTE] = &gpll1_vote,
1482         [GPLL2] = &gpll2.clkr,
1483         [GPLL2_EARLY] = &gpll2_early.clkr,
1484         [BIMC_PLL] = &bimc_pll.clkr,
1485         [BIMC_PLL_VOTE] = &bimc_pll_vote,
1486         [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
1487         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
1488         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
1489         [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
1490         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
1491         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
1492         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
1493         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
1494         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
1495         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
1496         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
1497         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
1498         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
1499         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
1500         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
1501         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
1502         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
1503         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
1504         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
1505         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
1506         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
1507         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
1508         [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
1509         [GP1_CLK_SRC] = &gp1_clk_src.clkr,
1510         [GP2_CLK_SRC] = &gp2_clk_src.clkr,
1511         [GP3_CLK_SRC] = &gp3_clk_src.clkr,
1512         [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
1513         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
1514         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
1515         [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
1516         [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
1517         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1518         [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
1519         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1520         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1521         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1522         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1523         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1524         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1525         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1526         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1527         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
1528         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
1529         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
1530         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
1531         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1532         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1533         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1534         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1535         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
1536         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
1537         [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1538         [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
1539         [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
1540         [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
1541         [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1542         [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1543         [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1544         [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
1545         [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1546         [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1547         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
1548         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1549         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1550         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
1551         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
1552         [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
1553         [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
1554         [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
1555         [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
1556         [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
1557         [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
1558         [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
1559         [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
1560         [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
1561         [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
1562         [GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
1563         [GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
1564         [GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
1565 };
1566
1567 static const struct qcom_reset_map gcc_mdm9607_resets[] = {
1568         [USB_HS_HSIC_BCR] = { 0x3d05c },
1569         [GCC_MSS_RESTART] = { 0x3e000 },
1570         [USB_HS_BCR] = { 0x41000 },
1571         [USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
1572         [QUSB2_PHY_BCR] = { 0x4103c },
1573 };
1574
1575 static const struct regmap_config gcc_mdm9607_regmap_config = {
1576         .reg_bits       = 32,
1577         .reg_stride     = 4,
1578         .val_bits       = 32,
1579         .max_register   = 0x80000,
1580         .fast_io        = true,
1581 };
1582
1583 static const struct qcom_cc_desc gcc_mdm9607_desc = {
1584         .config = &gcc_mdm9607_regmap_config,
1585         .clks = gcc_mdm9607_clocks,
1586         .num_clks = ARRAY_SIZE(gcc_mdm9607_clocks),
1587         .resets = gcc_mdm9607_resets,
1588         .num_resets = ARRAY_SIZE(gcc_mdm9607_resets),
1589 };
1590
1591 static const struct of_device_id gcc_mdm9607_match_table[] = {
1592         { .compatible = "qcom,gcc-mdm9607" },
1593         { }
1594 };
1595 MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table);
1596
1597 static int gcc_mdm9607_probe(struct platform_device *pdev)
1598 {
1599         struct regmap *regmap;
1600
1601         regmap = qcom_cc_map(pdev, &gcc_mdm9607_desc);
1602         if (IS_ERR(regmap))
1603                 return PTR_ERR(regmap);
1604
1605         /* Vote for GPLL0 to turn on. Needed by acpuclock. */
1606         regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
1607
1608         return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
1609 }
1610
1611 static struct platform_driver gcc_mdm9607_driver = {
1612         .probe          = gcc_mdm9607_probe,
1613         .driver         = {
1614                 .name   = "gcc-mdm9607",
1615                 .of_match_table = gcc_mdm9607_match_table,
1616         },
1617 };
1618
1619 static int __init gcc_mdm9607_init(void)
1620 {
1621         return platform_driver_register(&gcc_mdm9607_driver);
1622 }
1623 core_initcall(gcc_mdm9607_init);
1624
1625 static void __exit gcc_mdm9607_exit(void)
1626 {
1627         platform_driver_unregister(&gcc_mdm9607_driver);
1628 }
1629 module_exit(gcc_mdm9607_exit);
1630
1631 MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver");
1632 MODULE_LICENSE("GPL v2");