1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/clk-provider.h>
14 #include <linux/regmap.h>
15 #include <linux/reset-controller.h>
17 #include <dt-bindings/clock/qcom,gcc-mdm9607.h>
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
24 #include "clk-branch.h"
37 static struct clk_alpha_pll gpll0_early = {
39 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
41 .enable_reg = 0x45000,
42 .enable_mask = BIT(0),
43 .hw.init = &(struct clk_init_data)
45 .name = "gpll0_early",
46 .parent_data = &(const struct clk_parent_data){
50 .ops = &clk_alpha_pll_ops,
55 static struct clk_alpha_pll_postdiv gpll0 = {
57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
58 .clkr.hw.init = &(struct clk_init_data)
61 .parent_hws = (const struct clk_hw *[]){ &gpll0_early.clkr.hw },
63 .ops = &clk_alpha_pll_postdiv_ops,
67 static const struct parent_map gcc_xo_gpll0_map[] = {
72 static const struct clk_parent_data gcc_xo_gpll0[] = {
74 { .hw = &gpll0.clkr.hw },
77 static struct clk_pll gpll1 = {
81 .config_reg = 0x20010,
83 .status_reg = 0x2001c,
85 .clkr.hw.init = &(struct clk_init_data){
87 .parent_data = &(const struct clk_parent_data){
95 static struct clk_regmap gpll1_vote = {
96 .enable_reg = 0x45000,
97 .enable_mask = BIT(1),
98 .hw.init = &(struct clk_init_data){
100 .parent_hws = (const struct clk_hw *[]){ &gpll1.clkr.hw },
102 .ops = &clk_pll_vote_ops,
106 static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
113 static const struct clk_parent_data gcc_xo_gpll0_gpll1_sleep[] = {
115 { .hw = &gpll0.clkr.hw },
116 { .hw = &gpll1_vote.hw },
117 { .fw_name = "sleep_clk" },
120 static struct clk_alpha_pll gpll2_early = {
122 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
124 .enable_reg = 0x45000,
125 .enable_mask = BIT(3), /* Yeah, apparently it's not 2 */
126 .hw.init = &(struct clk_init_data)
128 .name = "gpll2_early",
129 .parent_data = &(const struct clk_parent_data){
133 .ops = &clk_alpha_pll_ops,
138 static struct clk_alpha_pll_postdiv gpll2 = {
140 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
141 .clkr.hw.init = &(struct clk_init_data)
144 .parent_hws = (const struct clk_hw *[]){ &gpll2_early.clkr.hw },
146 .ops = &clk_alpha_pll_postdiv_ops,
150 static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
156 static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
158 { .hw = &gpll0.clkr.hw },
159 { .hw = &gpll2.clkr.hw },
162 static const struct parent_map gcc_xo_gpll0_gpll1_gpll2_map[] = {
169 static const struct clk_parent_data gcc_xo_gpll0_gpll1_gpll2[] = {
171 { .hw = &gpll0.clkr.hw },
172 { .hw = &gpll1_vote.hw },
173 { .hw = &gpll2.clkr.hw },
176 static const struct freq_tbl ftbl_apss_ahb_clk[] = {
177 F(19200000, P_XO, 1, 0, 0),
178 F(50000000, P_GPLL0, 16, 0, 0),
179 F(100000000, P_GPLL0, 8, 0, 0),
183 static struct clk_rcg2 apss_ahb_clk_src = {
186 .parent_map = gcc_xo_gpll0_map,
187 .freq_tbl = ftbl_apss_ahb_clk,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "apss_ahb_clk_src",
190 .parent_data = gcc_xo_gpll0,
192 .ops = &clk_rcg2_ops,
196 static struct clk_pll bimc_pll = {
200 .config_reg = 0x23010,
202 .status_reg = 0x2301c,
204 .clkr.hw.init = &(struct clk_init_data){
206 .parent_data = &(const struct clk_parent_data){
214 static struct clk_regmap bimc_pll_vote = {
215 .enable_reg = 0x45000,
216 .enable_mask = BIT(3),
217 .hw.init = &(struct clk_init_data){
218 .name = "bimc_pll_vote",
219 .parent_hws = (const struct clk_hw *[]){ &bimc_pll.clkr.hw },
221 .ops = &clk_pll_vote_ops,
225 static const struct parent_map gcc_xo_gpll0_bimc_map[] = {
231 static const struct clk_parent_data gcc_xo_gpll0_bimc[] = {
233 { .hw = &gpll0.clkr.hw },
234 { .hw = &bimc_pll_vote.hw },
237 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
238 F(19200000, P_XO, 1, 0, 0),
239 F(50000000, P_GPLL0, 16, 0, 0),
240 F(100000000, P_GPLL0, 8, 0, 0),
244 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
246 .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
248 .parent_map = gcc_xo_gpll0_bimc_map,
249 .clkr.hw.init = &(struct clk_init_data){
250 .name = "pcnoc_bfdcd_clk_src",
251 .parent_data = gcc_xo_gpll0_bimc,
252 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
253 .ops = &clk_rcg2_ops,
254 .flags = CLK_IS_CRITICAL,
258 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
261 .parent_map = gcc_xo_gpll0_bimc_map,
262 .clkr.hw.init = &(struct clk_init_data){
263 .name = "system_noc_bfdcd_clk_src",
264 .parent_data = gcc_xo_gpll0_bimc,
265 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc),
266 .ops = &clk_rcg2_ops,
270 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_i2c_apps_clk[] = {
271 F(19200000, P_XO, 1, 0, 0),
272 F(50000000, P_GPLL0, 16, 0, 0),
276 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
279 .parent_map = gcc_xo_gpll0_map,
280 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
281 .clkr.hw.init = &(struct clk_init_data){
282 .name = "blsp1_qup1_i2c_apps_clk_src",
283 .parent_data = gcc_xo_gpll0,
285 .ops = &clk_rcg2_ops,
289 static const struct freq_tbl ftbl_gcc_blsp1_qup1_6_spi_apps_clk[] = {
290 F(960000, P_XO, 10, 1, 2),
291 F(4800000, P_XO, 4, 0, 0),
292 F(9600000, P_XO, 2, 0, 0),
293 F(16000000, P_GPLL0, 10, 1, 5),
294 F(19200000, P_XO, 1, 0, 0),
295 F(25000000, P_GPLL0, 16, 1, 2),
296 F(50000000, P_GPLL0, 16, 0, 0),
300 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
304 .parent_map = gcc_xo_gpll0_map,
305 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
306 .clkr.hw.init = &(struct clk_init_data){
307 .name = "blsp1_qup1_spi_apps_clk_src",
308 .parent_data = gcc_xo_gpll0,
310 .ops = &clk_rcg2_ops,
314 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
317 .parent_map = gcc_xo_gpll0_map,
318 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
319 .clkr.hw.init = &(struct clk_init_data){
320 .name = "blsp1_qup2_i2c_apps_clk_src",
321 .parent_data = gcc_xo_gpll0,
323 .ops = &clk_rcg2_ops,
327 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
331 .parent_map = gcc_xo_gpll0_map,
332 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
333 .clkr.hw.init = &(struct clk_init_data){
334 .name = "blsp1_qup2_spi_apps_clk_src",
335 .parent_data = gcc_xo_gpll0,
337 .ops = &clk_rcg2_ops,
341 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
344 .parent_map = gcc_xo_gpll0_map,
345 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
346 .clkr.hw.init = &(struct clk_init_data){
347 .name = "blsp1_qup3_i2c_apps_clk_src",
348 .parent_data = gcc_xo_gpll0,
350 .ops = &clk_rcg2_ops,
354 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
358 .parent_map = gcc_xo_gpll0_map,
359 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
360 .clkr.hw.init = &(struct clk_init_data){
361 .name = "blsp1_qup3_spi_apps_clk_src",
362 .parent_data = gcc_xo_gpll0,
364 .ops = &clk_rcg2_ops,
368 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
371 .parent_map = gcc_xo_gpll0_map,
372 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
373 .clkr.hw.init = &(struct clk_init_data){
374 .name = "blsp1_qup4_i2c_apps_clk_src",
375 .parent_data = gcc_xo_gpll0,
377 .ops = &clk_rcg2_ops,
381 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
385 .parent_map = gcc_xo_gpll0_map,
386 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
387 .clkr.hw.init = &(struct clk_init_data){
388 .name = "blsp1_qup4_spi_apps_clk_src",
389 .parent_data = gcc_xo_gpll0,
391 .ops = &clk_rcg2_ops,
395 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
398 .parent_map = gcc_xo_gpll0_map,
399 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
400 .clkr.hw.init = &(struct clk_init_data){
401 .name = "blsp1_qup5_i2c_apps_clk_src",
402 .parent_data = gcc_xo_gpll0,
404 .ops = &clk_rcg2_ops,
408 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
412 .parent_map = gcc_xo_gpll0_map,
413 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
414 .clkr.hw.init = &(struct clk_init_data){
415 .name = "blsp1_qup5_spi_apps_clk_src",
416 .parent_data = gcc_xo_gpll0,
418 .ops = &clk_rcg2_ops,
422 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
425 .parent_map = gcc_xo_gpll0_map,
426 .freq_tbl = ftbl_gcc_blsp1_qup1_6_i2c_apps_clk,
427 .clkr.hw.init = &(struct clk_init_data){
428 .name = "blsp1_qup6_i2c_apps_clk_src",
429 .parent_data = gcc_xo_gpll0,
431 .ops = &clk_rcg2_ops,
435 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
439 .parent_map = gcc_xo_gpll0_map,
440 .freq_tbl = ftbl_gcc_blsp1_qup1_6_spi_apps_clk,
441 .clkr.hw.init = &(struct clk_init_data){
442 .name = "blsp1_qup6_spi_apps_clk_src",
443 .parent_data = gcc_xo_gpll0,
445 .ops = &clk_rcg2_ops,
449 static const struct freq_tbl ftbl_gcc_blsp1_uart1_6_apps_clk[] = {
450 F(3686400, P_GPLL0, 1, 72, 15625),
451 F(7372800, P_GPLL0, 1, 144, 15625),
452 F(14745600, P_GPLL0, 1, 288, 15625),
453 F(16000000, P_GPLL0, 10, 1, 5),
454 F(19200000, P_XO, 1, 0, 0),
455 F(24000000, P_GPLL0, 1, 3, 100),
456 F(25000000, P_GPLL0, 16, 1, 2),
457 F(32000000, P_GPLL0, 1, 1, 25),
458 F(40000000, P_GPLL0, 1, 1, 20),
459 F(46400000, P_GPLL0, 1, 29, 500),
460 F(48000000, P_GPLL0, 1, 3, 50),
461 F(51200000, P_GPLL0, 1, 8, 125),
462 F(56000000, P_GPLL0, 1, 7, 100),
463 F(58982400, P_GPLL0, 1, 1152, 15625),
464 F(60000000, P_GPLL0, 1, 3, 40),
468 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
472 .parent_map = gcc_xo_gpll0_map,
473 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
474 .clkr.hw.init = &(struct clk_init_data){
475 .name = "blsp1_uart1_apps_clk_src",
476 .parent_data = gcc_xo_gpll0,
478 .ops = &clk_rcg2_ops,
482 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
486 .parent_map = gcc_xo_gpll0_map,
487 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
488 .clkr.hw.init = &(struct clk_init_data){
489 .name = "blsp1_uart2_apps_clk_src",
490 .parent_data = gcc_xo_gpll0,
492 .ops = &clk_rcg2_ops,
496 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
500 .parent_map = gcc_xo_gpll0_map,
501 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
502 .clkr.hw.init = &(struct clk_init_data){
503 .name = "blsp1_uart3_apps_clk_src",
504 .parent_data = gcc_xo_gpll0,
506 .ops = &clk_rcg2_ops,
510 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
514 .parent_map = gcc_xo_gpll0_map,
515 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
516 .clkr.hw.init = &(struct clk_init_data){
517 .name = "blsp1_uart4_apps_clk_src",
518 .parent_data = gcc_xo_gpll0,
520 .ops = &clk_rcg2_ops,
524 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
528 .parent_map = gcc_xo_gpll0_map,
529 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
530 .clkr.hw.init = &(struct clk_init_data){
531 .name = "blsp1_uart5_apps_clk_src",
532 .parent_data = gcc_xo_gpll0,
534 .ops = &clk_rcg2_ops,
538 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
542 .parent_map = gcc_xo_gpll0_map,
543 .freq_tbl = ftbl_gcc_blsp1_uart1_6_apps_clk,
544 .clkr.hw.init = &(struct clk_init_data){
545 .name = "blsp1_uart6_apps_clk_src",
546 .parent_data = gcc_xo_gpll0,
548 .ops = &clk_rcg2_ops,
552 static const struct freq_tbl ftbl_gcc_crypto_clk[] = {
553 F(50000000, P_GPLL0, 16, 0, 0),
554 F(80000000, P_GPLL0, 10, 0, 0),
555 F(100000000, P_GPLL0, 8, 0, 0),
556 F(160000000, P_GPLL0, 5, 0, 0),
560 static struct clk_rcg2 crypto_clk_src = {
563 .parent_map = gcc_xo_gpll0_map,
564 .freq_tbl = ftbl_gcc_crypto_clk,
565 .clkr.hw.init = &(struct clk_init_data){
566 .name = "crypto_clk_src",
567 .parent_data = gcc_xo_gpll0,
569 .ops = &clk_rcg2_ops,
573 static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
574 F(19200000, P_XO, 1, 0, 0),
578 static struct clk_rcg2 gp1_clk_src = {
582 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
583 .freq_tbl = ftbl_gcc_gp1_3_clk,
584 .clkr.hw.init = &(struct clk_init_data){
585 .name = "gp1_clk_src",
586 .parent_data = gcc_xo_gpll0_gpll1_sleep,
587 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
588 .ops = &clk_rcg2_ops,
592 static struct clk_rcg2 gp2_clk_src = {
596 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
597 .freq_tbl = ftbl_gcc_gp1_3_clk,
598 .clkr.hw.init = &(struct clk_init_data){
599 .name = "gp2_clk_src",
600 .parent_data = gcc_xo_gpll0_gpll1_sleep,
601 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
602 .ops = &clk_rcg2_ops,
606 static struct clk_rcg2 gp3_clk_src = {
610 .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
611 .freq_tbl = ftbl_gcc_gp1_3_clk,
612 .clkr.hw.init = &(struct clk_init_data){
613 .name = "gp3_clk_src",
614 .parent_data = gcc_xo_gpll0_gpll1_sleep,
615 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_sleep),
616 .ops = &clk_rcg2_ops,
620 static const struct freq_tbl ftbl_gcc_pdm2_clk[] = {
621 F(64000000, P_GPLL0, 12.5, 0, 0),
625 static struct clk_rcg2 pdm2_clk_src = {
628 .parent_map = gcc_xo_gpll0_map,
629 .freq_tbl = ftbl_gcc_pdm2_clk,
630 .clkr.hw.init = &(struct clk_init_data){
631 .name = "pdm2_clk_src",
632 .parent_data = gcc_xo_gpll0,
634 .ops = &clk_rcg2_ops,
638 static const struct freq_tbl ftbl_gcc_sdcc_apps_clk[] = {
639 F(144000, P_XO, 16, 3, 25),
640 F(400000, P_XO, 12, 1, 4),
641 F(20000000, P_GPLL0, 10, 1, 4),
642 F(25000000, P_GPLL0, 16, 1, 2),
643 F(50000000, P_GPLL0, 16, 0, 0),
644 F(100000000, P_GPLL0, 8, 0, 0),
645 F(177770000, P_GPLL0, 4.5, 0, 0),
646 F(200000000, P_GPLL0, 4, 0, 0),
650 static struct clk_rcg2 sdcc1_apps_clk_src = {
654 .parent_map = gcc_xo_gpll0_map,
655 .freq_tbl = ftbl_gcc_sdcc_apps_clk,
656 .clkr.hw.init = &(struct clk_init_data){
657 .name = "sdcc1_apps_clk_src",
658 .parent_data = gcc_xo_gpll0,
660 .ops = &clk_rcg2_floor_ops,
664 static struct clk_rcg2 sdcc2_apps_clk_src = {
668 .parent_map = gcc_xo_gpll0_map,
669 .freq_tbl = ftbl_gcc_sdcc_apps_clk,
670 .clkr.hw.init = &(struct clk_init_data){
671 .name = "sdcc2_apps_clk_src",
672 .parent_data = gcc_xo_gpll0,
674 .ops = &clk_rcg2_floor_ops,
678 static const struct freq_tbl ftbl_gcc_apss_tcu_clk[] = {
679 F(155000000, P_GPLL2, 6, 0, 0),
680 F(310000000, P_GPLL2, 3, 0, 0),
681 F(400000000, P_GPLL0, 2, 0, 0),
685 static struct clk_rcg2 apss_tcu_clk_src = {
688 .parent_map = gcc_xo_gpll0_gpll1_gpll2_map,
689 .freq_tbl = ftbl_gcc_apss_tcu_clk,
690 .clkr.hw.init = &(struct clk_init_data){
691 .name = "apss_tcu_clk_src",
692 .parent_data = gcc_xo_gpll0_gpll1_gpll2,
694 .ops = &clk_rcg2_ops,
698 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
699 F(19200000, P_XO, 1, 0, 0),
700 F(57140000, P_GPLL0, 14, 0, 0),
701 F(69565000, P_GPLL0, 11.5, 0, 0),
702 F(133330000, P_GPLL0, 6, 0, 0),
703 F(177778000, P_GPLL0, 4.5, 0, 0),
707 static struct clk_rcg2 usb_hs_system_clk_src = {
710 .parent_map = gcc_xo_gpll0_map,
711 .freq_tbl = ftbl_gcc_usb_hs_system_clk,
712 .clkr.hw.init = &(struct clk_init_data){
713 .name = "usb_hs_system_clk_src",
714 .parent_data = gcc_xo_gpll0,
716 .ops = &clk_rcg2_ops,
720 static const struct freq_tbl ftbl_usb_hsic_clk_src[] = {
721 F(480000000, P_GPLL2, 1, 0, 0),
725 static struct clk_rcg2 usb_hsic_clk_src = {
728 .parent_map = gcc_xo_gpll0_gpll2_map,
729 .freq_tbl = ftbl_usb_hsic_clk_src,
730 .clkr.hw.init = &(struct clk_init_data){
731 .name = "usb_hsic_clk_src",
732 .parent_data = gcc_xo_gpll0_gpll2,
733 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
734 .ops = &clk_rcg2_ops,
738 static const struct freq_tbl ftbl_usb_hsic_io_cal_clk_src[] = {
739 F(9600000, P_XO, 2, 0, 0),
743 static struct clk_rcg2 usb_hsic_io_cal_clk_src = {
746 .parent_map = gcc_xo_gpll0_map,
747 .freq_tbl = ftbl_usb_hsic_io_cal_clk_src,
748 .clkr.hw.init = &(struct clk_init_data){
749 .name = "usb_hsic_io_cal_clk_src",
750 .parent_data = gcc_xo_gpll0,
751 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
752 .ops = &clk_rcg2_ops,
756 static const struct freq_tbl ftbl_usb_hsic_system_clk_src[] = {
757 F(19200000, P_XO, 1, 0, 0),
758 F(57140000, P_GPLL0, 14, 0, 0),
759 F(133330000, P_GPLL0, 6, 0, 0),
760 F(177778000, P_GPLL0, 4.5, 0, 0),
764 static struct clk_rcg2 usb_hsic_system_clk_src = {
767 .parent_map = gcc_xo_gpll0_map,
768 .freq_tbl = ftbl_usb_hsic_system_clk_src,
769 .clkr.hw.init = &(struct clk_init_data){
770 .name = "usb_hsic_system_clk_src",
771 .parent_data = gcc_xo_gpll0,
772 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
773 .ops = &clk_rcg2_ops,
777 static struct clk_branch gcc_blsp1_ahb_clk = {
779 .halt_check = BRANCH_HALT_VOTED,
781 .enable_reg = 0x45004,
782 .enable_mask = BIT(10),
783 .hw.init = &(struct clk_init_data){
784 .name = "gcc_blsp1_ahb_clk",
785 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
787 .ops = &clk_branch2_ops,
792 static struct clk_branch gcc_blsp1_sleep_clk = {
795 .enable_reg = 0x1004,
796 .enable_mask = BIT(0),
797 .hw.init = &(struct clk_init_data){
798 .name = "gcc_blsp1_sleep_clk",
799 .parent_data = &(const struct clk_parent_data){
800 .fw_name = "sleep_clk",
803 .flags = CLK_SET_RATE_PARENT,
804 .ops = &clk_branch2_ops,
809 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
812 .enable_reg = 0x2008,
813 .enable_mask = BIT(0),
814 .hw.init = &(struct clk_init_data){
815 .name = "gcc_blsp1_qup1_i2c_apps_clk",
816 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
818 .flags = CLK_SET_RATE_PARENT,
819 .ops = &clk_branch2_ops,
824 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
827 .enable_reg = 0x2004,
828 .enable_mask = BIT(0),
829 .hw.init = &(struct clk_init_data){
830 .name = "gcc_blsp1_qup1_spi_apps_clk",
831 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
833 .flags = CLK_SET_RATE_PARENT,
834 .ops = &clk_branch2_ops,
839 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
842 .enable_reg = 0x3010,
843 .enable_mask = BIT(0),
844 .hw.init = &(struct clk_init_data){
845 .name = "gcc_blsp1_qup2_i2c_apps_clk",
846 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
848 .flags = CLK_SET_RATE_PARENT,
849 .ops = &clk_branch2_ops,
854 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
857 .enable_reg = 0x300c,
858 .enable_mask = BIT(0),
859 .hw.init = &(struct clk_init_data){
860 .name = "gcc_blsp1_qup2_spi_apps_clk",
861 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
863 .flags = CLK_SET_RATE_PARENT,
864 .ops = &clk_branch2_ops,
869 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
872 .enable_reg = 0x4020,
873 .enable_mask = BIT(0),
874 .hw.init = &(struct clk_init_data){
875 .name = "gcc_blsp1_qup3_i2c_apps_clk",
876 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
878 .flags = CLK_SET_RATE_PARENT,
879 .ops = &clk_branch2_ops,
884 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
887 .enable_reg = 0x401c,
888 .enable_mask = BIT(0),
889 .hw.init = &(struct clk_init_data){
890 .name = "gcc_blsp1_qup3_spi_apps_clk",
891 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
893 .flags = CLK_SET_RATE_PARENT,
894 .ops = &clk_branch2_ops,
899 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
902 .enable_reg = 0x5020,
903 .enable_mask = BIT(0),
904 .hw.init = &(struct clk_init_data){
905 .name = "gcc_blsp1_qup4_i2c_apps_clk",
906 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
908 .flags = CLK_SET_RATE_PARENT,
909 .ops = &clk_branch2_ops,
914 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
917 .enable_reg = 0x501c,
918 .enable_mask = BIT(0),
919 .hw.init = &(struct clk_init_data){
920 .name = "gcc_blsp1_qup4_spi_apps_clk",
921 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
923 .flags = CLK_SET_RATE_PARENT,
924 .ops = &clk_branch2_ops,
929 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
932 .enable_reg = 0x6020,
933 .enable_mask = BIT(0),
934 .hw.init = &(struct clk_init_data){
935 .name = "gcc_blsp1_qup5_i2c_apps_clk",
936 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
938 .flags = CLK_SET_RATE_PARENT,
939 .ops = &clk_branch2_ops,
944 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
947 .enable_reg = 0x601c,
948 .enable_mask = BIT(0),
949 .hw.init = &(struct clk_init_data){
950 .name = "gcc_blsp1_qup5_spi_apps_clk",
951 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
953 .flags = CLK_SET_RATE_PARENT,
954 .ops = &clk_branch2_ops,
959 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
962 .enable_reg = 0x7020,
963 .enable_mask = BIT(0),
964 .hw.init = &(struct clk_init_data){
965 .name = "gcc_blsp1_qup6_i2c_apps_clk",
966 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
968 .flags = CLK_SET_RATE_PARENT,
969 .ops = &clk_branch2_ops,
974 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
977 .enable_reg = 0x701c,
978 .enable_mask = BIT(0),
979 .hw.init = &(struct clk_init_data){
980 .name = "gcc_blsp1_qup6_spi_apps_clk",
981 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
983 .flags = CLK_SET_RATE_PARENT,
984 .ops = &clk_branch2_ops,
989 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
992 .enable_reg = 0x203c,
993 .enable_mask = BIT(0),
994 .hw.init = &(struct clk_init_data){
995 .name = "gcc_blsp1_uart1_apps_clk",
996 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
998 .flags = CLK_SET_RATE_PARENT,
999 .ops = &clk_branch2_ops,
1004 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1007 .enable_reg = 0x302c,
1008 .enable_mask = BIT(0),
1009 .hw.init = &(struct clk_init_data){
1010 .name = "gcc_blsp1_uart2_apps_clk",
1011 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1013 .flags = CLK_SET_RATE_PARENT,
1014 .ops = &clk_branch2_ops,
1019 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1022 .enable_reg = 0x403c,
1023 .enable_mask = BIT(0),
1024 .hw.init = &(struct clk_init_data){
1025 .name = "gcc_blsp1_uart3_apps_clk",
1026 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1028 .flags = CLK_SET_RATE_PARENT,
1029 .ops = &clk_branch2_ops,
1034 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1037 .enable_reg = 0x503c,
1038 .enable_mask = BIT(0),
1039 .hw.init = &(struct clk_init_data){
1040 .name = "gcc_blsp1_uart4_apps_clk",
1041 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1043 .flags = CLK_SET_RATE_PARENT,
1044 .ops = &clk_branch2_ops,
1049 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1052 .enable_reg = 0x603c,
1053 .enable_mask = BIT(0),
1054 .hw.init = &(struct clk_init_data){
1055 .name = "gcc_blsp1_uart5_apps_clk",
1056 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1058 .flags = CLK_SET_RATE_PARENT,
1059 .ops = &clk_branch2_ops,
1064 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1067 .enable_reg = 0x703c,
1068 .enable_mask = BIT(0),
1069 .hw.init = &(struct clk_init_data){
1070 .name = "gcc_blsp1_uart6_apps_clk",
1071 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1073 .flags = CLK_SET_RATE_PARENT,
1074 .ops = &clk_branch2_ops,
1079 static struct clk_branch gcc_boot_rom_ahb_clk = {
1080 .halt_reg = 0x1300c,
1081 .halt_check = BRANCH_HALT_VOTED,
1083 .enable_reg = 0x45004,
1084 .enable_mask = BIT(7),
1085 .hw.init = &(struct clk_init_data){
1086 .name = "gcc_boot_rom_ahb_clk",
1087 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1089 .ops = &clk_branch2_ops,
1094 static struct clk_branch gcc_crypto_ahb_clk = {
1095 .halt_reg = 0x16024,
1096 .halt_check = BRANCH_HALT_VOTED,
1098 .enable_reg = 0x45004,
1099 .enable_mask = BIT(0),
1100 .hw.init = &(struct clk_init_data){
1101 .name = "gcc_crypto_ahb_clk",
1102 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1104 .flags = CLK_SET_RATE_PARENT,
1105 .ops = &clk_branch2_ops,
1110 static struct clk_branch gcc_crypto_axi_clk = {
1111 .halt_reg = 0x16020,
1112 .halt_check = BRANCH_HALT_VOTED,
1114 .enable_reg = 0x45004,
1115 .enable_mask = BIT(1),
1116 .hw.init = &(struct clk_init_data){
1117 .name = "gcc_crypto_axi_clk",
1118 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1120 .flags = CLK_SET_RATE_PARENT,
1121 .ops = &clk_branch2_ops,
1126 static struct clk_branch gcc_crypto_clk = {
1127 .halt_reg = 0x1601c,
1128 .halt_check = BRANCH_HALT_VOTED,
1130 .enable_reg = 0x45004,
1131 .enable_mask = BIT(2),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "gcc_crypto_clk",
1134 .parent_hws = (const struct clk_hw *[]){ &crypto_clk_src.clkr.hw },
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1142 static struct clk_branch gcc_gp1_clk = {
1143 .halt_reg = 0x08000,
1145 .enable_reg = 0x08000,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "gcc_gp1_clk",
1149 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1151 .flags = CLK_SET_RATE_PARENT,
1152 .ops = &clk_branch2_ops,
1157 static struct clk_branch gcc_gp2_clk = {
1158 .halt_reg = 0x09000,
1160 .enable_reg = 0x09000,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_gp2_clk",
1164 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1172 static struct clk_branch gcc_gp3_clk = {
1173 .halt_reg = 0x0a000,
1175 .enable_reg = 0x0a000,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_gp3_clk",
1179 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1187 static struct clk_branch gcc_mss_cfg_ahb_clk = {
1188 .halt_reg = 0x49000,
1190 .enable_reg = 0x49000,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gcc_mss_cfg_ahb_clk",
1194 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1202 static struct clk_branch gcc_pdm2_clk = {
1203 .halt_reg = 0x4400c,
1205 .enable_reg = 0x4400c,
1206 .enable_mask = BIT(0),
1207 .hw.init = &(struct clk_init_data){
1208 .name = "gcc_pdm2_clk",
1209 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1217 static struct clk_branch gcc_pdm_ahb_clk = {
1218 .halt_reg = 0x44004,
1220 .enable_reg = 0x44004,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "gcc_pdm_ahb_clk",
1224 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1226 .flags = CLK_SET_RATE_PARENT,
1227 .ops = &clk_branch2_ops,
1232 static struct clk_branch gcc_prng_ahb_clk = {
1233 .halt_reg = 0x13004,
1234 .halt_check = BRANCH_HALT_VOTED,
1236 .enable_reg = 0x45004,
1237 .enable_mask = BIT(8),
1238 .hw.init = &(struct clk_init_data){
1239 .name = "gcc_prng_ahb_clk",
1240 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1242 .flags = CLK_SET_RATE_PARENT,
1243 .ops = &clk_branch2_ops,
1248 static struct clk_branch gcc_sdcc1_ahb_clk = {
1249 .halt_reg = 0x4201c,
1251 .enable_reg = 0x4201c,
1252 .enable_mask = BIT(0),
1253 .hw.init = &(struct clk_init_data){
1254 .name = "gcc_sdcc1_ahb_clk",
1255 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1257 .flags = CLK_SET_RATE_PARENT,
1258 .ops = &clk_branch2_ops,
1263 static struct clk_branch gcc_sdcc1_apps_clk = {
1264 .halt_reg = 0x42018,
1266 .enable_reg = 0x42018,
1267 .enable_mask = BIT(0),
1268 .hw.init = &(struct clk_init_data){
1269 .name = "gcc_sdcc1_apps_clk",
1270 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1272 .flags = CLK_SET_RATE_PARENT,
1273 .ops = &clk_branch2_ops,
1278 static struct clk_branch gcc_sdcc2_ahb_clk = {
1279 .halt_reg = 0x4301c,
1281 .enable_reg = 0x4301c,
1282 .enable_mask = BIT(0),
1283 .hw.init = &(struct clk_init_data){
1284 .name = "gcc_sdcc2_ahb_clk",
1285 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1287 .flags = CLK_SET_RATE_PARENT,
1288 .ops = &clk_branch2_ops,
1293 static struct clk_branch gcc_sdcc2_apps_clk = {
1294 .halt_reg = 0x43018,
1296 .enable_reg = 0x43018,
1297 .enable_mask = BIT(0),
1298 .hw.init = &(struct clk_init_data){
1299 .name = "gcc_sdcc2_apps_clk",
1300 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1302 .flags = CLK_SET_RATE_PARENT,
1303 .ops = &clk_branch2_ops,
1308 static struct clk_rcg2 bimc_ddr_clk_src = {
1309 .cmd_rcgr = 0x32004,
1311 .parent_map = gcc_xo_gpll0_bimc_map,
1312 .clkr.hw.init = &(struct clk_init_data){
1313 .name = "bimc_ddr_clk_src",
1314 .parent_data = gcc_xo_gpll0_bimc,
1316 .ops = &clk_rcg2_ops,
1317 .flags = CLK_GET_RATE_NOCACHE,
1321 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1322 .halt_reg = 0x49004,
1324 .enable_reg = 0x49004,
1325 .enable_mask = BIT(0),
1326 .hw.init = &(struct clk_init_data){
1327 .name = "gcc_mss_q6_bimc_axi_clk",
1328 .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
1330 .flags = CLK_SET_RATE_PARENT,
1331 .ops = &clk_branch2_ops,
1336 static struct clk_branch gcc_apss_tcu_clk = {
1337 .halt_reg = 0x12018,
1338 .halt_check = BRANCH_HALT_VOTED,
1340 .enable_reg = 0x4500c,
1341 .enable_mask = BIT(1),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "gcc_apss_tcu_clk",
1344 .parent_hws = (const struct clk_hw *[]){ &bimc_ddr_clk_src.clkr.hw },
1346 .ops = &clk_branch2_ops,
1351 static struct clk_branch gcc_smmu_cfg_clk = {
1352 .halt_reg = 0x12038,
1353 .halt_check = BRANCH_HALT_VOTED,
1355 .enable_reg = 0x4500c,
1356 .enable_mask = BIT(12),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "gcc_smmu_cfg_clk",
1359 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1367 static struct clk_branch gcc_qdss_dap_clk = {
1368 .halt_reg = 0x29084,
1369 .halt_check = BRANCH_HALT_VOTED,
1371 .enable_reg = 0x45004,
1372 .enable_mask = BIT(19),
1373 .hw.init = &(struct clk_init_data){
1374 .name = "gcc_qdss_dap_clk",
1375 .parent_data = &(const struct clk_parent_data){
1379 .ops = &clk_branch2_ops,
1384 static struct clk_branch gcc_usb2a_phy_sleep_clk = {
1385 .halt_reg = 0x4102c,
1387 .enable_reg = 0x4102c,
1388 .enable_mask = BIT(0),
1389 .hw.init = &(struct clk_init_data){
1390 .name = "gcc_usb2a_phy_sleep_clk",
1391 .parent_data = &(const struct clk_parent_data){
1392 .fw_name = "sleep_clk",
1395 .flags = CLK_SET_RATE_PARENT,
1396 .ops = &clk_branch2_ops,
1401 static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = {
1402 .halt_reg = 0x41030,
1403 .halt_check = BRANCH_HALT,
1405 .enable_reg = 0x41030,
1406 .enable_mask = BIT(0),
1407 .hw.init = &(struct clk_init_data){
1408 .name = "gcc_usb_hs_phy_cfg_ahb_clk",
1409 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1411 .flags = CLK_SET_RATE_PARENT,
1412 .ops = &clk_branch2_ops,
1417 static struct clk_branch gcc_usb_hs_ahb_clk = {
1418 .halt_reg = 0x41008,
1420 .enable_reg = 0x41008,
1421 .enable_mask = BIT(0),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "gcc_usb_hs_ahb_clk",
1424 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1426 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops,
1432 static struct clk_branch gcc_usb_hs_system_clk = {
1433 .halt_reg = 0x41004,
1435 .enable_reg = 0x41004,
1436 .enable_mask = BIT(0),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "gcc_usb_hs_system_clk",
1439 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
1441 .flags = CLK_SET_RATE_PARENT,
1442 .ops = &clk_branch2_ops,
1447 static struct clk_branch gcc_apss_ahb_clk = {
1448 .halt_reg = 0x4601c,
1449 .halt_check = BRANCH_HALT_VOTED,
1451 .enable_reg = 0x45004,
1452 .enable_mask = BIT(14),
1453 .hw.init = &(struct clk_init_data){
1454 .name = "gcc_apss_ahb_clk",
1455 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1457 .ops = &clk_branch2_ops,
1462 static struct clk_branch gcc_apss_axi_clk = {
1463 .halt_reg = 0x4601c,
1464 .halt_check = BRANCH_HALT_VOTED,
1466 .enable_reg = 0x45004,
1467 .enable_mask = BIT(13),
1468 .hw.init = &(struct clk_init_data){
1469 .name = "gcc_apss_axi_clk",
1470 .parent_hws = (const struct clk_hw *[]){ &pcnoc_bfdcd_clk_src.clkr.hw },
1472 .ops = &clk_branch2_ops,
1477 static struct clk_regmap *gcc_mdm9607_clocks[] = {
1478 [GPLL0] = &gpll0.clkr,
1479 [GPLL0_EARLY] = &gpll0_early.clkr,
1480 [GPLL1] = &gpll1.clkr,
1481 [GPLL1_VOTE] = &gpll1_vote,
1482 [GPLL2] = &gpll2.clkr,
1483 [GPLL2_EARLY] = &gpll2_early.clkr,
1484 [BIMC_PLL] = &bimc_pll.clkr,
1485 [BIMC_PLL_VOTE] = &bimc_pll_vote,
1486 [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
1487 [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
1488 [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
1489 [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
1490 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
1491 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
1492 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
1493 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
1494 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
1495 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
1496 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
1497 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
1498 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
1499 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
1500 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
1501 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
1502 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
1503 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
1504 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
1505 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
1506 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
1507 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
1508 [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,
1509 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
1510 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
1511 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
1512 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
1513 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
1514 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
1515 [APSS_TCU_CLK_SRC] = &apss_tcu_clk_src.clkr,
1516 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
1517 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
1518 [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,
1519 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
1520 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
1521 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
1522 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
1523 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
1524 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
1525 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
1526 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
1527 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
1528 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
1529 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
1530 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
1531 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
1532 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
1533 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
1534 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
1535 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
1536 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
1537 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
1538 [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,
1539 [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,
1540 [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,
1541 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
1542 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
1543 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
1544 [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
1545 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
1546 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
1547 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
1548 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
1549 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
1550 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
1551 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
1552 [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr,
1553 [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr,
1554 [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr,
1555 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
1556 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
1557 [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
1558 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
1559 [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
1560 [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
1561 [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
1562 [GCC_USB_HSIC_CLK_SRC] = &usb_hsic_clk_src.clkr,
1563 [GCC_USB_HSIC_IO_CAL_CLK_SRC] = &usb_hsic_io_cal_clk_src.clkr,
1564 [GCC_USB_HSIC_SYSTEM_CLK_SRC] = &usb_hsic_system_clk_src.clkr,
1567 static const struct qcom_reset_map gcc_mdm9607_resets[] = {
1568 [USB_HS_HSIC_BCR] = { 0x3d05c },
1569 [GCC_MSS_RESTART] = { 0x3e000 },
1570 [USB_HS_BCR] = { 0x41000 },
1571 [USB2_HS_PHY_ONLY_BCR] = { 0x41034 },
1572 [QUSB2_PHY_BCR] = { 0x4103c },
1575 static const struct regmap_config gcc_mdm9607_regmap_config = {
1579 .max_register = 0x80000,
1583 static const struct qcom_cc_desc gcc_mdm9607_desc = {
1584 .config = &gcc_mdm9607_regmap_config,
1585 .clks = gcc_mdm9607_clocks,
1586 .num_clks = ARRAY_SIZE(gcc_mdm9607_clocks),
1587 .resets = gcc_mdm9607_resets,
1588 .num_resets = ARRAY_SIZE(gcc_mdm9607_resets),
1591 static const struct of_device_id gcc_mdm9607_match_table[] = {
1592 { .compatible = "qcom,gcc-mdm9607" },
1595 MODULE_DEVICE_TABLE(of, gcc_mdm9607_match_table);
1597 static int gcc_mdm9607_probe(struct platform_device *pdev)
1599 struct regmap *regmap;
1601 regmap = qcom_cc_map(pdev, &gcc_mdm9607_desc);
1603 return PTR_ERR(regmap);
1605 /* Vote for GPLL0 to turn on. Needed by acpuclock. */
1606 regmap_update_bits(regmap, 0x45000, BIT(0), BIT(0));
1608 return qcom_cc_really_probe(pdev, &gcc_mdm9607_desc, regmap);
1611 static struct platform_driver gcc_mdm9607_driver = {
1612 .probe = gcc_mdm9607_probe,
1614 .name = "gcc-mdm9607",
1615 .of_match_table = gcc_mdm9607_match_table,
1619 static int __init gcc_mdm9607_init(void)
1621 return platform_driver_register(&gcc_mdm9607_driver);
1623 core_initcall(gcc_mdm9607_init);
1625 static void __exit gcc_mdm9607_exit(void)
1627 platform_driver_unregister(&gcc_mdm9607_driver);
1629 module_exit(gcc_mdm9607_exit);
1631 MODULE_DESCRIPTION("Qualcomm GCC mdm9607 Driver");
1632 MODULE_LICENSE("GPL v2");