drivers/clk/qcom/gcc-ipq8074.c

   1 /*
   2  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   3  *
   4  * This software is licensed under the terms of the GNU General Public
   5  * License version 2, as published by the Free Software Foundation, and
   6  * may be copied, distributed, and modified under those terms.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/err.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/clk-provider.h>
  21 #include <linux/regmap.h>
  22
  23 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
  24
  25 #include "common.h"
  26 #include "clk-regmap.h"
  27 #include "clk-pll.h"
  28 #include "clk-rcg.h"
  29 #include "clk-branch.h"
  30 #include "clk-alpha-pll.h"
  31 #include "clk-regmap-divider.h"
  32 #include "clk-regmap-mux.h"
  33 #include "reset.h"
  34
  35 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
  36
  37 enum {
  38         P_XO,
  39         P_GPLL0,
  40         P_GPLL0_DIV2,
  41         P_GPLL2,
  42         P_GPLL4,
  43         P_GPLL6,
  44         P_SLEEP_CLK,
  45         P_PCIE20_PHY0_PIPE,
  46         P_PCIE20_PHY1_PIPE,
  47         P_USB3PHY_0_PIPE,
  48         P_USB3PHY_1_PIPE,
  49         P_UBI32_PLL,
  50         P_NSS_CRYPTO_PLL,
  51         P_BIAS_PLL,
  52         P_BIAS_PLL_NSS_NOC,
  53 };
  54
  55 static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = {
  56         "xo",
  57         "gpll0",
  58         "gpll0_out_main_div2",
  59 };
  60
  61 static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
  62         { P_XO, 0 },
  63         { P_GPLL0, 1 },
  64         { P_GPLL0_DIV2, 4 },
  65 };
  66
  67 static const char * const gcc_xo_gpll0[] = {
  68         "xo",
  69         "gpll0",
  70 };
  71
  72 static const struct parent_map gcc_xo_gpll0_map[] = {
  73         { P_XO, 0 },
  74         { P_GPLL0, 1 },
  75 };
  76
  77 static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
  78         "xo",
  79         "gpll0",
  80         "gpll2",
  81         "gpll0_out_main_div2",
  82 };
  83
  84 static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
  85         { P_XO, 0 },
  86         { P_GPLL0, 1 },
  87         { P_GPLL2, 2 },
  88         { P_GPLL0_DIV2, 4 },
  89 };
  90
  91 static const char * const gcc_xo_gpll0_sleep_clk[] = {
  92         "xo",
  93         "gpll0",
  94         "sleep_clk",
  95 };
  96
  97 static const struct parent_map gcc_xo_gpll0_sleep_clk_map[] = {
  98         { P_XO, 0 },
  99         { P_GPLL0, 2 },
 100         { P_SLEEP_CLK, 6 },
 101 };
 102
 103 static const char * const gcc_xo_gpll6_gpll0_gpll0_out_main_div2[] = {
 104         "xo",
 105         "gpll6",
 106         "gpll0",
 107         "gpll0_out_main_div2",
 108 };
 109
 110 static const struct parent_map gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map[] = {
 111         { P_XO, 0 },
 112         { P_GPLL6, 1 },
 113         { P_GPLL0, 3 },
 114         { P_GPLL0_DIV2, 4 },
 115 };
 116
 117 static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = {
 118         "xo",
 119         "gpll0_out_main_div2",
 120         "gpll0",
 121 };
 122
 123 static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
 124         { P_XO, 0 },
 125         { P_GPLL0_DIV2, 2 },
 126         { P_GPLL0, 1 },
 127 };
 128
 129 static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = {
 130         "usb3phy_0_cc_pipe_clk",
 131         "xo",
 132 };
 133
 134 static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
 135         { P_USB3PHY_0_PIPE, 0 },
 136         { P_XO, 2 },
 137 };
 138
 139 static const char * const gcc_usb3phy_1_cc_pipe_clk_xo[] = {
 140         "usb3phy_1_cc_pipe_clk",
 141         "xo",
 142 };
 143
 144 static const struct parent_map gcc_usb3phy_1_cc_pipe_clk_xo_map[] = {
 145         { P_USB3PHY_1_PIPE, 0 },
 146         { P_XO, 2 },
 147 };
 148
 149 static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = {
 150         "pcie20_phy0_pipe_clk",
 151         "xo",
 152 };
 153
 154 static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {
 155         { P_PCIE20_PHY0_PIPE, 0 },
 156         { P_XO, 2 },
 157 };
 158
 159 static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = {
 160         "pcie20_phy1_pipe_clk",
 161         "xo",
 162 };
 163
 164 static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {
 165         { P_PCIE20_PHY1_PIPE, 0 },
 166         { P_XO, 2 },
 167 };
 168
 169 static const char * const gcc_xo_gpll0_gpll6_gpll0_div2[] = {
 170         "xo",
 171         "gpll0",
 172         "gpll6",
 173         "gpll0_out_main_div2",
 174 };
 175
 176 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_div2_map[] = {
 177         { P_XO, 0 },
 178         { P_GPLL0, 1 },
 179         { P_GPLL6, 2 },
 180         { P_GPLL0_DIV2, 4 },
 181 };
 182
 183 static const char * const gcc_xo_gpll0_gpll6_gpll0_out_main_div2[] = {
 184         "xo",
 185         "gpll0",
 186         "gpll6",
 187         "gpll0_out_main_div2",
 188 };
 189
 190 static const struct parent_map gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map[] = {
 191         { P_XO, 0 },
 192         { P_GPLL0, 1 },
 193         { P_GPLL6, 2 },
 194         { P_GPLL0_DIV2, 3 },
 195 };
 196
 197 static const char * const gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
 198         "xo",
 199         "bias_pll_nss_noc_clk",
 200         "gpll0",
 201         "gpll2",
 202 };
 203
 204 static const struct parent_map gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map[] = {
 205         { P_XO, 0 },
 206         { P_BIAS_PLL_NSS_NOC, 1 },
 207         { P_GPLL0, 2 },
 208         { P_GPLL2, 3 },
 209 };
 210
 211 static const char * const gcc_xo_nss_crypto_pll_gpll0[] = {
 212         "xo",
 213         "nss_crypto_pll",
 214         "gpll0",
 215 };
 216
 217 static const struct parent_map gcc_xo_nss_crypto_pll_gpll0_map[] = {
 218         { P_XO, 0 },
 219         { P_NSS_CRYPTO_PLL, 1 },
 220         { P_GPLL0, 2 },
 221 };
 222
 223 static const char * const gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6[] = {
 224         "xo",
 225         "ubi32_pll",
 226         "gpll0",
 227         "gpll2",
 228         "gpll4",
 229         "gpll6",
 230 };
 231
 232 static const struct parent_map gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map[] = {
 233         { P_XO, 0 },
 234         { P_UBI32_PLL, 1 },
 235         { P_GPLL0, 2 },
 236         { P_GPLL2, 3 },
 237         { P_GPLL4, 4 },
 238         { P_GPLL6, 5 },
 239 };
 240
 241 static const char * const gcc_xo_gpll0_out_main_div2[] = {
 242         "xo",
 243         "gpll0_out_main_div2",
 244 };
 245
 246 static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = {
 247         { P_XO, 0 },
 248         { P_GPLL0_DIV2, 1 },
 249 };
 250
 251 static const char * const gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
 252         "xo",
 253         "bias_pll_cc_clk",
 254         "gpll0",
 255         "gpll4",
 256         "nss_crypto_pll",
 257         "ubi32_pll",
 258 };
 259
 260 static const struct parent_map gcc_xo_bias_gpll0_gpll4_nss_ubi32_map[] = {
 261         { P_XO, 0 },
 262         { P_BIAS_PLL, 1 },
 263         { P_GPLL0, 2 },
 264         { P_GPLL4, 3 },
 265         { P_NSS_CRYPTO_PLL, 4 },
 266         { P_UBI32_PLL, 5 },
 267 };
 268
 269 static const char * const gcc_xo_gpll0_gpll4[] = {
 270         "xo",
 271         "gpll0",
 272         "gpll4",
 273 };
 274
 275 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
 276         { P_XO, 0 },
 277         { P_GPLL0, 1 },
 278         { P_GPLL4, 2 },
 279 };
 280
 281 static struct clk_alpha_pll gpll0_main = {
 282         .offset = 0x21000,
 283         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 284         .clkr = {
 285                 .enable_reg = 0x0b000,
 286                 .enable_mask = BIT(0),
 287                 .hw.init = &(struct clk_init_data){
 288                         .name = "gpll0_main",
 289                         .parent_names = (const char *[]){
 290                                 "xo"
 291                         },
 292                         .num_parents = 1,
 293                         .ops = &clk_alpha_pll_ops,
 294                 },
 295         },
 296 };
 297
 298 static struct clk_fixed_factor gpll0_out_main_div2 = {
 299         .mult = 1,
 300         .div = 2,
 301         .hw.init = &(struct clk_init_data){
 302                 .name = "gpll0_out_main_div2",
 303                 .parent_names = (const char *[]){
 304                         "gpll0_main"
 305                 },
 306                 .num_parents = 1,
 307                 .ops = &clk_fixed_factor_ops,
 308                 .flags = CLK_SET_RATE_PARENT,
 309         },
 310 };
 311
 312 static struct clk_alpha_pll_postdiv gpll0 = {
 313         .offset = 0x21000,
 314         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 315         .width = 4,
 316         .clkr.hw.init = &(struct clk_init_data){
 317                 .name = "gpll0",
 318                 .parent_names = (const char *[]){
 319                         "gpll0_main"
 320                 },
 321                 .num_parents = 1,
 322                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 323         },
 324 };
 325
 326 static struct clk_alpha_pll gpll2_main = {
 327         .offset = 0x4a000,
 328         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 329         .clkr = {
 330                 .enable_reg = 0x0b000,
 331                 .enable_mask = BIT(2),
 332                 .hw.init = &(struct clk_init_data){
 333                         .name = "gpll2_main",
 334                         .parent_names = (const char *[]){
 335                                 "xo"
 336                         },
 337                         .num_parents = 1,
 338                         .ops = &clk_alpha_pll_ops,
 339                         .flags = CLK_IS_CRITICAL,
 340                 },
 341         },
 342 };
 343
 344 static struct clk_alpha_pll_postdiv gpll2 = {
 345         .offset = 0x4a000,
 346         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 347         .width = 4,
 348         .clkr.hw.init = &(struct clk_init_data){
 349                 .name = "gpll2",
 350                 .parent_names = (const char *[]){
 351                         "gpll2_main"
 352                 },
 353                 .num_parents = 1,
 354                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 355                 .flags = CLK_SET_RATE_PARENT,
 356         },
 357 };
 358
 359 static struct clk_alpha_pll gpll4_main = {
 360         .offset = 0x24000,
 361         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 362         .clkr = {
 363                 .enable_reg = 0x0b000,
 364                 .enable_mask = BIT(5),
 365                 .hw.init = &(struct clk_init_data){
 366                         .name = "gpll4_main",
 367                         .parent_names = (const char *[]){
 368                                 "xo"
 369                         },
 370                         .num_parents = 1,
 371                         .ops = &clk_alpha_pll_ops,
 372                         .flags = CLK_IS_CRITICAL,
 373                 },
 374         },
 375 };
 376
 377 static struct clk_alpha_pll_postdiv gpll4 = {
 378         .offset = 0x24000,
 379         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 380         .width = 4,
 381         .clkr.hw.init = &(struct clk_init_data){
 382                 .name = "gpll4",
 383                 .parent_names = (const char *[]){
 384                         "gpll4_main"
 385                 },
 386                 .num_parents = 1,
 387                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 388                 .flags = CLK_SET_RATE_PARENT,
 389         },
 390 };
 391
 392 static struct clk_alpha_pll gpll6_main = {
 393         .offset = 0x37000,
 394         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 395         .flags = SUPPORTS_DYNAMIC_UPDATE,
 396         .clkr = {
 397                 .enable_reg = 0x0b000,
 398                 .enable_mask = BIT(7),
 399                 .hw.init = &(struct clk_init_data){
 400                         .name = "gpll6_main",
 401                         .parent_names = (const char *[]){
 402                                 "xo"
 403                         },
 404                         .num_parents = 1,
 405                         .ops = &clk_alpha_pll_ops,
 406                         .flags = CLK_IS_CRITICAL,
 407                 },
 408         },
 409 };
 410
 411 static struct clk_alpha_pll_postdiv gpll6 = {
 412         .offset = 0x37000,
 413         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_BRAMMO],
 414         .width = 2,
 415         .clkr.hw.init = &(struct clk_init_data){
 416                 .name = "gpll6",
 417                 .parent_names = (const char *[]){
 418                         "gpll6_main"
 419                 },
 420                 .num_parents = 1,
 421                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 422                 .flags = CLK_SET_RATE_PARENT,
 423         },
 424 };
 425
 426 static struct clk_fixed_factor gpll6_out_main_div2 = {
 427         .mult = 1,
 428         .div = 2,
 429         .hw.init = &(struct clk_init_data){
 430                 .name = "gpll6_out_main_div2",
 431                 .parent_names = (const char *[]){
 432                         "gpll6_main"
 433                 },
 434                 .num_parents = 1,
 435                 .ops = &clk_fixed_factor_ops,
 436                 .flags = CLK_SET_RATE_PARENT,
 437         },
 438 };
 439
 440 static struct clk_alpha_pll ubi32_pll_main = {
 441         .offset = 0x25000,
 442         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 443         .flags = SUPPORTS_DYNAMIC_UPDATE,
 444         .clkr = {
 445                 .enable_reg = 0x0b000,
 446                 .enable_mask = BIT(6),
 447                 .hw.init = &(struct clk_init_data){
 448                         .name = "ubi32_pll_main",
 449                         .parent_names = (const char *[]){
 450                                 "xo"
 451                         },
 452                         .num_parents = 1,
 453                         .ops = &clk_alpha_pll_huayra_ops,
 454                 },
 455         },
 456 };
 457
 458 static struct clk_alpha_pll_postdiv ubi32_pll = {
 459         .offset = 0x25000,
 460         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_HUAYRA],
 461         .width = 2,
 462         .clkr.hw.init = &(struct clk_init_data){
 463                 .name = "ubi32_pll",
 464                 .parent_names = (const char *[]){
 465                         "ubi32_pll_main"
 466                 },
 467                 .num_parents = 1,
 468                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 469                 .flags = CLK_SET_RATE_PARENT,
 470         },
 471 };
 472
 473 static struct clk_alpha_pll nss_crypto_pll_main = {
 474         .offset = 0x22000,
 475         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 476         .clkr = {
 477                 .enable_reg = 0x0b000,
 478                 .enable_mask = BIT(4),
 479                 .hw.init = &(struct clk_init_data){
 480                         .name = "nss_crypto_pll_main",
 481                         .parent_names = (const char *[]){
 482                                 "xo"
 483                         },
 484                         .num_parents = 1,
 485                         .ops = &clk_alpha_pll_ops,
 486                 },
 487         },
 488 };
 489
 490 static struct clk_alpha_pll_postdiv nss_crypto_pll = {
 491         .offset = 0x22000,
 492         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
 493         .width = 4,
 494         .clkr.hw.init = &(struct clk_init_data){
 495                 .name = "nss_crypto_pll",
 496                 .parent_names = (const char *[]){
 497                         "nss_crypto_pll_main"
 498                 },
 499                 .num_parents = 1,
 500                 .ops = &clk_alpha_pll_postdiv_ro_ops,
 501                 .flags = CLK_SET_RATE_PARENT,
 502         },
 503 };
 504
 505 static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
 506         F(19200000, P_XO, 1, 0, 0),
 507         F(50000000, P_GPLL0, 16, 0, 0),
 508         F(100000000, P_GPLL0, 8, 0, 0),
 509         { }
 510 };
 511
 512 static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
 513         .cmd_rcgr = 0x27000,
 514         .freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
 515         .hid_width = 5,
 516         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 517         .clkr.hw.init = &(struct clk_init_data){
 518                 .name = "pcnoc_bfdcd_clk_src",
 519                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 520                 .num_parents = 3,
 521                 .ops = &clk_rcg2_ops,
 522                 .flags = CLK_IS_CRITICAL,
 523         },
 524 };
 525
 526 static struct clk_fixed_factor pcnoc_clk_src = {
 527         .mult = 1,
 528         .div = 1,
 529         .hw.init = &(struct clk_init_data){
 530                 .name = "pcnoc_clk_src",
 531                 .parent_names = (const char *[]){
 532                         "pcnoc_bfdcd_clk_src"
 533                 },
 534                 .num_parents = 1,
 535                 .ops = &clk_fixed_factor_ops,
 536                 .flags = CLK_SET_RATE_PARENT,
 537         },
 538 };
 539
 540 static struct clk_branch gcc_sleep_clk_src = {
 541         .halt_reg = 0x30000,
 542         .clkr = {
 543                 .enable_reg = 0x30000,
 544                 .enable_mask = BIT(1),
 545                 .hw.init = &(struct clk_init_data){
 546                         .name = "gcc_sleep_clk_src",
 547                         .parent_names = (const char *[]){
 548                                 "sleep_clk"
 549                         },
 550                         .num_parents = 1,
 551                         .ops = &clk_branch2_ops,
 552                 },
 553         },
 554 };
 555
 556 static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
 557         F(19200000, P_XO, 1, 0, 0),
 558         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
 559         F(50000000, P_GPLL0, 16, 0, 0),
 560         { }
 561 };
 562
 563 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
 564         .cmd_rcgr = 0x0200c,
 565         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 566         .hid_width = 5,
 567         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 568         .clkr.hw.init = &(struct clk_init_data){
 569                 .name = "blsp1_qup1_i2c_apps_clk_src",
 570                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 571                 .num_parents = 3,
 572                 .ops = &clk_rcg2_ops,
 573         },
 574 };
 575
 576 static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
 577         F(960000, P_XO, 10, 1, 2),
 578         F(4800000, P_XO, 4, 0, 0),
 579         F(9600000, P_XO, 2, 0, 0),
 580         F(12500000, P_GPLL0_DIV2, 16, 1, 2),
 581         F(16000000, P_GPLL0, 10, 1, 5),
 582         F(19200000, P_XO, 1, 0, 0),
 583         F(25000000, P_GPLL0, 16, 1, 2),
 584         F(50000000, P_GPLL0, 16, 0, 0),
 585         { }
 586 };
 587
 588 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
 589         .cmd_rcgr = 0x02024,
 590         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 591         .mnd_width = 8,
 592         .hid_width = 5,
 593         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 594         .clkr.hw.init = &(struct clk_init_data){
 595                 .name = "blsp1_qup1_spi_apps_clk_src",
 596                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 597                 .num_parents = 3,
 598                 .ops = &clk_rcg2_ops,
 599         },
 600 };
 601
 602 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
 603         .cmd_rcgr = 0x03000,
 604         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 605         .hid_width = 5,
 606         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 607         .clkr.hw.init = &(struct clk_init_data){
 608                 .name = "blsp1_qup2_i2c_apps_clk_src",
 609                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 610                 .num_parents = 3,
 611                 .ops = &clk_rcg2_ops,
 612         },
 613 };
 614
 615 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
 616         .cmd_rcgr = 0x03014,
 617         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 618         .mnd_width = 8,
 619         .hid_width = 5,
 620         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 621         .clkr.hw.init = &(struct clk_init_data){
 622                 .name = "blsp1_qup2_spi_apps_clk_src",
 623                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 624                 .num_parents = 3,
 625                 .ops = &clk_rcg2_ops,
 626         },
 627 };
 628
 629 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
 630         .cmd_rcgr = 0x04000,
 631         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 632         .hid_width = 5,
 633         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 634         .clkr.hw.init = &(struct clk_init_data){
 635                 .name = "blsp1_qup3_i2c_apps_clk_src",
 636                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 637                 .num_parents = 3,
 638                 .ops = &clk_rcg2_ops,
 639         },
 640 };
 641
 642 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
 643         .cmd_rcgr = 0x04014,
 644         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 645         .mnd_width = 8,
 646         .hid_width = 5,
 647         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 648         .clkr.hw.init = &(struct clk_init_data){
 649                 .name = "blsp1_qup3_spi_apps_clk_src",
 650                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 651                 .num_parents = 3,
 652                 .ops = &clk_rcg2_ops,
 653         },
 654 };
 655
 656 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
 657         .cmd_rcgr = 0x05000,
 658         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 659         .hid_width = 5,
 660         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 661         .clkr.hw.init = &(struct clk_init_data){
 662                 .name = "blsp1_qup4_i2c_apps_clk_src",
 663                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 664                 .num_parents = 3,
 665                 .ops = &clk_rcg2_ops,
 666         },
 667 };
 668
 669 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
 670         .cmd_rcgr = 0x05014,
 671         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 672         .mnd_width = 8,
 673         .hid_width = 5,
 674         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 675         .clkr.hw.init = &(struct clk_init_data){
 676                 .name = "blsp1_qup4_spi_apps_clk_src",
 677                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 678                 .num_parents = 3,
 679                 .ops = &clk_rcg2_ops,
 680         },
 681 };
 682
 683 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
 684         .cmd_rcgr = 0x06000,
 685         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 686         .hid_width = 5,
 687         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 688         .clkr.hw.init = &(struct clk_init_data){
 689                 .name = "blsp1_qup5_i2c_apps_clk_src",
 690                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 691                 .num_parents = 3,
 692                 .ops = &clk_rcg2_ops,
 693         },
 694 };
 695
 696 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
 697         .cmd_rcgr = 0x06014,
 698         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 699         .mnd_width = 8,
 700         .hid_width = 5,
 701         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 702         .clkr.hw.init = &(struct clk_init_data){
 703                 .name = "blsp1_qup5_spi_apps_clk_src",
 704                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 705                 .num_parents = 3,
 706                 .ops = &clk_rcg2_ops,
 707         },
 708 };
 709
 710 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
 711         .cmd_rcgr = 0x07000,
 712         .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
 713         .hid_width = 5,
 714         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 715         .clkr.hw.init = &(struct clk_init_data){
 716                 .name = "blsp1_qup6_i2c_apps_clk_src",
 717                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 718                 .num_parents = 3,
 719                 .ops = &clk_rcg2_ops,
 720         },
 721 };
 722
 723 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
 724         .cmd_rcgr = 0x07014,
 725         .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
 726         .mnd_width = 8,
 727         .hid_width = 5,
 728         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 729         .clkr.hw.init = &(struct clk_init_data){
 730                 .name = "blsp1_qup6_spi_apps_clk_src",
 731                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 732                 .num_parents = 3,
 733                 .ops = &clk_rcg2_ops,
 734         },
 735 };
 736
 737 static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
 738         F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
 739         F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
 740         F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
 741         F(16000000, P_GPLL0_DIV2, 5, 1, 5),
 742         F(19200000, P_XO, 1, 0, 0),
 743         F(24000000, P_GPLL0, 1, 3, 100),
 744         F(25000000, P_GPLL0, 16, 1, 2),
 745         F(32000000, P_GPLL0, 1, 1, 25),
 746         F(40000000, P_GPLL0, 1, 1, 20),
 747         F(46400000, P_GPLL0, 1, 29, 500),
 748         F(48000000, P_GPLL0, 1, 3, 50),
 749         F(51200000, P_GPLL0, 1, 8, 125),
 750         F(56000000, P_GPLL0, 1, 7, 100),
 751         F(58982400, P_GPLL0, 1, 1152, 15625),
 752         F(60000000, P_GPLL0, 1, 3, 40),
 753         F(64000000, P_GPLL0, 12.5, 1, 1),
 754         { }
 755 };
 756
 757 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
 758         .cmd_rcgr = 0x02044,
 759         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 760         .mnd_width = 16,
 761         .hid_width = 5,
 762         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 763         .clkr.hw.init = &(struct clk_init_data){
 764                 .name = "blsp1_uart1_apps_clk_src",
 765                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 766                 .num_parents = 3,
 767                 .ops = &clk_rcg2_ops,
 768         },
 769 };
 770
 771 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
 772         .cmd_rcgr = 0x03034,
 773         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 774         .mnd_width = 16,
 775         .hid_width = 5,
 776         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 777         .clkr.hw.init = &(struct clk_init_data){
 778                 .name = "blsp1_uart2_apps_clk_src",
 779                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 780                 .num_parents = 3,
 781                 .ops = &clk_rcg2_ops,
 782         },
 783 };
 784
 785 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
 786         .cmd_rcgr = 0x04034,
 787         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 788         .mnd_width = 16,
 789         .hid_width = 5,
 790         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 791         .clkr.hw.init = &(struct clk_init_data){
 792                 .name = "blsp1_uart3_apps_clk_src",
 793                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 794                 .num_parents = 3,
 795                 .ops = &clk_rcg2_ops,
 796         },
 797 };
 798
 799 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
 800         .cmd_rcgr = 0x05034,
 801         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 802         .mnd_width = 16,
 803         .hid_width = 5,
 804         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 805         .clkr.hw.init = &(struct clk_init_data){
 806                 .name = "blsp1_uart4_apps_clk_src",
 807                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 808                 .num_parents = 3,
 809                 .ops = &clk_rcg2_ops,
 810         },
 811 };
 812
 813 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
 814         .cmd_rcgr = 0x06034,
 815         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 816         .mnd_width = 16,
 817         .hid_width = 5,
 818         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 819         .clkr.hw.init = &(struct clk_init_data){
 820                 .name = "blsp1_uart5_apps_clk_src",
 821                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 822                 .num_parents = 3,
 823                 .ops = &clk_rcg2_ops,
 824         },
 825 };
 826
 827 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
 828         .cmd_rcgr = 0x07034,
 829         .freq_tbl = ftbl_blsp1_uart_apps_clk_src,
 830         .mnd_width = 16,
 831         .hid_width = 5,
 832         .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
 833         .clkr.hw.init = &(struct clk_init_data){
 834                 .name = "blsp1_uart6_apps_clk_src",
 835                 .parent_names = gcc_xo_gpll0_gpll0_out_main_div2,
 836                 .num_parents = 3,
 837                 .ops = &clk_rcg2_ops,
 838         },
 839 };
 840
 841 static const struct freq_tbl ftbl_pcie_axi_clk_src[] = {
 842         F(19200000, P_XO, 1, 0, 0),
 843         F(200000000, P_GPLL0, 4, 0, 0),
 844         { }
 845 };
 846
 847 static struct clk_rcg2 pcie0_axi_clk_src = {
 848         .cmd_rcgr = 0x75054,
 849         .freq_tbl = ftbl_pcie_axi_clk_src,
 850         .hid_width = 5,
 851         .parent_map = gcc_xo_gpll0_map,
 852         .clkr.hw.init = &(struct clk_init_data){
 853                 .name = "pcie0_axi_clk_src",
 854                 .parent_names = gcc_xo_gpll0,
 855                 .num_parents = 2,
 856                 .ops = &clk_rcg2_ops,
 857         },
 858 };
 859
 860 static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
 861         F(19200000, P_XO, 1, 0, 0),
 862 };
 863
 864 static struct clk_rcg2 pcie0_aux_clk_src = {
 865         .cmd_rcgr = 0x75024,
 866         .freq_tbl = ftbl_pcie_aux_clk_src,
 867         .mnd_width = 16,
 868         .hid_width = 5,
 869         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 870         .clkr.hw.init = &(struct clk_init_data){
 871                 .name = "pcie0_aux_clk_src",
 872                 .parent_names = gcc_xo_gpll0_sleep_clk,
 873                 .num_parents = 3,
 874                 .ops = &clk_rcg2_ops,
 875         },
 876 };
 877
 878 static struct clk_regmap_mux pcie0_pipe_clk_src = {
 879         .reg = 0x7501c,
 880         .shift = 8,
 881         .width = 2,
 882         .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,
 883         .clkr = {
 884                 .hw.init = &(struct clk_init_data){
 885                         .name = "pcie0_pipe_clk_src",
 886                         .parent_names = gcc_pcie20_phy0_pipe_clk_xo,
 887                         .num_parents = 2,
 888                         .ops = &clk_regmap_mux_closest_ops,
 889                         .flags = CLK_SET_RATE_PARENT,
 890                 },
 891         },
 892 };
 893
 894 static struct clk_rcg2 pcie1_axi_clk_src = {
 895         .cmd_rcgr = 0x76054,
 896         .freq_tbl = ftbl_pcie_axi_clk_src,
 897         .hid_width = 5,
 898         .parent_map = gcc_xo_gpll0_map,
 899         .clkr.hw.init = &(struct clk_init_data){
 900                 .name = "pcie1_axi_clk_src",
 901                 .parent_names = gcc_xo_gpll0,
 902                 .num_parents = 2,
 903                 .ops = &clk_rcg2_ops,
 904         },
 905 };
 906
 907 static struct clk_rcg2 pcie1_aux_clk_src = {
 908         .cmd_rcgr = 0x76024,
 909         .freq_tbl = ftbl_pcie_aux_clk_src,
 910         .mnd_width = 16,
 911         .hid_width = 5,
 912         .parent_map = gcc_xo_gpll0_sleep_clk_map,
 913         .clkr.hw.init = &(struct clk_init_data){
 914                 .name = "pcie1_aux_clk_src",
 915                 .parent_names = gcc_xo_gpll0_sleep_clk,
 916                 .num_parents = 3,
 917                 .ops = &clk_rcg2_ops,
 918         },
 919 };
 920
 921 static struct clk_regmap_mux pcie1_pipe_clk_src = {
 922         .reg = 0x7601c,
 923         .shift = 8,
 924         .width = 2,
 925         .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map,
 926         .clkr = {
 927                 .hw.init = &(struct clk_init_data){
 928                         .name = "pcie1_pipe_clk_src",
 929                         .parent_names = gcc_pcie20_phy1_pipe_clk_xo,
 930                         .num_parents = 2,
 931                         .ops = &clk_regmap_mux_closest_ops,
 932                         .flags = CLK_SET_RATE_PARENT,
 933                 },
 934         },
 935 };
 936
 937 static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
 938         F(144000, P_XO, 16, 3, 25),
 939         F(400000, P_XO, 12, 1, 4),
 940         F(24000000, P_GPLL2, 12, 1, 4),
 941         F(48000000, P_GPLL2, 12, 1, 2),
 942         F(96000000, P_GPLL2, 12, 0, 0),
 943         F(177777778, P_GPLL0, 4.5, 0, 0),
 944         F(192000000, P_GPLL2, 6, 0, 0),
 945         F(384000000, P_GPLL2, 3, 0, 0),
 946         { }
 947 };
 948
 949 static struct clk_rcg2 sdcc1_apps_clk_src = {
 950         .cmd_rcgr = 0x42004,
 951         .freq_tbl = ftbl_sdcc_apps_clk_src,
 952         .mnd_width = 8,
 953         .hid_width = 5,
 954         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 955         .clkr.hw.init = &(struct clk_init_data){
 956                 .name = "sdcc1_apps_clk_src",
 957                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 958                 .num_parents = 4,
 959                 .ops = &clk_rcg2_ops,
 960         },
 961 };
 962
 963 static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
 964         F(19200000, P_XO, 1, 0, 0),
 965         F(160000000, P_GPLL0, 5, 0, 0),
 966         F(308570000, P_GPLL6, 3.5, 0, 0),
 967 };
 968
 969 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 970         .cmd_rcgr = 0x5d000,
 971         .freq_tbl = ftbl_sdcc_ice_core_clk_src,
 972         .mnd_width = 8,
 973         .hid_width = 5,
 974         .parent_map = gcc_xo_gpll0_gpll6_gpll0_div2_map,
 975         .clkr.hw.init = &(struct clk_init_data){
 976                 .name = "sdcc1_ice_core_clk_src",
 977                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_div2,
 978                 .num_parents = 4,
 979                 .ops = &clk_rcg2_ops,
 980         },
 981 };
 982
 983 static struct clk_rcg2 sdcc2_apps_clk_src = {
 984         .cmd_rcgr = 0x43004,
 985         .freq_tbl = ftbl_sdcc_apps_clk_src,
 986         .mnd_width = 8,
 987         .hid_width = 5,
 988         .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
 989         .clkr.hw.init = &(struct clk_init_data){
 990                 .name = "sdcc2_apps_clk_src",
 991                 .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
 992                 .num_parents = 4,
 993                 .ops = &clk_rcg2_ops,
 994         },
 995 };
 996
 997 static const struct freq_tbl ftbl_usb_master_clk_src[] = {
 998         F(80000000, P_GPLL0_DIV2, 5, 0, 0),
 999         F(100000000, P_GPLL0, 8, 0, 0),
1000         F(133330000, P_GPLL0, 6, 0, 0),
1001         { }
1002 };
1003
1004 static struct clk_rcg2 usb0_master_clk_src = {
1005         .cmd_rcgr = 0x3e00c,
1006         .freq_tbl = ftbl_usb_master_clk_src,
1007         .mnd_width = 8,
1008         .hid_width = 5,
1009         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1010         .clkr.hw.init = &(struct clk_init_data){
1011                 .name = "usb0_master_clk_src",
1012                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1013                 .num_parents = 3,
1014                 .ops = &clk_rcg2_ops,
1015         },
1016 };
1017
1018 static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
1019         F(19200000, P_XO, 1, 0, 0),
1020         { }
1021 };
1022
1023 static struct clk_rcg2 usb0_aux_clk_src = {
1024         .cmd_rcgr = 0x3e05c,
1025         .freq_tbl = ftbl_usb_aux_clk_src,
1026         .mnd_width = 16,
1027         .hid_width = 5,
1028         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1029         .clkr.hw.init = &(struct clk_init_data){
1030                 .name = "usb0_aux_clk_src",
1031                 .parent_names = gcc_xo_gpll0_sleep_clk,
1032                 .num_parents = 3,
1033                 .ops = &clk_rcg2_ops,
1034         },
1035 };
1036
1037 static const struct freq_tbl ftbl_usb_mock_utmi_clk_src[] = {
1038         F(19200000, P_XO, 1, 0, 0),
1039         F(20000000, P_GPLL6, 6, 1, 9),
1040         F(60000000, P_GPLL6, 6, 1, 3),
1041         { }
1042 };
1043
1044 static struct clk_rcg2 usb0_mock_utmi_clk_src = {
1045         .cmd_rcgr = 0x3e020,
1046         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1047         .mnd_width = 8,
1048         .hid_width = 5,
1049         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1050         .clkr.hw.init = &(struct clk_init_data){
1051                 .name = "usb0_mock_utmi_clk_src",
1052                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1053                 .num_parents = 4,
1054                 .ops = &clk_rcg2_ops,
1055         },
1056 };
1057
1058 static struct clk_regmap_mux usb0_pipe_clk_src = {
1059         .reg = 0x3e048,
1060         .shift = 8,
1061         .width = 2,
1062         .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
1063         .clkr = {
1064                 .hw.init = &(struct clk_init_data){
1065                         .name = "usb0_pipe_clk_src",
1066                         .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo,
1067                         .num_parents = 2,
1068                         .ops = &clk_regmap_mux_closest_ops,
1069                         .flags = CLK_SET_RATE_PARENT,
1070                 },
1071         },
1072 };
1073
1074 static struct clk_rcg2 usb1_master_clk_src = {
1075         .cmd_rcgr = 0x3f00c,
1076         .freq_tbl = ftbl_usb_master_clk_src,
1077         .mnd_width = 8,
1078         .hid_width = 5,
1079         .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
1080         .clkr.hw.init = &(struct clk_init_data){
1081                 .name = "usb1_master_clk_src",
1082                 .parent_names = gcc_xo_gpll0_out_main_div2_gpll0,
1083                 .num_parents = 3,
1084                 .ops = &clk_rcg2_ops,
1085         },
1086 };
1087
1088 static struct clk_rcg2 usb1_aux_clk_src = {
1089         .cmd_rcgr = 0x3f05c,
1090         .freq_tbl = ftbl_usb_aux_clk_src,
1091         .mnd_width = 16,
1092         .hid_width = 5,
1093         .parent_map = gcc_xo_gpll0_sleep_clk_map,
1094         .clkr.hw.init = &(struct clk_init_data){
1095                 .name = "usb1_aux_clk_src",
1096                 .parent_names = gcc_xo_gpll0_sleep_clk,
1097                 .num_parents = 3,
1098                 .ops = &clk_rcg2_ops,
1099         },
1100 };
1101
1102 static struct clk_rcg2 usb1_mock_utmi_clk_src = {
1103         .cmd_rcgr = 0x3f020,
1104         .freq_tbl = ftbl_usb_mock_utmi_clk_src,
1105         .mnd_width = 8,
1106         .hid_width = 5,
1107         .parent_map = gcc_xo_gpll6_gpll0_gpll0_out_main_div2_map,
1108         .clkr.hw.init = &(struct clk_init_data){
1109                 .name = "usb1_mock_utmi_clk_src",
1110                 .parent_names = gcc_xo_gpll6_gpll0_gpll0_out_main_div2,
1111                 .num_parents = 4,
1112                 .ops = &clk_rcg2_ops,
1113         },
1114 };
1115
1116 static struct clk_regmap_mux usb1_pipe_clk_src = {
1117         .reg = 0x3f048,
1118         .shift = 8,
1119         .width = 2,
1120         .parent_map = gcc_usb3phy_1_cc_pipe_clk_xo_map,
1121         .clkr = {
1122                 .hw.init = &(struct clk_init_data){
1123                         .name = "usb1_pipe_clk_src",
1124                         .parent_names = gcc_usb3phy_1_cc_pipe_clk_xo,
1125                         .num_parents = 2,
1126                         .ops = &clk_regmap_mux_closest_ops,
1127                         .flags = CLK_SET_RATE_PARENT,
1128                 },
1129         },
1130 };
1131
1132 static struct clk_branch gcc_xo_clk_src = {
1133         .halt_reg = 0x30018,
1134         .clkr = {
1135                 .enable_reg = 0x30018,
1136                 .enable_mask = BIT(1),
1137                 .hw.init = &(struct clk_init_data){
1138                         .name = "gcc_xo_clk_src",
1139                         .parent_names = (const char *[]){
1140                                 "xo"
1141                         },
1142                         .num_parents = 1,
1143                         .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1144                         .ops = &clk_branch2_ops,
1145                 },
1146         },
1147 };
1148
1149 static struct clk_fixed_factor gcc_xo_div4_clk_src = {
1150         .mult = 1,
1151         .div = 4,
1152         .hw.init = &(struct clk_init_data){
1153                 .name = "gcc_xo_div4_clk_src",
1154                 .parent_names = (const char *[]){
1155                         "gcc_xo_clk_src"
1156                 },
1157                 .num_parents = 1,
1158                 .ops = &clk_fixed_factor_ops,
1159                 .flags = CLK_SET_RATE_PARENT,
1160         },
1161 };
1162
1163 static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
1164         F(19200000, P_XO, 1, 0, 0),
1165         F(50000000, P_GPLL0_DIV2, 8, 0, 0),
1166         F(100000000, P_GPLL0, 8, 0, 0),
1167         F(133333333, P_GPLL0, 6, 0, 0),
1168         F(160000000, P_GPLL0, 5, 0, 0),
1169         F(200000000, P_GPLL0, 4, 0, 0),
1170         F(266666667, P_GPLL0, 3, 0, 0),
1171         { }
1172 };
1173
1174 static struct clk_rcg2 system_noc_bfdcd_clk_src = {
1175         .cmd_rcgr = 0x26004,
1176         .freq_tbl = ftbl_system_noc_bfdcd_clk_src,
1177         .hid_width = 5,
1178         .parent_map = gcc_xo_gpll0_gpll6_gpll0_out_main_div2_map,
1179         .clkr.hw.init = &(struct clk_init_data){
1180                 .name = "system_noc_bfdcd_clk_src",
1181                 .parent_names = gcc_xo_gpll0_gpll6_gpll0_out_main_div2,
1182                 .num_parents = 4,
1183                 .ops = &clk_rcg2_ops,
1184                 .flags = CLK_IS_CRITICAL,
1185         },
1186 };
1187
1188 static struct clk_fixed_factor system_noc_clk_src = {
1189         .mult = 1,
1190         .div = 1,
1191         .hw.init = &(struct clk_init_data){
1192                 .name = "system_noc_clk_src",
1193                 .parent_names = (const char *[]){
1194                         "system_noc_bfdcd_clk_src"
1195                 },
1196                 .num_parents = 1,
1197                 .ops = &clk_fixed_factor_ops,
1198                 .flags = CLK_SET_RATE_PARENT,
1199         },
1200 };
1201
1202 static const struct freq_tbl ftbl_nss_ce_clk_src[] = {
1203         F(19200000, P_XO, 1, 0, 0),
1204         F(200000000, P_GPLL0, 4, 0, 0),
1205         { }
1206 };
1207
1208 static struct clk_rcg2 nss_ce_clk_src = {
1209         .cmd_rcgr = 0x68098,
1210         .freq_tbl = ftbl_nss_ce_clk_src,
1211         .hid_width = 5,
1212         .parent_map = gcc_xo_gpll0_map,
1213         .clkr.hw.init = &(struct clk_init_data){
1214                 .name = "nss_ce_clk_src",
1215                 .parent_names = gcc_xo_gpll0,
1216                 .num_parents = 2,
1217                 .ops = &clk_rcg2_ops,
1218         },
1219 };
1220
1221 static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
1222         F(19200000, P_XO, 1, 0, 0),
1223         F(461500000, P_BIAS_PLL_NSS_NOC, 1, 0, 0),
1224         { }
1225 };
1226
1227 static struct clk_rcg2 nss_noc_bfdcd_clk_src = {
1228         .cmd_rcgr = 0x68088,
1229         .freq_tbl = ftbl_nss_noc_bfdcd_clk_src,
1230         .hid_width = 5,
1231         .parent_map = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2_map,
1232         .clkr.hw.init = &(struct clk_init_data){
1233                 .name = "nss_noc_bfdcd_clk_src",
1234                 .parent_names = gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2,
1235                 .num_parents = 4,
1236                 .ops = &clk_rcg2_ops,
1237         },
1238 };
1239
1240 static struct clk_fixed_factor nss_noc_clk_src = {
1241         .mult = 1,
1242         .div = 1,
1243         .hw.init = &(struct clk_init_data){
1244                 .name = "nss_noc_clk_src",
1245                 .parent_names = (const char *[]){
1246                         "nss_noc_bfdcd_clk_src"
1247                 },
1248                 .num_parents = 1,
1249                 .ops = &clk_fixed_factor_ops,
1250                 .flags = CLK_SET_RATE_PARENT,
1251         },
1252 };
1253
1254 static const struct freq_tbl ftbl_nss_crypto_clk_src[] = {
1255         F(19200000, P_XO, 1, 0, 0),
1256         F(600000000, P_NSS_CRYPTO_PLL, 1, 0, 0),
1257         { }
1258 };
1259
1260 static struct clk_rcg2 nss_crypto_clk_src = {
1261         .cmd_rcgr = 0x68144,
1262         .freq_tbl = ftbl_nss_crypto_clk_src,
1263         .mnd_width = 16,
1264         .hid_width = 5,
1265         .parent_map = gcc_xo_nss_crypto_pll_gpll0_map,
1266         .clkr.hw.init = &(struct clk_init_data){
1267                 .name = "nss_crypto_clk_src",
1268                 .parent_names = gcc_xo_nss_crypto_pll_gpll0,
1269                 .num_parents = 3,
1270                 .ops = &clk_rcg2_ops,
1271         },
1272 };
1273
1274 static const struct freq_tbl ftbl_nss_ubi_clk_src[] = {
1275         F(19200000, P_XO, 1, 0, 0),
1276         F(187200000, P_UBI32_PLL, 8, 0, 0),
1277         F(748800000, P_UBI32_PLL, 2, 0, 0),
1278         F(1497600000, P_UBI32_PLL, 1, 0, 0),
1279         F(1689600000, P_UBI32_PLL, 1, 0, 0),
1280         { }
1281 };
1282
1283 static struct clk_rcg2 nss_ubi0_clk_src = {
1284         .cmd_rcgr = 0x68104,
1285         .freq_tbl = ftbl_nss_ubi_clk_src,
1286         .hid_width = 5,
1287         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1288         .clkr.hw.init = &(struct clk_init_data){
1289                 .name = "nss_ubi0_clk_src",
1290                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1291                 .num_parents = 6,
1292                 .ops = &clk_rcg2_ops,
1293                 .flags = CLK_SET_RATE_PARENT,
1294         },
1295 };
1296
1297 static struct clk_regmap_div nss_ubi0_div_clk_src = {
1298         .reg = 0x68118,
1299         .shift = 0,
1300         .width = 4,
1301         .clkr = {
1302                 .hw.init = &(struct clk_init_data){
1303                         .name = "nss_ubi0_div_clk_src",
1304                         .parent_names = (const char *[]){
1305                                 "nss_ubi0_clk_src"
1306                         },
1307                         .num_parents = 1,
1308                         .ops = &clk_regmap_div_ro_ops,
1309                         .flags = CLK_SET_RATE_PARENT,
1310                 },
1311         },
1312 };
1313
1314 static struct clk_rcg2 nss_ubi1_clk_src = {
1315         .cmd_rcgr = 0x68124,
1316         .freq_tbl = ftbl_nss_ubi_clk_src,
1317         .hid_width = 5,
1318         .parent_map = gcc_xo_ubi32_gpll0_gpll2_gpll4_gpll6_map,
1319         .clkr.hw.init = &(struct clk_init_data){
1320                 .name = "nss_ubi1_clk_src",
1321                 .parent_names = gcc_xo_ubi32_pll_gpll0_gpll2_gpll4_gpll6,
1322                 .num_parents = 6,
1323                 .ops = &clk_rcg2_ops,
1324                 .flags = CLK_SET_RATE_PARENT,
1325         },
1326 };
1327
1328 static struct clk_regmap_div nss_ubi1_div_clk_src = {
1329         .reg = 0x68138,
1330         .shift = 0,
1331         .width = 4,
1332         .clkr = {
1333                 .hw.init = &(struct clk_init_data){
1334                         .name = "nss_ubi1_div_clk_src",
1335                         .parent_names = (const char *[]){
1336                                 "nss_ubi1_clk_src"
1337                         },
1338                         .num_parents = 1,
1339                         .ops = &clk_regmap_div_ro_ops,
1340                         .flags = CLK_SET_RATE_PARENT,
1341                 },
1342         },
1343 };
1344
1345 static const struct freq_tbl ftbl_ubi_mpt_clk_src[] = {
1346         F(19200000, P_XO, 1, 0, 0),
1347         F(25000000, P_GPLL0_DIV2, 16, 0, 0),
1348         { }
1349 };
1350
1351 static struct clk_rcg2 ubi_mpt_clk_src = {
1352         .cmd_rcgr = 0x68090,
1353         .freq_tbl = ftbl_ubi_mpt_clk_src,
1354         .hid_width = 5,
1355         .parent_map = gcc_xo_gpll0_out_main_div2_map,
1356         .clkr.hw.init = &(struct clk_init_data){
1357                 .name = "ubi_mpt_clk_src",
1358                 .parent_names = gcc_xo_gpll0_out_main_div2,
1359                 .num_parents = 2,
1360                 .ops = &clk_rcg2_ops,
1361         },
1362 };
1363
1364 static const struct freq_tbl ftbl_nss_imem_clk_src[] = {
1365         F(19200000, P_XO, 1, 0, 0),
1366         F(400000000, P_GPLL0, 2, 0, 0),
1367         { }
1368 };
1369
1370 static struct clk_rcg2 nss_imem_clk_src = {
1371         .cmd_rcgr = 0x68158,
1372         .freq_tbl = ftbl_nss_imem_clk_src,
1373         .hid_width = 5,
1374         .parent_map = gcc_xo_gpll0_gpll4_map,
1375         .clkr.hw.init = &(struct clk_init_data){
1376                 .name = "nss_imem_clk_src",
1377                 .parent_names = gcc_xo_gpll0_gpll4,
1378                 .num_parents = 3,
1379                 .ops = &clk_rcg2_ops,
1380         },
1381 };
1382
1383 static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
1384         F(19200000, P_XO, 1, 0, 0),
1385         F(300000000, P_BIAS_PLL, 1, 0, 0),
1386         { }
1387 };
1388
1389 static struct clk_rcg2 nss_ppe_clk_src = {
1390         .cmd_rcgr = 0x68080,
1391         .freq_tbl = ftbl_nss_ppe_clk_src,
1392         .hid_width = 5,
1393         .parent_map = gcc_xo_bias_gpll0_gpll4_nss_ubi32_map,
1394         .clkr.hw.init = &(struct clk_init_data){
1395                 .name = "nss_ppe_clk_src",
1396                 .parent_names = gcc_xo_bias_gpll0_gpll4_nss_ubi32,
1397                 .num_parents = 6,
1398                 .ops = &clk_rcg2_ops,
1399         },
1400 };
1401
1402 static struct clk_fixed_factor nss_ppe_cdiv_clk_src = {
1403         .mult = 1,
1404         .div = 4,
1405         .hw.init = &(struct clk_init_data){
1406                 .name = "nss_ppe_cdiv_clk_src",
1407                 .parent_names = (const char *[]){
1408                         "nss_ppe_clk_src"
1409                 },
1410                 .num_parents = 1,
1411                 .ops = &clk_fixed_factor_ops,
1412                 .flags = CLK_SET_RATE_PARENT,
1413         },
1414 };
1415
1416 static struct clk_branch gcc_blsp1_ahb_clk = {
1417         .halt_reg = 0x01008,
1418         .clkr = {
1419                 .enable_reg = 0x01008,
1420                 .enable_mask = BIT(0),
1421                 .hw.init = &(struct clk_init_data){
1422                         .name = "gcc_blsp1_ahb_clk",
1423                         .parent_names = (const char *[]){
1424                                 "pcnoc_clk_src"
1425                         },
1426                         .num_parents = 1,
1427                         .flags = CLK_SET_RATE_PARENT,
1428                         .ops = &clk_branch2_ops,
1429                 },
1430         },
1431 };
1432
1433 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1434         .halt_reg = 0x02008,
1435         .clkr = {
1436                 .enable_reg = 0x02008,
1437                 .enable_mask = BIT(0),
1438                 .hw.init = &(struct clk_init_data){
1439                         .name = "gcc_blsp1_qup1_i2c_apps_clk",
1440                         .parent_names = (const char *[]){
1441                                 "blsp1_qup1_i2c_apps_clk_src"
1442                         },
1443                         .num_parents = 1,
1444                         .flags = CLK_SET_RATE_PARENT,
1445                         .ops = &clk_branch2_ops,
1446                 },
1447         },
1448 };
1449
1450 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1451         .halt_reg = 0x02004,
1452         .clkr = {
1453                 .enable_reg = 0x02004,
1454                 .enable_mask = BIT(0),
1455                 .hw.init = &(struct clk_init_data){
1456                         .name = "gcc_blsp1_qup1_spi_apps_clk",
1457                         .parent_names = (const char *[]){
1458                                 "blsp1_qup1_spi_apps_clk_src"
1459                         },
1460                         .num_parents = 1,
1461                         .flags = CLK_SET_RATE_PARENT,
1462                         .ops = &clk_branch2_ops,
1463                 },
1464         },
1465 };
1466
1467 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1468         .halt_reg = 0x03010,
1469         .clkr = {
1470                 .enable_reg = 0x03010,
1471                 .enable_mask = BIT(0),
1472                 .hw.init = &(struct clk_init_data){
1473                         .name = "gcc_blsp1_qup2_i2c_apps_clk",
1474                         .parent_names = (const char *[]){
1475                                 "blsp1_qup2_i2c_apps_clk_src"
1476                         },
1477                         .num_parents = 1,
1478                         .flags = CLK_SET_RATE_PARENT,
1479                         .ops = &clk_branch2_ops,
1480                 },
1481         },
1482 };
1483
1484 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1485         .halt_reg = 0x0300c,
1486         .clkr = {
1487                 .enable_reg = 0x0300c,
1488                 .enable_mask = BIT(0),
1489                 .hw.init = &(struct clk_init_data){
1490                         .name = "gcc_blsp1_qup2_spi_apps_clk",
1491                         .parent_names = (const char *[]){
1492                                 "blsp1_qup2_spi_apps_clk_src"
1493                         },
1494                         .num_parents = 1,
1495                         .flags = CLK_SET_RATE_PARENT,
1496                         .ops = &clk_branch2_ops,
1497                 },
1498         },
1499 };
1500
1501 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1502         .halt_reg = 0x04010,
1503         .clkr = {
1504                 .enable_reg = 0x04010,
1505                 .enable_mask = BIT(0),
1506                 .hw.init = &(struct clk_init_data){
1507                         .name = "gcc_blsp1_qup3_i2c_apps_clk",
1508                         .parent_names = (const char *[]){
1509                                 "blsp1_qup3_i2c_apps_clk_src"
1510                         },
1511                         .num_parents = 1,
1512                         .flags = CLK_SET_RATE_PARENT,
1513                         .ops = &clk_branch2_ops,
1514                 },
1515         },
1516 };
1517
1518 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1519         .halt_reg = 0x0400c,
1520         .clkr = {
1521                 .enable_reg = 0x0400c,
1522                 .enable_mask = BIT(0),
1523                 .hw.init = &(struct clk_init_data){
1524                         .name = "gcc_blsp1_qup3_spi_apps_clk",
1525                         .parent_names = (const char *[]){
1526                                 "blsp1_qup3_spi_apps_clk_src"
1527                         },
1528                         .num_parents = 1,
1529                         .flags = CLK_SET_RATE_PARENT,
1530                         .ops = &clk_branch2_ops,
1531                 },
1532         },
1533 };
1534
1535 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1536         .halt_reg = 0x05010,
1537         .clkr = {
1538                 .enable_reg = 0x05010,
1539                 .enable_mask = BIT(0),
1540                 .hw.init = &(struct clk_init_data){
1541                         .name = "gcc_blsp1_qup4_i2c_apps_clk",
1542                         .parent_names = (const char *[]){
1543                                 "blsp1_qup4_i2c_apps_clk_src"
1544                         },
1545                         .num_parents = 1,
1546                         .flags = CLK_SET_RATE_PARENT,
1547                         .ops = &clk_branch2_ops,
1548                 },
1549         },
1550 };
1551
1552 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1553         .halt_reg = 0x0500c,
1554         .clkr = {
1555                 .enable_reg = 0x0500c,
1556                 .enable_mask = BIT(0),
1557                 .hw.init = &(struct clk_init_data){
1558                         .name = "gcc_blsp1_qup4_spi_apps_clk",
1559                         .parent_names = (const char *[]){
1560                                 "blsp1_qup4_spi_apps_clk_src"
1561                         },
1562                         .num_parents = 1,
1563                         .flags = CLK_SET_RATE_PARENT,
1564                         .ops = &clk_branch2_ops,
1565                 },
1566         },
1567 };
1568
1569 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1570         .halt_reg = 0x06010,
1571         .clkr = {
1572                 .enable_reg = 0x06010,
1573                 .enable_mask = BIT(0),
1574                 .hw.init = &(struct clk_init_data){
1575                         .name = "gcc_blsp1_qup5_i2c_apps_clk",
1576                         .parent_names = (const char *[]){
1577                                 "blsp1_qup5_i2c_apps_clk_src"
1578                         },
1579                         .num_parents = 1,
1580                         .flags = CLK_SET_RATE_PARENT,
1581                         .ops = &clk_branch2_ops,
1582                 },
1583         },
1584 };
1585
1586 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1587         .halt_reg = 0x0600c,
1588         .clkr = {
1589                 .enable_reg = 0x0600c,
1590                 .enable_mask = BIT(0),
1591                 .hw.init = &(struct clk_init_data){
1592                         .name = "gcc_blsp1_qup5_spi_apps_clk",
1593                         .parent_names = (const char *[]){
1594                                 "blsp1_qup5_spi_apps_clk_src"
1595                         },
1596                         .num_parents = 1,
1597                         .flags = CLK_SET_RATE_PARENT,
1598                         .ops = &clk_branch2_ops,
1599                 },
1600         },
1601 };
1602
1603 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1604         .halt_reg = 0x07010,
1605         .clkr = {
1606                 .enable_reg = 0x07010,
1607                 .enable_mask = BIT(0),
1608                 .hw.init = &(struct clk_init_data){
1609                         .name = "gcc_blsp1_qup6_i2c_apps_clk",
1610                         .parent_names = (const char *[]){
1611                                 "blsp1_qup6_i2c_apps_clk_src"
1612                         },
1613                         .num_parents = 1,
1614                         .flags = CLK_SET_RATE_PARENT,
1615                         .ops = &clk_branch2_ops,
1616                 },
1617         },
1618 };
1619
1620 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1621         .halt_reg = 0x0700c,
1622         .clkr = {
1623                 .enable_reg = 0x0700c,
1624                 .enable_mask = BIT(0),
1625                 .hw.init = &(struct clk_init_data){
1626                         .name = "gcc_blsp1_qup6_spi_apps_clk",
1627                         .parent_names = (const char *[]){
1628                                 "blsp1_qup6_spi_apps_clk_src"
1629                         },
1630                         .num_parents = 1,
1631                         .flags = CLK_SET_RATE_PARENT,
1632                         .ops = &clk_branch2_ops,
1633                 },
1634         },
1635 };
1636
1637 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1638         .halt_reg = 0x0203c,
1639         .clkr = {
1640                 .enable_reg = 0x0203c,
1641                 .enable_mask = BIT(0),
1642                 .hw.init = &(struct clk_init_data){
1643                         .name = "gcc_blsp1_uart1_apps_clk",
1644                         .parent_names = (const char *[]){
1645                                 "blsp1_uart1_apps_clk_src"
1646                         },
1647                         .num_parents = 1,
1648                         .flags = CLK_SET_RATE_PARENT,
1649                         .ops = &clk_branch2_ops,
1650                 },
1651         },
1652 };
1653
1654 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1655         .halt_reg = 0x0302c,
1656         .clkr = {
1657                 .enable_reg = 0x0302c,
1658                 .enable_mask = BIT(0),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "gcc_blsp1_uart2_apps_clk",
1661                         .parent_names = (const char *[]){
1662                                 "blsp1_uart2_apps_clk_src"
1663                         },
1664                         .num_parents = 1,
1665                         .flags = CLK_SET_RATE_PARENT,
1666                         .ops = &clk_branch2_ops,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1672         .halt_reg = 0x0402c,
1673         .clkr = {
1674                 .enable_reg = 0x0402c,
1675                 .enable_mask = BIT(0),
1676                 .hw.init = &(struct clk_init_data){
1677                         .name = "gcc_blsp1_uart3_apps_clk",
1678                         .parent_names = (const char *[]){
1679                                 "blsp1_uart3_apps_clk_src"
1680                         },
1681                         .num_parents = 1,
1682                         .flags = CLK_SET_RATE_PARENT,
1683                         .ops = &clk_branch2_ops,
1684                 },
1685         },
1686 };
1687
1688 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1689         .halt_reg = 0x0502c,
1690         .clkr = {
1691                 .enable_reg = 0x0502c,
1692                 .enable_mask = BIT(0),
1693                 .hw.init = &(struct clk_init_data){
1694                         .name = "gcc_blsp1_uart4_apps_clk",
1695                         .parent_names = (const char *[]){
1696                                 "blsp1_uart4_apps_clk_src"
1697                         },
1698                         .num_parents = 1,
1699                         .flags = CLK_SET_RATE_PARENT,
1700                         .ops = &clk_branch2_ops,
1701                 },
1702         },
1703 };
1704
1705 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1706         .halt_reg = 0x0602c,
1707         .clkr = {
1708                 .enable_reg = 0x0602c,
1709                 .enable_mask = BIT(0),
1710                 .hw.init = &(struct clk_init_data){
1711                         .name = "gcc_blsp1_uart5_apps_clk",
1712                         .parent_names = (const char *[]){
1713                                 "blsp1_uart5_apps_clk_src"
1714                         },
1715                         .num_parents = 1,
1716                         .flags = CLK_SET_RATE_PARENT,
1717                         .ops = &clk_branch2_ops,
1718                 },
1719         },
1720 };
1721
1722 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1723         .halt_reg = 0x0702c,
1724         .clkr = {
1725                 .enable_reg = 0x0702c,
1726                 .enable_mask = BIT(0),
1727                 .hw.init = &(struct clk_init_data){
1728                         .name = "gcc_blsp1_uart6_apps_clk",
1729                         .parent_names = (const char *[]){
1730                                 "blsp1_uart6_apps_clk_src"
1731                         },
1732                         .num_parents = 1,
1733                         .flags = CLK_SET_RATE_PARENT,
1734                         .ops = &clk_branch2_ops,
1735                 },
1736         },
1737 };
1738
1739 static struct clk_branch gcc_prng_ahb_clk = {
1740         .halt_reg = 0x13004,
1741         .halt_check = BRANCH_HALT_VOTED,
1742         .clkr = {
1743                 .enable_reg = 0x0b004,
1744                 .enable_mask = BIT(8),
1745                 .hw.init = &(struct clk_init_data){
1746                         .name = "gcc_prng_ahb_clk",
1747                         .parent_names = (const char *[]){
1748                                 "pcnoc_clk_src"
1749                         },
1750                         .num_parents = 1,
1751                         .flags = CLK_SET_RATE_PARENT,
1752                         .ops = &clk_branch2_ops,
1753                 },
1754         },
1755 };
1756
1757 static struct clk_branch gcc_qpic_ahb_clk = {
1758         .halt_reg = 0x57024,
1759         .clkr = {
1760                 .enable_reg = 0x57024,
1761                 .enable_mask = BIT(0),
1762                 .hw.init = &(struct clk_init_data){
1763                         .name = "gcc_qpic_ahb_clk",
1764                         .parent_names = (const char *[]){
1765                                 "pcnoc_clk_src"
1766                         },
1767                         .num_parents = 1,
1768                         .flags = CLK_SET_RATE_PARENT,
1769                         .ops = &clk_branch2_ops,
1770                 },
1771         },
1772 };
1773
1774 static struct clk_branch gcc_qpic_clk = {
1775         .halt_reg = 0x57020,
1776         .clkr = {
1777                 .enable_reg = 0x57020,
1778                 .enable_mask = BIT(0),
1779                 .hw.init = &(struct clk_init_data){
1780                         .name = "gcc_qpic_clk",
1781                         .parent_names = (const char *[]){
1782                                 "pcnoc_clk_src"
1783                         },
1784                         .num_parents = 1,
1785                         .flags = CLK_SET_RATE_PARENT,
1786                         .ops = &clk_branch2_ops,
1787                 },
1788         },
1789 };
1790
1791 static struct clk_branch gcc_pcie0_ahb_clk = {
1792         .halt_reg = 0x75010,
1793         .clkr = {
1794                 .enable_reg = 0x75010,
1795                 .enable_mask = BIT(0),
1796                 .hw.init = &(struct clk_init_data){
1797                         .name = "gcc_pcie0_ahb_clk",
1798                         .parent_names = (const char *[]){
1799                                 "pcnoc_clk_src"
1800                         },
1801                         .num_parents = 1,
1802                         .flags = CLK_SET_RATE_PARENT,
1803                         .ops = &clk_branch2_ops,
1804                 },
1805         },
1806 };
1807
1808 static struct clk_branch gcc_pcie0_aux_clk = {
1809         .halt_reg = 0x75014,
1810         .clkr = {
1811                 .enable_reg = 0x75014,
1812                 .enable_mask = BIT(0),
1813                 .hw.init = &(struct clk_init_data){
1814                         .name = "gcc_pcie0_aux_clk",
1815                         .parent_names = (const char *[]){
1816                                 "pcie0_aux_clk_src"
1817                         },
1818                         .num_parents = 1,
1819                         .flags = CLK_SET_RATE_PARENT,
1820                         .ops = &clk_branch2_ops,
1821                 },
1822         },
1823 };
1824
1825 static struct clk_branch gcc_pcie0_axi_m_clk = {
1826         .halt_reg = 0x75008,
1827         .clkr = {
1828                 .enable_reg = 0x75008,
1829                 .enable_mask = BIT(0),
1830                 .hw.init = &(struct clk_init_data){
1831                         .name = "gcc_pcie0_axi_m_clk",
1832                         .parent_names = (const char *[]){
1833                                 "pcie0_axi_clk_src"
1834                         },
1835                         .num_parents = 1,
1836                         .flags = CLK_SET_RATE_PARENT,
1837                         .ops = &clk_branch2_ops,
1838                 },
1839         },
1840 };
1841
1842 static struct clk_branch gcc_pcie0_axi_s_clk = {
1843         .halt_reg = 0x7500c,
1844         .clkr = {
1845                 .enable_reg = 0x7500c,
1846                 .enable_mask = BIT(0),
1847                 .hw.init = &(struct clk_init_data){
1848                         .name = "gcc_pcie0_axi_s_clk",
1849                         .parent_names = (const char *[]){
1850                                 "pcie0_axi_clk_src"
1851                         },
1852                         .num_parents = 1,
1853                         .flags = CLK_SET_RATE_PARENT,
1854                         .ops = &clk_branch2_ops,
1855                 },
1856         },
1857 };
1858
1859 static struct clk_branch gcc_pcie0_pipe_clk = {
1860         .halt_reg = 0x75018,
1861         .halt_check = BRANCH_HALT_DELAY,
1862         .clkr = {
1863                 .enable_reg = 0x75018,
1864                 .enable_mask = BIT(0),
1865                 .hw.init = &(struct clk_init_data){
1866                         .name = "gcc_pcie0_pipe_clk",
1867                         .parent_names = (const char *[]){
1868                                 "pcie0_pipe_clk_src"
1869                         },
1870                         .num_parents = 1,
1871                         .flags = CLK_SET_RATE_PARENT,
1872                         .ops = &clk_branch2_ops,
1873                 },
1874         },
1875 };
1876
1877 static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {
1878         .halt_reg = 0x26048,
1879         .clkr = {
1880                 .enable_reg = 0x26048,
1881                 .enable_mask = BIT(0),
1882                 .hw.init = &(struct clk_init_data){
1883                         .name = "gcc_sys_noc_pcie0_axi_clk",
1884                         .parent_names = (const char *[]){
1885                                 "pcie0_axi_clk_src"
1886                         },
1887                         .num_parents = 1,
1888                         .flags = CLK_SET_RATE_PARENT,
1889                         .ops = &clk_branch2_ops,
1890                 },
1891         },
1892 };
1893
1894 static struct clk_branch gcc_pcie1_ahb_clk = {
1895         .halt_reg = 0x76010,
1896         .clkr = {
1897                 .enable_reg = 0x76010,
1898                 .enable_mask = BIT(0),
1899                 .hw.init = &(struct clk_init_data){
1900                         .name = "gcc_pcie1_ahb_clk",
1901                         .parent_names = (const char *[]){
1902                                 "pcnoc_clk_src"
1903                         },
1904                         .num_parents = 1,
1905                         .flags = CLK_SET_RATE_PARENT,
1906                         .ops = &clk_branch2_ops,
1907                 },
1908         },
1909 };
1910
1911 static struct clk_branch gcc_pcie1_aux_clk = {
1912         .halt_reg = 0x76014,
1913         .clkr = {
1914                 .enable_reg = 0x76014,
1915                 .enable_mask = BIT(0),
1916                 .hw.init = &(struct clk_init_data){
1917                         .name = "gcc_pcie1_aux_clk",
1918                         .parent_names = (const char *[]){
1919                                 "pcie1_aux_clk_src"
1920                         },
1921                         .num_parents = 1,
1922                         .flags = CLK_SET_RATE_PARENT,
1923                         .ops = &clk_branch2_ops,
1924                 },
1925         },
1926 };
1927
1928 static struct clk_branch gcc_pcie1_axi_m_clk = {
1929         .halt_reg = 0x76008,
1930         .clkr = {
1931                 .enable_reg = 0x76008,
1932                 .enable_mask = BIT(0),
1933                 .hw.init = &(struct clk_init_data){
1934                         .name = "gcc_pcie1_axi_m_clk",
1935                         .parent_names = (const char *[]){
1936                                 "pcie1_axi_clk_src"
1937                         },
1938                         .num_parents = 1,
1939                         .flags = CLK_SET_RATE_PARENT,
1940                         .ops = &clk_branch2_ops,
1941                 },
1942         },
1943 };
1944
1945 static struct clk_branch gcc_pcie1_axi_s_clk = {
1946         .halt_reg = 0x7600c,
1947         .clkr = {
1948                 .enable_reg = 0x7600c,
1949                 .enable_mask = BIT(0),
1950                 .hw.init = &(struct clk_init_data){
1951                         .name = "gcc_pcie1_axi_s_clk",
1952                         .parent_names = (const char *[]){
1953                                 "pcie1_axi_clk_src"
1954                         },
1955                         .num_parents = 1,
1956                         .flags = CLK_SET_RATE_PARENT,
1957                         .ops = &clk_branch2_ops,
1958                 },
1959         },
1960 };
1961
1962 static struct clk_branch gcc_pcie1_pipe_clk = {
1963         .halt_reg = 0x76018,
1964         .halt_check = BRANCH_HALT_DELAY,
1965         .clkr = {
1966                 .enable_reg = 0x76018,
1967                 .enable_mask = BIT(0),
1968                 .hw.init = &(struct clk_init_data){
1969                         .name = "gcc_pcie1_pipe_clk",
1970                         .parent_names = (const char *[]){
1971                                 "pcie1_pipe_clk_src"
1972                         },
1973                         .num_parents = 1,
1974                         .flags = CLK_SET_RATE_PARENT,
1975                         .ops = &clk_branch2_ops,
1976                 },
1977         },
1978 };
1979
1980 static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {
1981         .halt_reg = 0x2604c,
1982         .clkr = {
1983                 .enable_reg = 0x2604c,
1984                 .enable_mask = BIT(0),
1985                 .hw.init = &(struct clk_init_data){
1986                         .name = "gcc_sys_noc_pcie1_axi_clk",
1987                         .parent_names = (const char *[]){
1988                                 "pcie1_axi_clk_src"
1989                         },
1990                         .num_parents = 1,
1991                         .flags = CLK_SET_RATE_PARENT,
1992                         .ops = &clk_branch2_ops,
1993                 },
1994         },
1995 };
1996
1997 static struct clk_branch gcc_usb0_aux_clk = {
1998         .halt_reg = 0x3e044,
1999         .clkr = {
2000                 .enable_reg = 0x3e044,
2001                 .enable_mask = BIT(0),
2002                 .hw.init = &(struct clk_init_data){
2003                         .name = "gcc_usb0_aux_clk",
2004                         .parent_names = (const char *[]){
2005                                 "usb0_aux_clk_src"
2006                         },
2007                         .num_parents = 1,
2008                         .flags = CLK_SET_RATE_PARENT,
2009                         .ops = &clk_branch2_ops,
2010                 },
2011         },
2012 };
2013
2014 static struct clk_branch gcc_sys_noc_usb0_axi_clk = {
2015         .halt_reg = 0x26040,
2016         .clkr = {
2017                 .enable_reg = 0x26040,
2018                 .enable_mask = BIT(0),
2019                 .hw.init = &(struct clk_init_data){
2020                         .name = "gcc_sys_noc_usb0_axi_clk",
2021                         .parent_names = (const char *[]){
2022                                 "usb0_master_clk_src"
2023                         },
2024                         .num_parents = 1,
2025                         .flags = CLK_SET_RATE_PARENT,
2026                         .ops = &clk_branch2_ops,
2027                 },
2028         },
2029 };
2030
2031 static struct clk_branch gcc_usb0_master_clk = {
2032         .halt_reg = 0x3e000,
2033         .clkr = {
2034                 .enable_reg = 0x3e000,
2035                 .enable_mask = BIT(0),
2036                 .hw.init = &(struct clk_init_data){
2037                         .name = "gcc_usb0_master_clk",
2038                         .parent_names = (const char *[]){
2039                                 "usb0_master_clk_src"
2040                         },
2041                         .num_parents = 1,
2042                         .flags = CLK_SET_RATE_PARENT,
2043                         .ops = &clk_branch2_ops,
2044                 },
2045         },
2046 };
2047
2048 static struct clk_branch gcc_usb0_mock_utmi_clk = {
2049         .halt_reg = 0x3e008,
2050         .clkr = {
2051                 .enable_reg = 0x3e008,
2052                 .enable_mask = BIT(0),
2053                 .hw.init = &(struct clk_init_data){
2054                         .name = "gcc_usb0_mock_utmi_clk",
2055                         .parent_names = (const char *[]){
2056                                 "usb0_mock_utmi_clk_src"
2057                         },
2058                         .num_parents = 1,
2059                         .flags = CLK_SET_RATE_PARENT,
2060                         .ops = &clk_branch2_ops,
2061                 },
2062         },
2063 };
2064
2065 static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
2066         .halt_reg = 0x3e080,
2067         .clkr = {
2068                 .enable_reg = 0x3e080,
2069                 .enable_mask = BIT(0),
2070                 .hw.init = &(struct clk_init_data){
2071                         .name = "gcc_usb0_phy_cfg_ahb_clk",
2072                         .parent_names = (const char *[]){
2073                                 "pcnoc_clk_src"
2074                         },
2075                         .num_parents = 1,
2076                         .flags = CLK_SET_RATE_PARENT,
2077                         .ops = &clk_branch2_ops,
2078                 },
2079         },
2080 };
2081
2082 static struct clk_branch gcc_usb0_pipe_clk = {
2083         .halt_reg = 0x3e040,
2084         .halt_check = BRANCH_HALT_DELAY,
2085         .clkr = {
2086                 .enable_reg = 0x3e040,
2087                 .enable_mask = BIT(0),
2088                 .hw.init = &(struct clk_init_data){
2089                         .name = "gcc_usb0_pipe_clk",
2090                         .parent_names = (const char *[]){
2091                                 "usb0_pipe_clk_src"
2092                         },
2093                         .num_parents = 1,
2094                         .flags = CLK_SET_RATE_PARENT,
2095                         .ops = &clk_branch2_ops,
2096                 },
2097         },
2098 };
2099
2100 static struct clk_branch gcc_usb0_sleep_clk = {
2101         .halt_reg = 0x3e004,
2102         .clkr = {
2103                 .enable_reg = 0x3e004,
2104                 .enable_mask = BIT(0),
2105                 .hw.init = &(struct clk_init_data){
2106                         .name = "gcc_usb0_sleep_clk",
2107                         .parent_names = (const char *[]){
2108                                 "gcc_sleep_clk_src"
2109                         },
2110                         .num_parents = 1,
2111                         .flags = CLK_SET_RATE_PARENT,
2112                         .ops = &clk_branch2_ops,
2113                 },
2114         },
2115 };
2116
2117 static struct clk_branch gcc_usb1_aux_clk = {
2118         .halt_reg = 0x3f044,
2119         .clkr = {
2120                 .enable_reg = 0x3f044,
2121                 .enable_mask = BIT(0),
2122                 .hw.init = &(struct clk_init_data){
2123                         .name = "gcc_usb1_aux_clk",
2124                         .parent_names = (const char *[]){
2125                                 "usb1_aux_clk_src"
2126                         },
2127                         .num_parents = 1,
2128                         .flags = CLK_SET_RATE_PARENT,
2129                         .ops = &clk_branch2_ops,
2130                 },
2131         },
2132 };
2133
2134 static struct clk_branch gcc_sys_noc_usb1_axi_clk = {
2135         .halt_reg = 0x26044,
2136         .clkr = {
2137                 .enable_reg = 0x26044,
2138                 .enable_mask = BIT(0),
2139                 .hw.init = &(struct clk_init_data){
2140                         .name = "gcc_sys_noc_usb1_axi_clk",
2141                         .parent_names = (const char *[]){
2142                                 "usb1_master_clk_src"
2143                         },
2144                         .num_parents = 1,
2145                         .flags = CLK_SET_RATE_PARENT,
2146                         .ops = &clk_branch2_ops,
2147                 },
2148         },
2149 };
2150
2151 static struct clk_branch gcc_usb1_master_clk = {
2152         .halt_reg = 0x3f000,
2153         .clkr = {
2154                 .enable_reg = 0x3f000,
2155                 .enable_mask = BIT(0),
2156                 .hw.init = &(struct clk_init_data){
2157                         .name = "gcc_usb1_master_clk",
2158                         .parent_names = (const char *[]){
2159                                 "usb1_master_clk_src"
2160                         },
2161                         .num_parents = 1,
2162                         .flags = CLK_SET_RATE_PARENT,
2163                         .ops = &clk_branch2_ops,
2164                 },
2165         },
2166 };
2167
2168 static struct clk_branch gcc_usb1_mock_utmi_clk = {
2169         .halt_reg = 0x3f008,
2170         .clkr = {
2171                 .enable_reg = 0x3f008,
2172                 .enable_mask = BIT(0),
2173                 .hw.init = &(struct clk_init_data){
2174                         .name = "gcc_usb1_mock_utmi_clk",
2175                         .parent_names = (const char *[]){
2176                                 "usb1_mock_utmi_clk_src"
2177                         },
2178                         .num_parents = 1,
2179                         .flags = CLK_SET_RATE_PARENT,
2180                         .ops = &clk_branch2_ops,
2181                 },
2182         },
2183 };
2184
2185 static struct clk_branch gcc_usb1_phy_cfg_ahb_clk = {
2186         .halt_reg = 0x3f080,
2187         .clkr = {
2188                 .enable_reg = 0x3f080,
2189                 .enable_mask = BIT(0),
2190                 .hw.init = &(struct clk_init_data){
2191                         .name = "gcc_usb1_phy_cfg_ahb_clk",
2192                         .parent_names = (const char *[]){
2193                                 "pcnoc_clk_src"
2194                         },
2195                         .num_parents = 1,
2196                         .flags = CLK_SET_RATE_PARENT,
2197                         .ops = &clk_branch2_ops,
2198                 },
2199         },
2200 };
2201
2202 static struct clk_branch gcc_usb1_pipe_clk = {
2203         .halt_reg = 0x3f040,
2204         .halt_check = BRANCH_HALT_DELAY,
2205         .clkr = {
2206                 .enable_reg = 0x3f040,
2207                 .enable_mask = BIT(0),
2208                 .hw.init = &(struct clk_init_data){
2209                         .name = "gcc_usb1_pipe_clk",
2210                         .parent_names = (const char *[]){
2211                                 "usb1_pipe_clk_src"
2212                         },
2213                         .num_parents = 1,
2214                         .flags = CLK_SET_RATE_PARENT,
2215                         .ops = &clk_branch2_ops,
2216                 },
2217         },
2218 };
2219
2220 static struct clk_branch gcc_usb1_sleep_clk = {
2221         .halt_reg = 0x3f004,
2222         .clkr = {
2223                 .enable_reg = 0x3f004,
2224                 .enable_mask = BIT(0),
2225                 .hw.init = &(struct clk_init_data){
2226                         .name = "gcc_usb1_sleep_clk",
2227                         .parent_names = (const char *[]){
2228                                 "gcc_sleep_clk_src"
2229                         },
2230                         .num_parents = 1,
2231                         .flags = CLK_SET_RATE_PARENT,
2232                         .ops = &clk_branch2_ops,
2233                 },
2234         },
2235 };
2236
2237 static struct clk_branch gcc_sdcc1_ahb_clk = {
2238         .halt_reg = 0x4201c,
2239         .clkr = {
2240                 .enable_reg = 0x4201c,
2241                 .enable_mask = BIT(0),
2242                 .hw.init = &(struct clk_init_data){
2243                         .name = "gcc_sdcc1_ahb_clk",
2244                         .parent_names = (const char *[]){
2245                                 "pcnoc_clk_src"
2246                         },
2247                         .num_parents = 1,
2248                         .flags = CLK_SET_RATE_PARENT,
2249                         .ops = &clk_branch2_ops,
2250                 },
2251         },
2252 };
2253
2254 static struct clk_branch gcc_sdcc1_apps_clk = {
2255         .halt_reg = 0x42018,
2256         .clkr = {
2257                 .enable_reg = 0x42018,
2258                 .enable_mask = BIT(0),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "gcc_sdcc1_apps_clk",
2261                         .parent_names = (const char *[]){
2262                                 "sdcc1_apps_clk_src"
2263                         },
2264                         .num_parents = 1,
2265                         .flags = CLK_SET_RATE_PARENT,
2266                         .ops = &clk_branch2_ops,
2267                 },
2268         },
2269 };
2270
2271 static struct clk_branch gcc_sdcc1_ice_core_clk = {
2272         .halt_reg = 0x5d014,
2273         .clkr = {
2274                 .enable_reg = 0x5d014,
2275                 .enable_mask = BIT(0),
2276                 .hw.init = &(struct clk_init_data){
2277                         .name = "gcc_sdcc1_ice_core_clk",
2278                         .parent_names = (const char *[]){
2279                                 "sdcc1_ice_core_clk_src"
2280                         },
2281                         .num_parents = 1,
2282                         .flags = CLK_SET_RATE_PARENT,
2283                         .ops = &clk_branch2_ops,
2284                 },
2285         },
2286 };
2287
2288 static struct clk_branch gcc_sdcc2_ahb_clk = {
2289         .halt_reg = 0x4301c,
2290         .clkr = {
2291                 .enable_reg = 0x4301c,
2292                 .enable_mask = BIT(0),
2293                 .hw.init = &(struct clk_init_data){
2294                         .name = "gcc_sdcc2_ahb_clk",
2295                         .parent_names = (const char *[]){
2296                                 "pcnoc_clk_src"
2297                         },
2298                         .num_parents = 1,
2299                         .flags = CLK_SET_RATE_PARENT,
2300                         .ops = &clk_branch2_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_branch gcc_sdcc2_apps_clk = {
2306         .halt_reg = 0x43018,
2307         .clkr = {
2308                 .enable_reg = 0x43018,
2309                 .enable_mask = BIT(0),
2310                 .hw.init = &(struct clk_init_data){
2311                         .name = "gcc_sdcc2_apps_clk",
2312                         .parent_names = (const char *[]){
2313                                 "sdcc2_apps_clk_src"
2314                         },
2315                         .num_parents = 1,
2316                         .flags = CLK_SET_RATE_PARENT,
2317                         .ops = &clk_branch2_ops,
2318                 },
2319         },
2320 };
2321
2322 static struct clk_branch gcc_mem_noc_nss_axi_clk = {
2323         .halt_reg = 0x1d03c,
2324         .clkr = {
2325                 .enable_reg = 0x1d03c,
2326                 .enable_mask = BIT(0),
2327                 .hw.init = &(struct clk_init_data){
2328                         .name = "gcc_mem_noc_nss_axi_clk",
2329                         .parent_names = (const char *[]){
2330                                 "nss_noc_clk_src"
2331                         },
2332                         .num_parents = 1,
2333                         .flags = CLK_SET_RATE_PARENT,
2334                         .ops = &clk_branch2_ops,
2335                 },
2336         },
2337 };
2338
2339 static struct clk_branch gcc_nss_ce_apb_clk = {
2340         .halt_reg = 0x68174,
2341         .clkr = {
2342                 .enable_reg = 0x68174,
2343                 .enable_mask = BIT(0),
2344                 .hw.init = &(struct clk_init_data){
2345                         .name = "gcc_nss_ce_apb_clk",
2346                         .parent_names = (const char *[]){
2347                                 "nss_ce_clk_src"
2348                         },
2349                         .num_parents = 1,
2350                         .flags = CLK_SET_RATE_PARENT,
2351                         .ops = &clk_branch2_ops,
2352                 },
2353         },
2354 };
2355
2356 static struct clk_branch gcc_nss_ce_axi_clk = {
2357         .halt_reg = 0x68170,
2358         .clkr = {
2359                 .enable_reg = 0x68170,
2360                 .enable_mask = BIT(0),
2361                 .hw.init = &(struct clk_init_data){
2362                         .name = "gcc_nss_ce_axi_clk",
2363                         .parent_names = (const char *[]){
2364                                 "nss_ce_clk_src"
2365                         },
2366                         .num_parents = 1,
2367                         .flags = CLK_SET_RATE_PARENT,
2368                         .ops = &clk_branch2_ops,
2369                 },
2370         },
2371 };
2372
2373 static struct clk_branch gcc_nss_cfg_clk = {
2374         .halt_reg = 0x68160,
2375         .clkr = {
2376                 .enable_reg = 0x68160,
2377                 .enable_mask = BIT(0),
2378                 .hw.init = &(struct clk_init_data){
2379                         .name = "gcc_nss_cfg_clk",
2380                         .parent_names = (const char *[]){
2381                                 "pcnoc_clk_src"
2382                         },
2383                         .num_parents = 1,
2384                         .flags = CLK_SET_RATE_PARENT,
2385                         .ops = &clk_branch2_ops,
2386                 },
2387         },
2388 };
2389
2390 static struct clk_branch gcc_nss_crypto_clk = {
2391         .halt_reg = 0x68164,
2392         .clkr = {
2393                 .enable_reg = 0x68164,
2394                 .enable_mask = BIT(0),
2395                 .hw.init = &(struct clk_init_data){
2396                         .name = "gcc_nss_crypto_clk",
2397                         .parent_names = (const char *[]){
2398                                 "nss_crypto_clk_src"
2399                         },
2400                         .num_parents = 1,
2401                         .flags = CLK_SET_RATE_PARENT,
2402                         .ops = &clk_branch2_ops,
2403                 },
2404         },
2405 };
2406
2407 static struct clk_branch gcc_nss_csr_clk = {
2408         .halt_reg = 0x68318,
2409         .clkr = {
2410                 .enable_reg = 0x68318,
2411                 .enable_mask = BIT(0),
2412                 .hw.init = &(struct clk_init_data){
2413                         .name = "gcc_nss_csr_clk",
2414                         .parent_names = (const char *[]){
2415                                 "nss_ce_clk_src"
2416                         },
2417                         .num_parents = 1,
2418                         .flags = CLK_SET_RATE_PARENT,
2419                         .ops = &clk_branch2_ops,
2420                 },
2421         },
2422 };
2423
2424 static struct clk_branch gcc_nss_edma_cfg_clk = {
2425         .halt_reg = 0x6819c,
2426         .clkr = {
2427                 .enable_reg = 0x6819c,
2428                 .enable_mask = BIT(0),
2429                 .hw.init = &(struct clk_init_data){
2430                         .name = "gcc_nss_edma_cfg_clk",
2431                         .parent_names = (const char *[]){
2432                                 "nss_ppe_clk_src"
2433                         },
2434                         .num_parents = 1,
2435                         .flags = CLK_SET_RATE_PARENT,
2436                         .ops = &clk_branch2_ops,
2437                 },
2438         },
2439 };
2440
2441 static struct clk_branch gcc_nss_edma_clk = {
2442         .halt_reg = 0x68198,
2443         .clkr = {
2444                 .enable_reg = 0x68198,
2445                 .enable_mask = BIT(0),
2446                 .hw.init = &(struct clk_init_data){
2447                         .name = "gcc_nss_edma_clk",
2448                         .parent_names = (const char *[]){
2449                                 "nss_ppe_clk_src"
2450                         },
2451                         .num_parents = 1,
2452                         .flags = CLK_SET_RATE_PARENT,
2453                         .ops = &clk_branch2_ops,
2454                 },
2455         },
2456 };
2457
2458 static struct clk_branch gcc_nss_imem_clk = {
2459         .halt_reg = 0x68178,
2460         .clkr = {
2461                 .enable_reg = 0x68178,
2462                 .enable_mask = BIT(0),
2463                 .hw.init = &(struct clk_init_data){
2464                         .name = "gcc_nss_imem_clk",
2465                         .parent_names = (const char *[]){
2466                                 "nss_imem_clk_src"
2467                         },
2468                         .num_parents = 1,
2469                         .flags = CLK_SET_RATE_PARENT,
2470                         .ops = &clk_branch2_ops,
2471                 },
2472         },
2473 };
2474
2475 static struct clk_branch gcc_nss_noc_clk = {
2476         .halt_reg = 0x68168,
2477         .clkr = {
2478                 .enable_reg = 0x68168,
2479                 .enable_mask = BIT(0),
2480                 .hw.init = &(struct clk_init_data){
2481                         .name = "gcc_nss_noc_clk",
2482                         .parent_names = (const char *[]){
2483                                 "nss_noc_clk_src"
2484                         },
2485                         .num_parents = 1,
2486                         .flags = CLK_SET_RATE_PARENT,
2487                         .ops = &clk_branch2_ops,
2488                 },
2489         },
2490 };
2491
2492 static struct clk_branch gcc_nss_ppe_btq_clk = {
2493         .halt_reg = 0x6833c,
2494         .clkr = {
2495                 .enable_reg = 0x6833c,
2496                 .enable_mask = BIT(0),
2497                 .hw.init = &(struct clk_init_data){
2498                         .name = "gcc_nss_ppe_btq_clk",
2499                         .parent_names = (const char *[]){
2500                                 "nss_ppe_clk_src"
2501                         },
2502                         .num_parents = 1,
2503                         .flags = CLK_SET_RATE_PARENT,
2504                         .ops = &clk_branch2_ops,
2505                 },
2506         },
2507 };
2508
2509 static struct clk_branch gcc_nss_ppe_cfg_clk = {
2510         .halt_reg = 0x68194,
2511         .clkr = {
2512                 .enable_reg = 0x68194,
2513                 .enable_mask = BIT(0),
2514                 .hw.init = &(struct clk_init_data){
2515                         .name = "gcc_nss_ppe_cfg_clk",
2516                         .parent_names = (const char *[]){
2517                                 "nss_ppe_clk_src"
2518                         },
2519                         .num_parents = 1,
2520                         .flags = CLK_SET_RATE_PARENT,
2521                         .ops = &clk_branch2_ops,
2522                 },
2523         },
2524 };
2525
2526 static struct clk_branch gcc_nss_ppe_clk = {
2527         .halt_reg = 0x68190,
2528         .clkr = {
2529                 .enable_reg = 0x68190,
2530                 .enable_mask = BIT(0),
2531                 .hw.init = &(struct clk_init_data){
2532                         .name = "gcc_nss_ppe_clk",
2533                         .parent_names = (const char *[]){
2534                                 "nss_ppe_clk_src"
2535                         },
2536                         .num_parents = 1,
2537                         .flags = CLK_SET_RATE_PARENT,
2538                         .ops = &clk_branch2_ops,
2539                 },
2540         },
2541 };
2542
2543 static struct clk_branch gcc_nss_ppe_ipe_clk = {
2544         .halt_reg = 0x68338,
2545         .clkr = {
2546                 .enable_reg = 0x68338,
2547                 .enable_mask = BIT(0),
2548                 .hw.init = &(struct clk_init_data){
2549                         .name = "gcc_nss_ppe_ipe_clk",
2550                         .parent_names = (const char *[]){
2551                                 "nss_ppe_clk_src"
2552                         },
2553                         .num_parents = 1,
2554                         .flags = CLK_SET_RATE_PARENT,
2555                         .ops = &clk_branch2_ops,
2556                 },
2557         },
2558 };
2559
2560 static struct clk_branch gcc_nss_ptp_ref_clk = {
2561         .halt_reg = 0x6816c,
2562         .clkr = {
2563                 .enable_reg = 0x6816c,
2564                 .enable_mask = BIT(0),
2565                 .hw.init = &(struct clk_init_data){
2566                         .name = "gcc_nss_ptp_ref_clk",
2567                         .parent_names = (const char *[]){
2568                                 "nss_ppe_cdiv_clk_src"
2569                         },
2570                         .num_parents = 1,
2571                         .flags = CLK_SET_RATE_PARENT,
2572                         .ops = &clk_branch2_ops,
2573                 },
2574         },
2575 };
2576
2577 static struct clk_branch gcc_nssnoc_ce_apb_clk = {
2578         .halt_reg = 0x6830c,
2579         .clkr = {
2580                 .enable_reg = 0x6830c,
2581                 .enable_mask = BIT(0),
2582                 .hw.init = &(struct clk_init_data){
2583                         .name = "gcc_nssnoc_ce_apb_clk",
2584                         .parent_names = (const char *[]){
2585                                 "nss_ce_clk_src"
2586                         },
2587                         .num_parents = 1,
2588                         .flags = CLK_SET_RATE_PARENT,
2589                         .ops = &clk_branch2_ops,
2590                 },
2591         },
2592 };
2593
2594 static struct clk_branch gcc_nssnoc_ce_axi_clk = {
2595         .halt_reg = 0x68308,
2596         .clkr = {
2597                 .enable_reg = 0x68308,
2598                 .enable_mask = BIT(0),
2599                 .hw.init = &(struct clk_init_data){
2600                         .name = "gcc_nssnoc_ce_axi_clk",
2601                         .parent_names = (const char *[]){
2602                                 "nss_ce_clk_src"
2603                         },
2604                         .num_parents = 1,
2605                         .flags = CLK_SET_RATE_PARENT,
2606                         .ops = &clk_branch2_ops,
2607                 },
2608         },
2609 };
2610
2611 static struct clk_branch gcc_nssnoc_crypto_clk = {
2612         .halt_reg = 0x68314,
2613         .clkr = {
2614                 .enable_reg = 0x68314,
2615                 .enable_mask = BIT(0),
2616                 .hw.init = &(struct clk_init_data){
2617                         .name = "gcc_nssnoc_crypto_clk",
2618                         .parent_names = (const char *[]){
2619                                 "nss_crypto_clk_src"
2620                         },
2621                         .num_parents = 1,
2622                         .flags = CLK_SET_RATE_PARENT,
2623                         .ops = &clk_branch2_ops,
2624                 },
2625         },
2626 };
2627
2628 static struct clk_branch gcc_nssnoc_ppe_cfg_clk = {
2629         .halt_reg = 0x68304,
2630         .clkr = {
2631                 .enable_reg = 0x68304,
2632                 .enable_mask = BIT(0),
2633                 .hw.init = &(struct clk_init_data){
2634                         .name = "gcc_nssnoc_ppe_cfg_clk",
2635                         .parent_names = (const char *[]){
2636                                 "nss_ppe_clk_src"
2637                         },
2638                         .num_parents = 1,
2639                         .flags = CLK_SET_RATE_PARENT,
2640                         .ops = &clk_branch2_ops,
2641                 },
2642         },
2643 };
2644
2645 static struct clk_branch gcc_nssnoc_ppe_clk = {
2646         .halt_reg = 0x68300,
2647         .clkr = {
2648                 .enable_reg = 0x68300,
2649                 .enable_mask = BIT(0),
2650                 .hw.init = &(struct clk_init_data){
2651                         .name = "gcc_nssnoc_ppe_clk",
2652                         .parent_names = (const char *[]){
2653                                 "nss_ppe_clk_src"
2654                         },
2655                         .num_parents = 1,
2656                         .flags = CLK_SET_RATE_PARENT,
2657                         .ops = &clk_branch2_ops,
2658                 },
2659         },
2660 };
2661
2662 static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
2663         .halt_reg = 0x68180,
2664         .clkr = {
2665                 .enable_reg = 0x68180,
2666                 .enable_mask = BIT(0),
2667                 .hw.init = &(struct clk_init_data){
2668                         .name = "gcc_nssnoc_qosgen_ref_clk",
2669                         .parent_names = (const char *[]){
2670                                 "gcc_xo_clk_src"
2671                         },
2672                         .num_parents = 1,
2673                         .flags = CLK_SET_RATE_PARENT,
2674                         .ops = &clk_branch2_ops,
2675                 },
2676         },
2677 };
2678
2679 static struct clk_branch gcc_nssnoc_snoc_clk = {
2680         .halt_reg = 0x68188,
2681         .clkr = {
2682                 .enable_reg = 0x68188,
2683                 .enable_mask = BIT(0),
2684                 .hw.init = &(struct clk_init_data){
2685                         .name = "gcc_nssnoc_snoc_clk",
2686                         .parent_names = (const char *[]){
2687                                 "system_noc_clk_src"
2688                         },
2689                         .num_parents = 1,
2690                         .flags = CLK_SET_RATE_PARENT,
2691                         .ops = &clk_branch2_ops,
2692                 },
2693         },
2694 };
2695
2696 static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
2697         .halt_reg = 0x68184,
2698         .clkr = {
2699                 .enable_reg = 0x68184,
2700                 .enable_mask = BIT(0),
2701                 .hw.init = &(struct clk_init_data){
2702                         .name = "gcc_nssnoc_timeout_ref_clk",
2703                         .parent_names = (const char *[]){
2704                                 "gcc_xo_div4_clk_src"
2705                         },
2706                         .num_parents = 1,
2707                         .flags = CLK_SET_RATE_PARENT,
2708                         .ops = &clk_branch2_ops,
2709                 },
2710         },
2711 };
2712
2713 static struct clk_branch gcc_nssnoc_ubi0_ahb_clk = {
2714         .halt_reg = 0x68270,
2715         .clkr = {
2716                 .enable_reg = 0x68270,
2717                 .enable_mask = BIT(0),
2718                 .hw.init = &(struct clk_init_data){
2719                         .name = "gcc_nssnoc_ubi0_ahb_clk",
2720                         .parent_names = (const char *[]){
2721                                 "nss_ce_clk_src"
2722                         },
2723                         .num_parents = 1,
2724                         .flags = CLK_SET_RATE_PARENT,
2725                         .ops = &clk_branch2_ops,
2726                 },
2727         },
2728 };
2729
2730 static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {
2731         .halt_reg = 0x68274,
2732         .clkr = {
2733                 .enable_reg = 0x68274,
2734                 .enable_mask = BIT(0),
2735                 .hw.init = &(struct clk_init_data){
2736                         .name = "gcc_nssnoc_ubi1_ahb_clk",
2737                         .parent_names = (const char *[]){
2738                                 "nss_ce_clk_src"
2739                         },
2740                         .num_parents = 1,
2741                         .flags = CLK_SET_RATE_PARENT,
2742                         .ops = &clk_branch2_ops,
2743                 },
2744         },
2745 };
2746
2747 static struct clk_branch gcc_ubi0_ahb_clk = {
2748         .halt_reg = 0x6820c,
2749         .clkr = {
2750                 .enable_reg = 0x6820c,
2751                 .enable_mask = BIT(0),
2752                 .hw.init = &(struct clk_init_data){
2753                         .name = "gcc_ubi0_ahb_clk",
2754                         .parent_names = (const char *[]){
2755                                 "nss_ce_clk_src"
2756                         },
2757                         .num_parents = 1,
2758                         .flags = CLK_SET_RATE_PARENT,
2759                         .ops = &clk_branch2_ops,
2760                 },
2761         },
2762 };
2763
2764 static struct clk_branch gcc_ubi0_axi_clk = {
2765         .halt_reg = 0x68200,
2766         .clkr = {
2767                 .enable_reg = 0x68200,
2768                 .enable_mask = BIT(0),
2769                 .hw.init = &(struct clk_init_data){
2770                         .name = "gcc_ubi0_axi_clk",
2771                         .parent_names = (const char *[]){
2772                                 "nss_noc_clk_src"
2773                         },
2774                         .num_parents = 1,
2775                         .flags = CLK_SET_RATE_PARENT,
2776                         .ops = &clk_branch2_ops,
2777                 },
2778         },
2779 };
2780
2781 static struct clk_branch gcc_ubi0_nc_axi_clk = {
2782         .halt_reg = 0x68204,
2783         .clkr = {
2784                 .enable_reg = 0x68204,
2785                 .enable_mask = BIT(0),
2786                 .hw.init = &(struct clk_init_data){
2787                         .name = "gcc_ubi0_nc_axi_clk",
2788                         .parent_names = (const char *[]){
2789                                 "nss_noc_clk_src"
2790                         },
2791                         .num_parents = 1,
2792                         .flags = CLK_SET_RATE_PARENT,
2793                         .ops = &clk_branch2_ops,
2794                 },
2795         },
2796 };
2797
2798 static struct clk_branch gcc_ubi0_core_clk = {
2799         .halt_reg = 0x68210,
2800         .clkr = {
2801                 .enable_reg = 0x68210,
2802                 .enable_mask = BIT(0),
2803                 .hw.init = &(struct clk_init_data){
2804                         .name = "gcc_ubi0_core_clk",
2805                         .parent_names = (const char *[]){
2806                                 "nss_ubi0_div_clk_src"
2807                         },
2808                         .num_parents = 1,
2809                         .flags = CLK_SET_RATE_PARENT,
2810                         .ops = &clk_branch2_ops,
2811                 },
2812         },
2813 };
2814
2815 static struct clk_branch gcc_ubi0_mpt_clk = {
2816         .halt_reg = 0x68208,
2817         .clkr = {
2818                 .enable_reg = 0x68208,
2819                 .enable_mask = BIT(0),
2820                 .hw.init = &(struct clk_init_data){
2821                         .name = "gcc_ubi0_mpt_clk",
2822                         .parent_names = (const char *[]){
2823                                 "ubi_mpt_clk_src"
2824                         },
2825                         .num_parents = 1,
2826                         .flags = CLK_SET_RATE_PARENT,
2827                         .ops = &clk_branch2_ops,
2828                 },
2829         },
2830 };
2831
2832 static struct clk_branch gcc_ubi1_ahb_clk = {
2833         .halt_reg = 0x6822c,
2834         .clkr = {
2835                 .enable_reg = 0x6822c,
2836                 .enable_mask = BIT(0),
2837                 .hw.init = &(struct clk_init_data){
2838                         .name = "gcc_ubi1_ahb_clk",
2839                         .parent_names = (const char *[]){
2840                                 "nss_ce_clk_src"
2841                         },
2842                         .num_parents = 1,
2843                         .flags = CLK_SET_RATE_PARENT,
2844                         .ops = &clk_branch2_ops,
2845                 },
2846         },
2847 };
2848
2849 static struct clk_branch gcc_ubi1_axi_clk = {
2850         .halt_reg = 0x68220,
2851         .clkr = {
2852                 .enable_reg = 0x68220,
2853                 .enable_mask = BIT(0),
2854                 .hw.init = &(struct clk_init_data){
2855                         .name = "gcc_ubi1_axi_clk",
2856                         .parent_names = (const char *[]){
2857                                 "nss_noc_clk_src"
2858                         },
2859                         .num_parents = 1,
2860                         .flags = CLK_SET_RATE_PARENT,
2861                         .ops = &clk_branch2_ops,
2862                 },
2863         },
2864 };
2865
2866 static struct clk_branch gcc_ubi1_nc_axi_clk = {
2867         .halt_reg = 0x68224,
2868         .clkr = {
2869                 .enable_reg = 0x68224,
2870                 .enable_mask = BIT(0),
2871                 .hw.init = &(struct clk_init_data){
2872                         .name = "gcc_ubi1_nc_axi_clk",
2873                         .parent_names = (const char *[]){
2874                                 "nss_noc_clk_src"
2875                         },
2876                         .num_parents = 1,
2877                         .flags = CLK_SET_RATE_PARENT,
2878                         .ops = &clk_branch2_ops,
2879                 },
2880         },
2881 };
2882
2883 static struct clk_branch gcc_ubi1_core_clk = {
2884         .halt_reg = 0x68230,
2885         .clkr = {
2886                 .enable_reg = 0x68230,
2887                 .enable_mask = BIT(0),
2888                 .hw.init = &(struct clk_init_data){
2889                         .name = "gcc_ubi1_core_clk",
2890                         .parent_names = (const char *[]){
2891                                 "nss_ubi1_div_clk_src"
2892                         },
2893                         .num_parents = 1,
2894                         .flags = CLK_SET_RATE_PARENT,
2895                         .ops = &clk_branch2_ops,
2896                 },
2897         },
2898 };
2899
2900 static struct clk_branch gcc_ubi1_mpt_clk = {
2901         .halt_reg = 0x68228,
2902         .clkr = {
2903                 .enable_reg = 0x68228,
2904                 .enable_mask = BIT(0),
2905                 .hw.init = &(struct clk_init_data){
2906                         .name = "gcc_ubi1_mpt_clk",
2907                         .parent_names = (const char *[]){
2908                                 "ubi_mpt_clk_src"
2909                         },
2910                         .num_parents = 1,
2911                         .flags = CLK_SET_RATE_PARENT,
2912                         .ops = &clk_branch2_ops,
2913                 },
2914         },
2915 };
2916
2917 static struct clk_hw *gcc_ipq8074_hws[] = {
2918         &gpll0_out_main_div2.hw,
2919         &gpll6_out_main_div2.hw,
2920         &pcnoc_clk_src.hw,
2921         &system_noc_clk_src.hw,
2922         &gcc_xo_div4_clk_src.hw,
2923         &nss_noc_clk_src.hw,
2924         &nss_ppe_cdiv_clk_src.hw,
2925 };
2926
2927 static struct clk_regmap *gcc_ipq8074_clks[] = {
2928         [GPLL0_MAIN] = &gpll0_main.clkr,
2929         [GPLL0] = &gpll0.clkr,
2930         [GPLL2_MAIN] = &gpll2_main.clkr,
2931         [GPLL2] = &gpll2.clkr,
2932         [GPLL4_MAIN] = &gpll4_main.clkr,
2933         [GPLL4] = &gpll4.clkr,
2934         [GPLL6_MAIN] = &gpll6_main.clkr,
2935         [GPLL6] = &gpll6.clkr,
2936         [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,
2937         [UBI32_PLL] = &ubi32_pll.clkr,
2938         [NSS_CRYPTO_PLL_MAIN] = &nss_crypto_pll_main.clkr,
2939         [NSS_CRYPTO_PLL] = &nss_crypto_pll.clkr,
2940         [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
2941         [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
2942         [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2943         [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2944         [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2945         [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2946         [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2947         [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2948         [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2949         [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2950         [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2951         [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2952         [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2953         [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2954         [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2955         [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2956         [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2957         [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2958         [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2959         [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2960         [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,
2961         [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,
2962         [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
2963         [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,
2964         [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,
2965         [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
2966         [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2967         [SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
2968         [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2969         [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
2970         [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
2971         [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
2972         [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
2973         [USB1_MASTER_CLK_SRC] = &usb1_master_clk_src.clkr,
2974         [USB1_AUX_CLK_SRC] = &usb1_aux_clk_src.clkr,
2975         [USB1_MOCK_UTMI_CLK_SRC] = &usb1_mock_utmi_clk_src.clkr,
2976         [USB1_PIPE_CLK_SRC] = &usb1_pipe_clk_src.clkr,
2977         [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
2978         [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
2979         [NSS_CE_CLK_SRC] = &nss_ce_clk_src.clkr,
2980         [NSS_NOC_BFDCD_CLK_SRC] = &nss_noc_bfdcd_clk_src.clkr,
2981         [NSS_CRYPTO_CLK_SRC] = &nss_crypto_clk_src.clkr,
2982         [NSS_UBI0_CLK_SRC] = &nss_ubi0_clk_src.clkr,
2983         [NSS_UBI0_DIV_CLK_SRC] = &nss_ubi0_div_clk_src.clkr,
2984         [NSS_UBI1_CLK_SRC] = &nss_ubi1_clk_src.clkr,
2985         [NSS_UBI1_DIV_CLK_SRC] = &nss_ubi1_div_clk_src.clkr,
2986         [UBI_MPT_CLK_SRC] = &ubi_mpt_clk_src.clkr,
2987         [NSS_IMEM_CLK_SRC] = &nss_imem_clk_src.clkr,
2988         [NSS_PPE_CLK_SRC] = &nss_ppe_clk_src.clkr,
2989         [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2990         [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2991         [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2992         [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2993         [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2994         [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2995         [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2996         [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2997         [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2998         [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2999         [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
3000         [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
3001         [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
3002         [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
3003         [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
3004         [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
3005         [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
3006         [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
3007         [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
3008         [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
3009         [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
3010         [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
3011         [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
3012         [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
3013         [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
3014         [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
3015         [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,
3016         [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,
3017         [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
3018         [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
3019         [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
3020         [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
3021         [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,
3022         [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,
3023         [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
3024         [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,
3025         [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
3026         [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
3027         [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
3028         [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,
3029         [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,
3030         [GCC_USB1_AUX_CLK] = &gcc_usb1_aux_clk.clkr,
3031         [GCC_SYS_NOC_USB1_AXI_CLK] = &gcc_sys_noc_usb1_axi_clk.clkr,
3032         [GCC_USB1_MASTER_CLK] = &gcc_usb1_master_clk.clkr,
3033         [GCC_USB1_MOCK_UTMI_CLK] = &gcc_usb1_mock_utmi_clk.clkr,
3034         [GCC_USB1_PHY_CFG_AHB_CLK] = &gcc_usb1_phy_cfg_ahb_clk.clkr,
3035         [GCC_USB1_PIPE_CLK] = &gcc_usb1_pipe_clk.clkr,
3036         [GCC_USB1_SLEEP_CLK] = &gcc_usb1_sleep_clk.clkr,
3037         [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
3038         [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
3039         [GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
3040         [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
3041         [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
3042         [GCC_MEM_NOC_NSS_AXI_CLK] = &gcc_mem_noc_nss_axi_clk.clkr,
3043         [GCC_NSS_CE_APB_CLK] = &gcc_nss_ce_apb_clk.clkr,
3044         [GCC_NSS_CE_AXI_CLK] = &gcc_nss_ce_axi_clk.clkr,
3045         [GCC_NSS_CFG_CLK] = &gcc_nss_cfg_clk.clkr,
3046         [GCC_NSS_CRYPTO_CLK] = &gcc_nss_crypto_clk.clkr,
3047         [GCC_NSS_CSR_CLK] = &gcc_nss_csr_clk.clkr,
3048         [GCC_NSS_EDMA_CFG_CLK] = &gcc_nss_edma_cfg_clk.clkr,
3049         [GCC_NSS_EDMA_CLK] = &gcc_nss_edma_clk.clkr,
3050         [GCC_NSS_IMEM_CLK] = &gcc_nss_imem_clk.clkr,
3051         [GCC_NSS_NOC_CLK] = &gcc_nss_noc_clk.clkr,
3052         [GCC_NSS_PPE_BTQ_CLK] = &gcc_nss_ppe_btq_clk.clkr,
3053         [GCC_NSS_PPE_CFG_CLK] = &gcc_nss_ppe_cfg_clk.clkr,
3054         [GCC_NSS_PPE_CLK] = &gcc_nss_ppe_clk.clkr,
3055         [GCC_NSS_PPE_IPE_CLK] = &gcc_nss_ppe_ipe_clk.clkr,
3056         [GCC_NSS_PTP_REF_CLK] = &gcc_nss_ptp_ref_clk.clkr,
3057         [GCC_NSSNOC_CE_APB_CLK] = &gcc_nssnoc_ce_apb_clk.clkr,
3058         [GCC_NSSNOC_CE_AXI_CLK] = &gcc_nssnoc_ce_axi_clk.clkr,
3059         [GCC_NSSNOC_CRYPTO_CLK] = &gcc_nssnoc_crypto_clk.clkr,
3060         [GCC_NSSNOC_PPE_CFG_CLK] = &gcc_nssnoc_ppe_cfg_clk.clkr,
3061         [GCC_NSSNOC_PPE_CLK] = &gcc_nssnoc_ppe_clk.clkr,
3062         [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
3063         [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
3064         [GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
3065         [GCC_NSSNOC_UBI0_AHB_CLK] = &gcc_nssnoc_ubi0_ahb_clk.clkr,
3066         [GCC_NSSNOC_UBI1_AHB_CLK] = &gcc_nssnoc_ubi1_ahb_clk.clkr,
3067         [GCC_UBI0_AHB_CLK] = &gcc_ubi0_ahb_clk.clkr,
3068         [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,
3069         [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,
3070         [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,
3071         [GCC_UBI0_MPT_CLK] = &gcc_ubi0_mpt_clk.clkr,
3072         [GCC_UBI1_AHB_CLK] = &gcc_ubi1_ahb_clk.clkr,
3073         [GCC_UBI1_AXI_CLK] = &gcc_ubi1_axi_clk.clkr,
3074         [GCC_UBI1_NC_AXI_CLK] = &gcc_ubi1_nc_axi_clk.clkr,
3075         [GCC_UBI1_CORE_CLK] = &gcc_ubi1_core_clk.clkr,
3076         [GCC_UBI1_MPT_CLK] = &gcc_ubi1_mpt_clk.clkr,
3077 };
3078
3079 static const struct qcom_reset_map gcc_ipq8074_resets[] = {
3080         [GCC_BLSP1_BCR] = { 0x01000, 0 },
3081         [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
3082         [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },
3083         [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },
3084         [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
3085         [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },
3086         [GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
3087         [GCC_BLSP1_QUP4_BCR] = { 0x05008, 0 },
3088         [GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
3089         [GCC_BLSP1_QUP5_BCR] = { 0x06008, 0 },
3090         [GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
3091         [GCC_BLSP1_QUP6_BCR] = { 0x07008, 0 },
3092         [GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
3093         [GCC_IMEM_BCR] = { 0x0e000, 0 },
3094         [GCC_SMMU_BCR] = { 0x12000, 0 },
3095         [GCC_APSS_TCU_BCR] = { 0x12050, 0 },
3096         [GCC_SMMU_XPU_BCR] = { 0x12054, 0 },
3097         [GCC_PCNOC_TBU_BCR] = { 0x12058, 0 },
3098         [GCC_SMMU_CFG_BCR] = { 0x1208c, 0 },
3099         [GCC_PRNG_BCR] = { 0x13000, 0 },
3100         [GCC_BOOT_ROM_BCR] = { 0x13008, 0 },
3101         [GCC_CRYPTO_BCR] = { 0x16000, 0 },
3102         [GCC_WCSS_BCR] = { 0x18000, 0 },
3103         [GCC_WCSS_Q6_BCR] = { 0x18100, 0 },
3104         [GCC_NSS_BCR] = { 0x19000, 0 },
3105         [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
3106         [GCC_ADSS_BCR] = { 0x1c000, 0 },
3107         [GCC_DDRSS_BCR] = { 0x1e000, 0 },
3108         [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },
3109         [GCC_PCNOC_BCR] = { 0x27018, 0 },
3110         [GCC_TCSR_BCR] = { 0x28000, 0 },
3111         [GCC_QDSS_BCR] = { 0x29000, 0 },
3112         [GCC_DCD_BCR] = { 0x2a000, 0 },
3113         [GCC_MSG_RAM_BCR] = { 0x2b000, 0 },
3114         [GCC_MPM_BCR] = { 0x2c000, 0 },
3115         [GCC_SPMI_BCR] = { 0x2e000, 0 },
3116         [GCC_SPDM_BCR] = { 0x2f000, 0 },
3117         [GCC_RBCPR_BCR] = { 0x33000, 0 },
3118         [GCC_RBCPR_MX_BCR] = { 0x33014, 0 },
3119         [GCC_TLMM_BCR] = { 0x34000, 0 },
3120         [GCC_RBCPR_WCSS_BCR] = { 0x3a000, 0 },
3121         [GCC_USB0_PHY_BCR] = { 0x3e034, 0 },
3122         [GCC_USB3PHY_0_PHY_BCR] = { 0x3e03c, 0 },
3123         [GCC_USB0_BCR] = { 0x3e070, 0 },
3124         [GCC_USB1_PHY_BCR] = { 0x3f034, 0 },
3125         [GCC_USB3PHY_1_PHY_BCR] = { 0x3f03c, 0 },
3126         [GCC_USB1_BCR] = { 0x3f070, 0 },
3127         [GCC_QUSB2_0_PHY_BCR] = { 0x4103c, 0 },
3128         [GCC_QUSB2_1_PHY_BCR] = { 0x41040, 0 },
3129         [GCC_SDCC1_BCR] = { 0x42000, 0 },
3130         [GCC_SDCC2_BCR] = { 0x43000, 0 },
3131         [GCC_SNOC_BUS_TIMEOUT0_BCR] = { 0x47000, 0 },
3132         [GCC_SNOC_BUS_TIMEOUT2_BCR] = { 0x47008, 0 },
3133         [GCC_SNOC_BUS_TIMEOUT3_BCR] = { 0x47010, 0 },
3134         [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },
3135         [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },
3136         [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },
3137         [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },
3138         [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },
3139         [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },
3140         [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },
3141         [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },
3142         [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },
3143         [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },
3144         [GCC_UNIPHY0_BCR] = { 0x56000, 0 },
3145         [GCC_UNIPHY1_BCR] = { 0x56100, 0 },
3146         [GCC_UNIPHY2_BCR] = { 0x56200, 0 },
3147         [GCC_CMN_12GPLL_BCR] = { 0x56300, 0 },
3148         [GCC_QPIC_BCR] = { 0x57018, 0 },
3149         [GCC_MDIO_BCR] = { 0x58000, 0 },
3150         [GCC_PCIE1_TBU_BCR] = { 0x65000, 0 },
3151         [GCC_WCSS_CORE_TBU_BCR] = { 0x66000, 0 },
3152         [GCC_WCSS_Q6_TBU_BCR] = { 0x67000, 0 },
3153         [GCC_USB0_TBU_BCR] = { 0x6a000, 0 },
3154         [GCC_USB1_TBU_BCR] = { 0x6a004, 0 },
3155         [GCC_PCIE0_TBU_BCR] = { 0x6b000, 0 },
3156         [GCC_NSS_NOC_TBU_BCR] = { 0x6e000, 0 },
3157         [GCC_PCIE0_BCR] = { 0x75004, 0 },
3158         [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },
3159         [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },
3160         [GCC_PCIE0_LINK_DOWN_BCR] = { 0x75044, 0 },
3161         [GCC_PCIE1_BCR] = { 0x76004, 0 },
3162         [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },
3163         [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },
3164         [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },
3165         [GCC_DCC_BCR] = { 0x77000, 0 },
3166         [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },
3167         [GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x79000, 0 },
3168         [GCC_SMMU_CATS_BCR] = { 0x7c000, 0 },
3169 };
3170
3171 static const struct of_device_id gcc_ipq8074_match_table[] = {
3172         { .compatible = "qcom,gcc-ipq8074" },
3173         { }
3174 };
3175 MODULE_DEVICE_TABLE(of, gcc_ipq8074_match_table);
3176
3177 static const struct regmap_config gcc_ipq8074_regmap_config = {
3178         .reg_bits       = 32,
3179         .reg_stride     = 4,
3180         .val_bits       = 32,
3181         .max_register   = 0x7fffc,
3182         .fast_io        = true,
3183 };
3184
3185 static const struct qcom_cc_desc gcc_ipq8074_desc = {
3186         .config = &gcc_ipq8074_regmap_config,
3187         .clks = gcc_ipq8074_clks,
3188         .num_clks = ARRAY_SIZE(gcc_ipq8074_clks),
3189         .resets = gcc_ipq8074_resets,
3190         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
3191 };
3192
3193 static int gcc_ipq8074_probe(struct platform_device *pdev)
3194 {
3195         int ret, i;
3196
3197         for (i = 0; i < ARRAY_SIZE(gcc_ipq8074_hws); i++) {
3198                 ret = devm_clk_hw_register(&pdev->dev, gcc_ipq8074_hws[i]);
3199                 if (ret)
3200                         return ret;
3201         }
3202
3203         return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
3204 }
3205
3206 static struct platform_driver gcc_ipq8074_driver = {
3207         .probe = gcc_ipq8074_probe,
3208         .driver = {
3209                 .name   = "qcom,gcc-ipq8074",
3210                 .of_match_table = gcc_ipq8074_match_table,
3211         },
3212 };
3213
3214 static int __init gcc_ipq8074_init(void)
3215 {
3216         return platform_driver_register(&gcc_ipq8074_driver);
3217 }
3218 core_initcall(gcc_ipq8074_init);
3219
3220 static void __exit gcc_ipq8074_exit(void)
3221 {
3222         platform_driver_unregister(&gcc_ipq8074_driver);
3223 }
3224 module_exit(gcc_ipq8074_exit);
3225
3226 MODULE_DESCRIPTION("QCOM GCC IPQ8074 Driver");
3227 MODULE_LICENSE("GPL v2");
3228 MODULE_ALIAS("platform:gcc-ipq8074");