drivers/clk/qcom/dispcc-sm8250.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018-2020, 2022, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/module.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/regmap.h>
  11 #include <linux/reset-controller.h>
  12
  13 #include <dt-bindings/clock/qcom,dispcc-sm8250.h>
  14
  15 #include "clk-alpha-pll.h"
  16 #include "clk-branch.h"
  17 #include "clk-rcg.h"
  18 #include "clk-regmap-divider.h"
  19 #include "common.h"
  20 #include "gdsc.h"
  21 #include "reset.h"
  22
  23 enum {
  24         P_BI_TCXO,
  25         P_DISP_CC_PLL0_OUT_MAIN,
  26         P_DISP_CC_PLL1_OUT_EVEN,
  27         P_DISP_CC_PLL1_OUT_MAIN,
  28         P_DP_PHY_PLL_LINK_CLK,
  29         P_DP_PHY_PLL_VCO_DIV_CLK,
  30         P_DPTX1_PHY_PLL_LINK_CLK,
  31         P_DPTX1_PHY_PLL_VCO_DIV_CLK,
  32         P_DPTX2_PHY_PLL_LINK_CLK,
  33         P_DPTX2_PHY_PLL_VCO_DIV_CLK,
  34         P_EDP_PHY_PLL_LINK_CLK,
  35         P_EDP_PHY_PLL_VCO_DIV_CLK,
  36         P_DSI0_PHY_PLL_OUT_BYTECLK,
  37         P_DSI0_PHY_PLL_OUT_DSICLK,
  38         P_DSI1_PHY_PLL_OUT_BYTECLK,
  39         P_DSI1_PHY_PLL_OUT_DSICLK,
  40 };
  41
  42 static struct pll_vco vco_table[] = {
  43         { 249600000, 2000000000, 0 },
  44 };
  45
  46 static struct alpha_pll_config disp_cc_pll0_config = {
  47         .l = 0x47,
  48         .alpha = 0xE000,
  49         .config_ctl_val = 0x20485699,
  50         .config_ctl_hi_val = 0x00002261,
  51         .config_ctl_hi1_val = 0x329A699C,
  52         .user_ctl_val = 0x00000000,
  53         .user_ctl_hi_val = 0x00000805,
  54         .user_ctl_hi1_val = 0x00000000,
  55 };
  56
  57 static struct clk_init_data disp_cc_pll0_init = {
  58         .name = "disp_cc_pll0",
  59         .parent_data = &(const struct clk_parent_data){
  60                 .fw_name = "bi_tcxo",
  61         },
  62         .num_parents = 1,
  63         .ops = &clk_alpha_pll_lucid_ops,
  64 };
  65
  66 static struct clk_alpha_pll disp_cc_pll0 = {
  67         .offset = 0x0,
  68         .vco_table = vco_table,
  69         .num_vco = ARRAY_SIZE(vco_table),
  70         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  71         .clkr.hw.init = &disp_cc_pll0_init
  72 };
  73
  74 static struct alpha_pll_config disp_cc_pll1_config = {
  75         .l = 0x1F,
  76         .alpha = 0x4000,
  77         .config_ctl_val = 0x20485699,
  78         .config_ctl_hi_val = 0x00002261,
  79         .config_ctl_hi1_val = 0x329A699C,
  80         .user_ctl_val = 0x00000000,
  81         .user_ctl_hi_val = 0x00000805,
  82         .user_ctl_hi1_val = 0x00000000,
  83 };
  84
  85 static struct clk_init_data disp_cc_pll1_init = {
  86         .name = "disp_cc_pll1",
  87         .parent_data = &(const struct clk_parent_data){
  88                 .fw_name = "bi_tcxo",
  89         },
  90         .num_parents = 1,
  91         .ops = &clk_alpha_pll_lucid_ops,
  92 };
  93
  94 static struct clk_alpha_pll disp_cc_pll1 = {
  95         .offset = 0x1000,
  96         .vco_table = vco_table,
  97         .num_vco = ARRAY_SIZE(vco_table),
  98         .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
  99         .clkr.hw.init = &disp_cc_pll1_init
 100 };
 101
 102 static const struct parent_map disp_cc_parent_map_0[] = {
 103         { P_BI_TCXO, 0 },
 104         { P_DP_PHY_PLL_LINK_CLK, 1 },
 105         { P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
 106         { P_DPTX1_PHY_PLL_LINK_CLK, 3 },
 107         { P_DPTX1_PHY_PLL_VCO_DIV_CLK, 4 },
 108         { P_DPTX2_PHY_PLL_LINK_CLK, 5 },
 109         { P_DPTX2_PHY_PLL_VCO_DIV_CLK, 6 },
 110 };
 111
 112 static const struct clk_parent_data disp_cc_parent_data_0[] = {
 113         { .fw_name = "bi_tcxo" },
 114         { .fw_name = "dp_phy_pll_link_clk" },
 115         { .fw_name = "dp_phy_pll_vco_div_clk" },
 116         { .fw_name = "dptx1_phy_pll_link_clk" },
 117         { .fw_name = "dptx1_phy_pll_vco_div_clk" },
 118         { .fw_name = "dptx2_phy_pll_link_clk" },
 119         { .fw_name = "dptx2_phy_pll_vco_div_clk" },
 120 };
 121
 122 static const struct parent_map disp_cc_parent_map_1[] = {
 123         { P_BI_TCXO, 0 },
 124 };
 125
 126 static const struct clk_parent_data disp_cc_parent_data_1[] = {
 127         { .fw_name = "bi_tcxo" },
 128 };
 129
 130 static const struct parent_map disp_cc_parent_map_2[] = {
 131         { P_BI_TCXO, 0 },
 132         { P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
 133         { P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
 134 };
 135
 136 static const struct clk_parent_data disp_cc_parent_data_2[] = {
 137         { .fw_name = "bi_tcxo" },
 138         { .fw_name = "dsi0_phy_pll_out_byteclk" },
 139         { .fw_name = "dsi1_phy_pll_out_byteclk" },
 140 };
 141
 142 static const struct parent_map disp_cc_parent_map_3[] = {
 143         { P_BI_TCXO, 0 },
 144         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 145 };
 146
 147 static const struct clk_parent_data disp_cc_parent_data_3[] = {
 148         { .fw_name = "bi_tcxo" },
 149         { .hw = &disp_cc_pll1.clkr.hw },
 150 };
 151
 152 static const struct parent_map disp_cc_parent_map_4[] = {
 153         { P_BI_TCXO, 0 },
 154         { P_EDP_PHY_PLL_LINK_CLK, 1 },
 155         { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
 156 };
 157
 158 static const struct clk_parent_data disp_cc_parent_data_4[] = {
 159         { .fw_name = "bi_tcxo" },
 160         { .fw_name = "edp_phy_pll_link_clk" },
 161         { .fw_name = "edp_phy_pll_vco_div_clk" },
 162 };
 163
 164 static const struct parent_map disp_cc_parent_map_5[] = {
 165         { P_BI_TCXO, 0 },
 166         { P_DISP_CC_PLL0_OUT_MAIN, 1 },
 167         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 168 };
 169
 170 static const struct clk_parent_data disp_cc_parent_data_5[] = {
 171         { .fw_name = "bi_tcxo" },
 172         { .hw = &disp_cc_pll0.clkr.hw },
 173         { .hw = &disp_cc_pll1.clkr.hw },
 174 };
 175
 176 static const struct parent_map disp_cc_parent_map_6[] = {
 177         { P_BI_TCXO, 0 },
 178         { P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
 179         { P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
 180 };
 181
 182 static const struct clk_parent_data disp_cc_parent_data_6[] = {
 183         { .fw_name = "bi_tcxo" },
 184         { .fw_name = "dsi0_phy_pll_out_dsiclk" },
 185         { .fw_name = "dsi1_phy_pll_out_dsiclk" },
 186 };
 187
 188 static const struct parent_map disp_cc_parent_map_7[] = {
 189         { P_BI_TCXO, 0 },
 190         { P_DISP_CC_PLL1_OUT_MAIN, 4 },
 191         /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
 192 };
 193
 194 static const struct clk_parent_data disp_cc_parent_data_7[] = {
 195         { .fw_name = "bi_tcxo" },
 196         { .hw = &disp_cc_pll1.clkr.hw },
 197         /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
 198 };
 199
 200 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
 201         F(19200000, P_BI_TCXO, 1, 0, 0),
 202         F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
 203         F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
 204         { }
 205 };
 206
 207 static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
 208         .cmd_rcgr = 0x22bc,
 209         .mnd_width = 0,
 210         .hid_width = 5,
 211         .parent_map = disp_cc_parent_map_3,
 212         .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
 213         .clkr.hw.init = &(struct clk_init_data){
 214                 .name = "disp_cc_mdss_ahb_clk_src",
 215                 .parent_data = disp_cc_parent_data_3,
 216                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
 217                 .flags = CLK_SET_RATE_PARENT,
 218                 .ops = &clk_rcg2_shared_ops,
 219         },
 220 };
 221
 222 static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
 223         F(19200000, P_BI_TCXO, 1, 0, 0),
 224         { }
 225 };
 226
 227 static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
 228         .cmd_rcgr = 0x2110,
 229         .mnd_width = 0,
 230         .hid_width = 5,
 231         .parent_map = disp_cc_parent_map_2,
 232         .clkr.hw.init = &(struct clk_init_data){
 233                 .name = "disp_cc_mdss_byte0_clk_src",
 234                 .parent_data = disp_cc_parent_data_2,
 235                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 236                 .flags = CLK_SET_RATE_PARENT,
 237                 .ops = &clk_byte2_ops,
 238         },
 239 };
 240
 241 static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
 242         .cmd_rcgr = 0x212c,
 243         .mnd_width = 0,
 244         .hid_width = 5,
 245         .parent_map = disp_cc_parent_map_2,
 246         .clkr.hw.init = &(struct clk_init_data){
 247                 .name = "disp_cc_mdss_byte1_clk_src",
 248                 .parent_data = disp_cc_parent_data_2,
 249                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 250                 .flags = CLK_SET_RATE_PARENT,
 251                 .ops = &clk_byte2_ops,
 252         },
 253 };
 254
 255 static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
 256         .cmd_rcgr = 0x2240,
 257         .mnd_width = 0,
 258         .hid_width = 5,
 259         .parent_map = disp_cc_parent_map_1,
 260         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 261         .clkr.hw.init = &(struct clk_init_data){
 262                 .name = "disp_cc_mdss_dp_aux1_clk_src",
 263                 .parent_data = disp_cc_parent_data_1,
 264                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 265                 .flags = CLK_SET_RATE_PARENT,
 266                 .ops = &clk_rcg2_ops,
 267         },
 268 };
 269
 270 static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
 271         .cmd_rcgr = 0x21dc,
 272         .mnd_width = 0,
 273         .hid_width = 5,
 274         .parent_map = disp_cc_parent_map_1,
 275         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 276         .clkr.hw.init = &(struct clk_init_data){
 277                 .name = "disp_cc_mdss_dp_aux_clk_src",
 278                 .parent_data = disp_cc_parent_data_1,
 279                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 280                 .flags = CLK_SET_RATE_PARENT,
 281                 .ops = &clk_rcg2_ops,
 282         },
 283 };
 284
 285 static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
 286         .cmd_rcgr = 0x220c,
 287         .mnd_width = 0,
 288         .hid_width = 5,
 289         .parent_map = disp_cc_parent_map_0,
 290         .clkr.hw.init = &(struct clk_init_data){
 291                 .name = "disp_cc_mdss_dp_link1_clk_src",
 292                 .parent_data = disp_cc_parent_data_0,
 293                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 294                 .ops = &clk_byte2_ops,
 295         },
 296 };
 297
 298 static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
 299         .cmd_rcgr = 0x2178,
 300         .mnd_width = 0,
 301         .hid_width = 5,
 302         .parent_map = disp_cc_parent_map_0,
 303         .clkr.hw.init = &(struct clk_init_data){
 304                 .name = "disp_cc_mdss_dp_link_clk_src",
 305                 .parent_data = disp_cc_parent_data_0,
 306                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 307                 .ops = &clk_byte2_ops,
 308         },
 309 };
 310
 311 static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {
 312         .cmd_rcgr = 0x21c4,
 313         .mnd_width = 16,
 314         .hid_width = 5,
 315         .parent_map = disp_cc_parent_map_0,
 316         .clkr.hw.init = &(struct clk_init_data){
 317                 .name = "disp_cc_mdss_dp_pixel1_clk_src",
 318                 .parent_data = disp_cc_parent_data_0,
 319                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 320                 .ops = &clk_dp_ops,
 321         },
 322 };
 323
 324 static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
 325         .cmd_rcgr = 0x21f4,
 326         .mnd_width = 16,
 327         .hid_width = 5,
 328         .parent_map = disp_cc_parent_map_0,
 329         .clkr.hw.init = &(struct clk_init_data){
 330                 .name = "disp_cc_mdss_dp_pixel2_clk_src",
 331                 .parent_data = disp_cc_parent_data_0,
 332                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 333                 .ops = &clk_dp_ops,
 334         },
 335 };
 336
 337 static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
 338         .cmd_rcgr = 0x21ac,
 339         .mnd_width = 16,
 340         .hid_width = 5,
 341         .parent_map = disp_cc_parent_map_0,
 342         .clkr.hw.init = &(struct clk_init_data){
 343                 .name = "disp_cc_mdss_dp_pixel_clk_src",
 344                 .parent_data = disp_cc_parent_data_0,
 345                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
 346                 .ops = &clk_dp_ops,
 347         },
 348 };
 349
 350 static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
 351         .cmd_rcgr = 0x228c,
 352         .mnd_width = 0,
 353         .hid_width = 5,
 354         .parent_map = disp_cc_parent_map_1,
 355         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 356         .clkr.hw.init = &(struct clk_init_data){
 357                 .name = "disp_cc_mdss_edp_aux_clk_src",
 358                 .parent_data = disp_cc_parent_data_1,
 359                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 360                 .flags = CLK_SET_RATE_PARENT,
 361                 .ops = &clk_rcg2_ops,
 362         },
 363 };
 364
 365 static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
 366         .cmd_rcgr = 0x22a4,
 367         .mnd_width = 0,
 368         .hid_width = 5,
 369         .parent_map = disp_cc_parent_map_7,
 370         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 371         .clkr.hw.init = &(struct clk_init_data){
 372                 .name = "disp_cc_mdss_edp_gtc_clk_src",
 373                 .parent_data = disp_cc_parent_data_7,
 374                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
 375                 .flags = CLK_SET_RATE_PARENT,
 376                 .ops = &clk_rcg2_ops,
 377         },
 378 };
 379
 380 static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
 381         .cmd_rcgr = 0x2270,
 382         .mnd_width = 0,
 383         .hid_width = 5,
 384         .parent_map = disp_cc_parent_map_4,
 385         .clkr.hw.init = &(struct clk_init_data){
 386                 .name = "disp_cc_mdss_edp_link_clk_src",
 387                 .parent_data = disp_cc_parent_data_4,
 388                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 389                 .flags = CLK_SET_RATE_PARENT,
 390                 .ops = &clk_byte2_ops,
 391         },
 392 };
 393
 394 static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
 395         .cmd_rcgr = 0x2258,
 396         .mnd_width = 16,
 397         .hid_width = 5,
 398         .parent_map = disp_cc_parent_map_4,
 399         .clkr.hw.init = &(struct clk_init_data){
 400                 .name = "disp_cc_mdss_edp_pixel_clk_src",
 401                 .parent_data = disp_cc_parent_data_4,
 402                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
 403                 .ops = &clk_dp_ops,
 404         },
 405 };
 406
 407 static struct clk_branch disp_cc_mdss_edp_aux_clk = {
 408         .halt_reg = 0x2078,
 409         .halt_check = BRANCH_HALT,
 410         .clkr = {
 411                 .enable_reg = 0x2078,
 412                 .enable_mask = BIT(0),
 413                 .hw.init = &(struct clk_init_data){
 414                         .name = "disp_cc_mdss_edp_aux_clk",
 415                         .parent_hws = (const struct clk_hw*[]){
 416                                 &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
 417                         },
 418                         .num_parents = 1,
 419                         .flags = CLK_SET_RATE_PARENT,
 420                         .ops = &clk_branch2_ops,
 421                 },
 422         },
 423 };
 424
 425 static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
 426         .halt_reg = 0x207c,
 427         .halt_check = BRANCH_HALT,
 428         .clkr = {
 429                 .enable_reg = 0x207c,
 430                 .enable_mask = BIT(0),
 431                 .hw.init = &(struct clk_init_data){
 432                         .name = "disp_cc_mdss_edp_gtc_clk",
 433                         .parent_hws = (const struct clk_hw*[]){
 434                                 &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
 435                         },
 436                         .num_parents = 1,
 437                         .flags = CLK_SET_RATE_PARENT,
 438                         .ops = &clk_branch2_ops,
 439                 },
 440         },
 441 };
 442
 443 static struct clk_branch disp_cc_mdss_edp_link_clk = {
 444         .halt_reg = 0x2070,
 445         .halt_check = BRANCH_HALT,
 446         .clkr = {
 447                 .enable_reg = 0x2070,
 448                 .enable_mask = BIT(0),
 449                 .hw.init = &(struct clk_init_data){
 450                         .name = "disp_cc_mdss_edp_link_clk",
 451                         .parent_hws = (const struct clk_hw*[]){
 452                                 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
 453                         },
 454                         .num_parents = 1,
 455                         .flags = CLK_SET_RATE_PARENT,
 456                         .ops = &clk_branch2_ops,
 457                 },
 458         },
 459 };
 460
 461 static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
 462         .halt_reg = 0x2074,
 463         .halt_check = BRANCH_HALT,
 464         .clkr = {
 465                 .enable_reg = 0x2074,
 466                 .enable_mask = BIT(0),
 467                 .hw.init = &(struct clk_init_data){
 468                         .name = "disp_cc_mdss_edp_link_intf_clk",
 469                         .parent_hws = (const struct clk_hw*[]){
 470                                 &disp_cc_mdss_edp_link_clk_src.clkr.hw,
 471                         },
 472                         .num_parents = 1,
 473                         .flags = CLK_GET_RATE_NOCACHE,
 474                         .ops = &clk_branch2_ops,
 475                 },
 476         },
 477 };
 478
 479 static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
 480         .halt_reg = 0x206c,
 481         .halt_check = BRANCH_HALT,
 482         .clkr = {
 483                 .enable_reg = 0x206c,
 484                 .enable_mask = BIT(0),
 485                 .hw.init = &(struct clk_init_data){
 486                         .name = "disp_cc_mdss_edp_pixel_clk",
 487                         .parent_hws = (const struct clk_hw*[]){
 488                                 &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
 489                         },
 490                         .num_parents = 1,
 491                         .flags = CLK_SET_RATE_PARENT,
 492                         .ops = &clk_branch2_ops,
 493                 },
 494         },
 495 };
 496
 497 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
 498         .cmd_rcgr = 0x2148,
 499         .mnd_width = 0,
 500         .hid_width = 5,
 501         .parent_map = disp_cc_parent_map_2,
 502         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 503         .clkr.hw.init = &(struct clk_init_data){
 504                 .name = "disp_cc_mdss_esc0_clk_src",
 505                 .parent_data = disp_cc_parent_data_2,
 506                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 507                 .flags = CLK_SET_RATE_PARENT,
 508                 .ops = &clk_rcg2_ops,
 509         },
 510 };
 511
 512 static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = {
 513         .cmd_rcgr = 0x2160,
 514         .mnd_width = 0,
 515         .hid_width = 5,
 516         .parent_map = disp_cc_parent_map_2,
 517         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 518         .clkr.hw.init = &(struct clk_init_data){
 519                 .name = "disp_cc_mdss_esc1_clk_src",
 520                 .parent_data = disp_cc_parent_data_2,
 521                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
 522                 .flags = CLK_SET_RATE_PARENT,
 523                 .ops = &clk_rcg2_ops,
 524         },
 525 };
 526
 527 static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
 528         F(19200000, P_BI_TCXO, 1, 0, 0),
 529         F(85714286, P_DISP_CC_PLL1_OUT_MAIN, 7, 0, 0),
 530         F(100000000, P_DISP_CC_PLL1_OUT_MAIN, 6, 0, 0),
 531         F(150000000, P_DISP_CC_PLL1_OUT_MAIN, 4, 0, 0),
 532         F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
 533         F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
 534         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 535         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 536         { }
 537 };
 538
 539 static struct clk_rcg2 disp_cc_mdss_mdp_clk_src = {
 540         .cmd_rcgr = 0x20c8,
 541         .mnd_width = 0,
 542         .hid_width = 5,
 543         .parent_map = disp_cc_parent_map_5,
 544         .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
 545         .clkr.hw.init = &(struct clk_init_data){
 546                 .name = "disp_cc_mdss_mdp_clk_src",
 547                 .parent_data = disp_cc_parent_data_5,
 548                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 549                 .flags = CLK_SET_RATE_PARENT,
 550                 .ops = &clk_rcg2_shared_ops,
 551         },
 552 };
 553
 554 static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
 555         .cmd_rcgr = 0x2098,
 556         .mnd_width = 8,
 557         .hid_width = 5,
 558         .parent_map = disp_cc_parent_map_6,
 559         .clkr.hw.init = &(struct clk_init_data){
 560                 .name = "disp_cc_mdss_pclk0_clk_src",
 561                 .parent_data = disp_cc_parent_data_6,
 562                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 563                 .flags = CLK_SET_RATE_PARENT,
 564                 .ops = &clk_pixel_ops,
 565         },
 566 };
 567
 568 static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
 569         .cmd_rcgr = 0x20b0,
 570         .mnd_width = 8,
 571         .hid_width = 5,
 572         .parent_map = disp_cc_parent_map_6,
 573         .clkr.hw.init = &(struct clk_init_data){
 574                 .name = "disp_cc_mdss_pclk1_clk_src",
 575                 .parent_data = disp_cc_parent_data_6,
 576                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_6),
 577                 .flags = CLK_SET_RATE_PARENT,
 578                 .ops = &clk_pixel_ops,
 579         },
 580 };
 581
 582 static const struct freq_tbl ftbl_disp_cc_mdss_rot_clk_src[] = {
 583         F(19200000, P_BI_TCXO, 1, 0, 0),
 584         F(200000000, P_DISP_CC_PLL1_OUT_MAIN, 3, 0, 0),
 585         F(300000000, P_DISP_CC_PLL1_OUT_MAIN, 2, 0, 0),
 586         F(345000000, P_DISP_CC_PLL0_OUT_MAIN, 4, 0, 0),
 587         F(460000000, P_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
 588         { }
 589 };
 590
 591 static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
 592         .cmd_rcgr = 0x20e0,
 593         .mnd_width = 0,
 594         .hid_width = 5,
 595         .parent_map = disp_cc_parent_map_5,
 596         .freq_tbl = ftbl_disp_cc_mdss_rot_clk_src,
 597         .clkr.hw.init = &(struct clk_init_data){
 598                 .name = "disp_cc_mdss_rot_clk_src",
 599                 .parent_data = disp_cc_parent_data_5,
 600                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
 601                 .flags = CLK_SET_RATE_PARENT,
 602                 .ops = &clk_rcg2_shared_ops,
 603         },
 604 };
 605
 606 static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
 607         .cmd_rcgr = 0x20f8,
 608         .mnd_width = 0,
 609         .hid_width = 5,
 610         .parent_map = disp_cc_parent_map_1,
 611         .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
 612         .clkr.hw.init = &(struct clk_init_data){
 613                 .name = "disp_cc_mdss_vsync_clk_src",
 614                 .parent_data = disp_cc_parent_data_1,
 615                 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
 616                 .flags = CLK_SET_RATE_PARENT,
 617                 .ops = &clk_rcg2_ops,
 618         },
 619 };
 620
 621 static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = {
 622         .reg = 0x2128,
 623         .shift = 0,
 624         .width = 2,
 625         .clkr.hw.init = &(struct clk_init_data) {
 626                 .name = "disp_cc_mdss_byte0_div_clk_src",
 627                 .parent_hws = (const struct clk_hw*[]){
 628                         &disp_cc_mdss_byte0_clk_src.clkr.hw,
 629                 },
 630                 .num_parents = 1,
 631                 .ops = &clk_regmap_div_ops,
 632         },
 633 };
 634
 635
 636 static struct clk_regmap_div disp_cc_mdss_byte1_div_clk_src = {
 637         .reg = 0x2144,
 638         .shift = 0,
 639         .width = 2,
 640         .clkr.hw.init = &(struct clk_init_data) {
 641                 .name = "disp_cc_mdss_byte1_div_clk_src",
 642                 .parent_hws = (const struct clk_hw*[]){
 643                         &disp_cc_mdss_byte1_clk_src.clkr.hw,
 644                 },
 645                 .num_parents = 1,
 646                 .ops = &clk_regmap_div_ops,
 647         },
 648 };
 649
 650
 651 static struct clk_regmap_div disp_cc_mdss_dp_link1_div_clk_src = {
 652         .reg = 0x2224,
 653         .shift = 0,
 654         .width = 2,
 655         .clkr.hw.init = &(struct clk_init_data) {
 656                 .name = "disp_cc_mdss_dp_link1_div_clk_src",
 657                 .parent_hws = (const struct clk_hw*[]){
 658                         &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
 659                 },
 660                 .num_parents = 1,
 661                 .ops = &clk_regmap_div_ro_ops,
 662         },
 663 };
 664
 665
 666 static struct clk_regmap_div disp_cc_mdss_dp_link_div_clk_src = {
 667         .reg = 0x2190,
 668         .shift = 0,
 669         .width = 2,
 670         .clkr.hw.init = &(struct clk_init_data) {
 671                 .name = "disp_cc_mdss_dp_link_div_clk_src",
 672                 .parent_hws = (const struct clk_hw*[]){
 673                         &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 674                 },
 675                 .num_parents = 1,
 676                 .ops = &clk_regmap_div_ro_ops,
 677         },
 678 };
 679
 680 static struct clk_branch disp_cc_mdss_ahb_clk = {
 681         .halt_reg = 0x2080,
 682         .halt_check = BRANCH_HALT,
 683         .clkr = {
 684                 .enable_reg = 0x2080,
 685                 .enable_mask = BIT(0),
 686                 .hw.init = &(struct clk_init_data){
 687                         .name = "disp_cc_mdss_ahb_clk",
 688                         .parent_hws = (const struct clk_hw*[]){
 689                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
 690                         },
 691                         .num_parents = 1,
 692                         .flags = CLK_SET_RATE_PARENT,
 693                         .ops = &clk_branch2_ops,
 694                 },
 695         },
 696 };
 697
 698 static struct clk_branch disp_cc_mdss_byte0_clk = {
 699         .halt_reg = 0x2028,
 700         .halt_check = BRANCH_HALT,
 701         .clkr = {
 702                 .enable_reg = 0x2028,
 703                 .enable_mask = BIT(0),
 704                 .hw.init = &(struct clk_init_data){
 705                         .name = "disp_cc_mdss_byte0_clk",
 706                         .parent_hws = (const struct clk_hw*[]){
 707                                 &disp_cc_mdss_byte0_clk_src.clkr.hw,
 708                         },
 709                         .num_parents = 1,
 710                         .flags = CLK_SET_RATE_PARENT,
 711                         .ops = &clk_branch2_ops,
 712                 },
 713         },
 714 };
 715
 716 static struct clk_branch disp_cc_mdss_byte0_intf_clk = {
 717         .halt_reg = 0x202c,
 718         .halt_check = BRANCH_HALT,
 719         .clkr = {
 720                 .enable_reg = 0x202c,
 721                 .enable_mask = BIT(0),
 722                 .hw.init = &(struct clk_init_data){
 723                         .name = "disp_cc_mdss_byte0_intf_clk",
 724                         .parent_hws = (const struct clk_hw*[]){
 725                                 &disp_cc_mdss_byte0_div_clk_src.clkr.hw,
 726                         },
 727                         .num_parents = 1,
 728                         .flags = CLK_SET_RATE_PARENT,
 729                         .ops = &clk_branch2_ops,
 730                 },
 731         },
 732 };
 733
 734 static struct clk_branch disp_cc_mdss_byte1_clk = {
 735         .halt_reg = 0x2030,
 736         .halt_check = BRANCH_HALT,
 737         .clkr = {
 738                 .enable_reg = 0x2030,
 739                 .enable_mask = BIT(0),
 740                 .hw.init = &(struct clk_init_data){
 741                         .name = "disp_cc_mdss_byte1_clk",
 742                         .parent_hws = (const struct clk_hw*[]){
 743                                 &disp_cc_mdss_byte1_clk_src.clkr.hw,
 744                         },
 745                         .num_parents = 1,
 746                         .flags = CLK_SET_RATE_PARENT,
 747                         .ops = &clk_branch2_ops,
 748                 },
 749         },
 750 };
 751
 752 static struct clk_branch disp_cc_mdss_byte1_intf_clk = {
 753         .halt_reg = 0x2034,
 754         .halt_check = BRANCH_HALT,
 755         .clkr = {
 756                 .enable_reg = 0x2034,
 757                 .enable_mask = BIT(0),
 758                 .hw.init = &(struct clk_init_data){
 759                         .name = "disp_cc_mdss_byte1_intf_clk",
 760                         .parent_hws = (const struct clk_hw*[]){
 761                                 &disp_cc_mdss_byte1_div_clk_src.clkr.hw,
 762                         },
 763                         .num_parents = 1,
 764                         .flags = CLK_SET_RATE_PARENT,
 765                         .ops = &clk_branch2_ops,
 766                 },
 767         },
 768 };
 769
 770 static struct clk_branch disp_cc_mdss_dp_aux1_clk = {
 771         .halt_reg = 0x2068,
 772         .halt_check = BRANCH_HALT,
 773         .clkr = {
 774                 .enable_reg = 0x2068,
 775                 .enable_mask = BIT(0),
 776                 .hw.init = &(struct clk_init_data){
 777                         .name = "disp_cc_mdss_dp_aux1_clk",
 778                         .parent_hws = (const struct clk_hw*[]){
 779                                 &disp_cc_mdss_dp_aux1_clk_src.clkr.hw,
 780                         },
 781                         .num_parents = 1,
 782                         .flags = CLK_SET_RATE_PARENT,
 783                         .ops = &clk_branch2_ops,
 784                 },
 785         },
 786 };
 787
 788 static struct clk_branch disp_cc_mdss_dp_aux_clk = {
 789         .halt_reg = 0x2054,
 790         .halt_check = BRANCH_HALT,
 791         .clkr = {
 792                 .enable_reg = 0x2054,
 793                 .enable_mask = BIT(0),
 794                 .hw.init = &(struct clk_init_data){
 795                         .name = "disp_cc_mdss_dp_aux_clk",
 796                         .parent_hws = (const struct clk_hw*[]){
 797                                 &disp_cc_mdss_dp_aux_clk_src.clkr.hw,
 798                         },
 799                         .num_parents = 1,
 800                         .flags = CLK_SET_RATE_PARENT,
 801                         .ops = &clk_branch2_ops,
 802                 },
 803         },
 804 };
 805
 806 static struct clk_branch disp_cc_mdss_dp_link1_clk = {
 807         .halt_reg = 0x205c,
 808         .halt_check = BRANCH_HALT,
 809         .clkr = {
 810                 .enable_reg = 0x205c,
 811                 .enable_mask = BIT(0),
 812                 .hw.init = &(struct clk_init_data){
 813                         .name = "disp_cc_mdss_dp_link1_clk",
 814                         .parent_hws = (const struct clk_hw*[]){
 815                                 &disp_cc_mdss_dp_link1_clk_src.clkr.hw,
 816                         },
 817                         .num_parents = 1,
 818                         .flags = CLK_SET_RATE_PARENT,
 819                         .ops = &clk_branch2_ops,
 820                 },
 821         },
 822 };
 823
 824 static struct clk_branch disp_cc_mdss_dp_link1_intf_clk = {
 825         .halt_reg = 0x2060,
 826         .halt_check = BRANCH_HALT,
 827         .clkr = {
 828                 .enable_reg = 0x2060,
 829                 .enable_mask = BIT(0),
 830                 .hw.init = &(struct clk_init_data){
 831                         .name = "disp_cc_mdss_dp_link1_intf_clk",
 832                         .parent_hws = (const struct clk_hw*[]){
 833                                 &disp_cc_mdss_dp_link1_div_clk_src.clkr.hw,
 834                         },
 835                         .num_parents = 1,
 836                         .ops = &clk_branch2_ops,
 837                 },
 838         },
 839 };
 840
 841 static struct clk_branch disp_cc_mdss_dp_link_clk = {
 842         .halt_reg = 0x2040,
 843         .halt_check = BRANCH_HALT,
 844         .clkr = {
 845                 .enable_reg = 0x2040,
 846                 .enable_mask = BIT(0),
 847                 .hw.init = &(struct clk_init_data){
 848                         .name = "disp_cc_mdss_dp_link_clk",
 849                         .parent_hws = (const struct clk_hw*[]){
 850                                 &disp_cc_mdss_dp_link_clk_src.clkr.hw,
 851                         },
 852                         .num_parents = 1,
 853                         .flags = CLK_SET_RATE_PARENT,
 854                         .ops = &clk_branch2_ops,
 855                 },
 856         },
 857 };
 858
 859 static struct clk_branch disp_cc_mdss_dp_link_intf_clk = {
 860         .halt_reg = 0x2044,
 861         .halt_check = BRANCH_HALT,
 862         .clkr = {
 863                 .enable_reg = 0x2044,
 864                 .enable_mask = BIT(0),
 865                 .hw.init = &(struct clk_init_data){
 866                         .name = "disp_cc_mdss_dp_link_intf_clk",
 867                         .parent_hws = (const struct clk_hw*[]){
 868                                 &disp_cc_mdss_dp_link_div_clk_src.clkr.hw,
 869                         },
 870                         .num_parents = 1,
 871                         .ops = &clk_branch2_ops,
 872                 },
 873         },
 874 };
 875
 876 static struct clk_branch disp_cc_mdss_dp_pixel1_clk = {
 877         .halt_reg = 0x2050,
 878         .halt_check = BRANCH_HALT,
 879         .clkr = {
 880                 .enable_reg = 0x2050,
 881                 .enable_mask = BIT(0),
 882                 .hw.init = &(struct clk_init_data){
 883                         .name = "disp_cc_mdss_dp_pixel1_clk",
 884                         .parent_hws = (const struct clk_hw*[]){
 885                                 &disp_cc_mdss_dp_pixel1_clk_src.clkr.hw,
 886                         },
 887                         .num_parents = 1,
 888                         .flags = CLK_SET_RATE_PARENT,
 889                         .ops = &clk_branch2_ops,
 890                 },
 891         },
 892 };
 893
 894 static struct clk_branch disp_cc_mdss_dp_pixel2_clk = {
 895         .halt_reg = 0x2058,
 896         .halt_check = BRANCH_HALT,
 897         .clkr = {
 898                 .enable_reg = 0x2058,
 899                 .enable_mask = BIT(0),
 900                 .hw.init = &(struct clk_init_data){
 901                         .name = "disp_cc_mdss_dp_pixel2_clk",
 902                         .parent_hws = (const struct clk_hw*[]){
 903                                 &disp_cc_mdss_dp_pixel2_clk_src.clkr.hw,
 904                         },
 905                         .num_parents = 1,
 906                         .flags = CLK_SET_RATE_PARENT,
 907                         .ops = &clk_branch2_ops,
 908                 },
 909         },
 910 };
 911
 912 static struct clk_branch disp_cc_mdss_dp_pixel_clk = {
 913         .halt_reg = 0x204c,
 914         .halt_check = BRANCH_HALT,
 915         .clkr = {
 916                 .enable_reg = 0x204c,
 917                 .enable_mask = BIT(0),
 918                 .hw.init = &(struct clk_init_data){
 919                         .name = "disp_cc_mdss_dp_pixel_clk",
 920                         .parent_hws = (const struct clk_hw*[]){
 921                                 &disp_cc_mdss_dp_pixel_clk_src.clkr.hw,
 922                         },
 923                         .num_parents = 1,
 924                         .flags = CLK_SET_RATE_PARENT,
 925                         .ops = &clk_branch2_ops,
 926                 },
 927         },
 928 };
 929
 930 static struct clk_branch disp_cc_mdss_esc0_clk = {
 931         .halt_reg = 0x2038,
 932         .halt_check = BRANCH_HALT,
 933         .clkr = {
 934                 .enable_reg = 0x2038,
 935                 .enable_mask = BIT(0),
 936                 .hw.init = &(struct clk_init_data){
 937                         .name = "disp_cc_mdss_esc0_clk",
 938                         .parent_hws = (const struct clk_hw*[]){
 939                                 &disp_cc_mdss_esc0_clk_src.clkr.hw,
 940                         },
 941                         .num_parents = 1,
 942                         .flags = CLK_SET_RATE_PARENT,
 943                         .ops = &clk_branch2_ops,
 944                 },
 945         },
 946 };
 947
 948 static struct clk_branch disp_cc_mdss_esc1_clk = {
 949         .halt_reg = 0x203c,
 950         .halt_check = BRANCH_HALT,
 951         .clkr = {
 952                 .enable_reg = 0x203c,
 953                 .enable_mask = BIT(0),
 954                 .hw.init = &(struct clk_init_data){
 955                         .name = "disp_cc_mdss_esc1_clk",
 956                         .parent_hws = (const struct clk_hw*[]){
 957                                 &disp_cc_mdss_esc1_clk_src.clkr.hw,
 958                         },
 959                         .num_parents = 1,
 960                         .flags = CLK_SET_RATE_PARENT,
 961                         .ops = &clk_branch2_ops,
 962                 },
 963         },
 964 };
 965
 966 static struct clk_branch disp_cc_mdss_mdp_clk = {
 967         .halt_reg = 0x200c,
 968         .halt_check = BRANCH_HALT,
 969         .clkr = {
 970                 .enable_reg = 0x200c,
 971                 .enable_mask = BIT(0),
 972                 .hw.init = &(struct clk_init_data){
 973                         .name = "disp_cc_mdss_mdp_clk",
 974                         .parent_hws = (const struct clk_hw*[]){
 975                                 &disp_cc_mdss_mdp_clk_src.clkr.hw,
 976                         },
 977                         .num_parents = 1,
 978                         .flags = CLK_SET_RATE_PARENT,
 979                         .ops = &clk_branch2_ops,
 980                 },
 981         },
 982 };
 983
 984 static struct clk_branch disp_cc_mdss_mdp_lut_clk = {
 985         .halt_reg = 0x201c,
 986         .halt_check = BRANCH_VOTED,
 987         .clkr = {
 988                 .enable_reg = 0x201c,
 989                 .enable_mask = BIT(0),
 990                 .hw.init = &(struct clk_init_data){
 991                         .name = "disp_cc_mdss_mdp_lut_clk",
 992                         .parent_hws = (const struct clk_hw*[]){
 993                                 &disp_cc_mdss_mdp_clk_src.clkr.hw,
 994                         },
 995                         .num_parents = 1,
 996                         .ops = &clk_branch2_ops,
 997                 },
 998         },
 999 };
1000
1001 static struct clk_branch disp_cc_mdss_non_gdsc_ahb_clk = {
1002         .halt_reg = 0x4004,
1003         .halt_check = BRANCH_VOTED,
1004         .clkr = {
1005                 .enable_reg = 0x4004,
1006                 .enable_mask = BIT(0),
1007                 .hw.init = &(struct clk_init_data){
1008                         .name = "disp_cc_mdss_non_gdsc_ahb_clk",
1009                         .parent_hws = (const struct clk_hw*[]){
1010                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1011                         },
1012                         .num_parents = 1,
1013                         .flags = CLK_SET_RATE_PARENT,
1014                         .ops = &clk_branch2_ops,
1015                 },
1016         },
1017 };
1018
1019 static struct clk_branch disp_cc_mdss_pclk0_clk = {
1020         .halt_reg = 0x2004,
1021         .halt_check = BRANCH_HALT,
1022         .clkr = {
1023                 .enable_reg = 0x2004,
1024                 .enable_mask = BIT(0),
1025                 .hw.init = &(struct clk_init_data){
1026                         .name = "disp_cc_mdss_pclk0_clk",
1027                         .parent_hws = (const struct clk_hw*[]){
1028                                 &disp_cc_mdss_pclk0_clk_src.clkr.hw,
1029                         },
1030                         .num_parents = 1,
1031                         .flags = CLK_SET_RATE_PARENT,
1032                         .ops = &clk_branch2_ops,
1033                 },
1034         },
1035 };
1036
1037 static struct clk_branch disp_cc_mdss_pclk1_clk = {
1038         .halt_reg = 0x2008,
1039         .halt_check = BRANCH_HALT,
1040         .clkr = {
1041                 .enable_reg = 0x2008,
1042                 .enable_mask = BIT(0),
1043                 .hw.init = &(struct clk_init_data){
1044                         .name = "disp_cc_mdss_pclk1_clk",
1045                         .parent_hws = (const struct clk_hw*[]){
1046                                 &disp_cc_mdss_pclk1_clk_src.clkr.hw,
1047                         },
1048                         .num_parents = 1,
1049                         .flags = CLK_SET_RATE_PARENT,
1050                         .ops = &clk_branch2_ops,
1051                 },
1052         },
1053 };
1054
1055 static struct clk_branch disp_cc_mdss_rot_clk = {
1056         .halt_reg = 0x2014,
1057         .halt_check = BRANCH_HALT,
1058         .clkr = {
1059                 .enable_reg = 0x2014,
1060                 .enable_mask = BIT(0),
1061                 .hw.init = &(struct clk_init_data){
1062                         .name = "disp_cc_mdss_rot_clk",
1063                         .parent_hws = (const struct clk_hw*[]){
1064                                 &disp_cc_mdss_rot_clk_src.clkr.hw,
1065                         },
1066                         .num_parents = 1,
1067                         .flags = CLK_SET_RATE_PARENT,
1068                         .ops = &clk_branch2_ops,
1069                 },
1070         },
1071 };
1072
1073 static struct clk_branch disp_cc_mdss_rscc_ahb_clk = {
1074         .halt_reg = 0x400c,
1075         .halt_check = BRANCH_HALT,
1076         .clkr = {
1077                 .enable_reg = 0x400c,
1078                 .enable_mask = BIT(0),
1079                 .hw.init = &(struct clk_init_data){
1080                         .name = "disp_cc_mdss_rscc_ahb_clk",
1081                         .parent_hws = (const struct clk_hw*[]){
1082                                 &disp_cc_mdss_ahb_clk_src.clkr.hw,
1083                         },
1084                         .num_parents = 1,
1085                         .flags = CLK_SET_RATE_PARENT,
1086                         .ops = &clk_branch2_ops,
1087                 },
1088         },
1089 };
1090
1091 static struct clk_branch disp_cc_mdss_rscc_vsync_clk = {
1092         .halt_reg = 0x4008,
1093         .halt_check = BRANCH_HALT,
1094         .clkr = {
1095                 .enable_reg = 0x4008,
1096                 .enable_mask = BIT(0),
1097                 .hw.init = &(struct clk_init_data){
1098                         .name = "disp_cc_mdss_rscc_vsync_clk",
1099                         .parent_hws = (const struct clk_hw*[]){
1100                                 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1101                         },
1102                         .num_parents = 1,
1103                         .flags = CLK_SET_RATE_PARENT,
1104                         .ops = &clk_branch2_ops,
1105                 },
1106         },
1107 };
1108
1109 static struct clk_branch disp_cc_mdss_vsync_clk = {
1110         .halt_reg = 0x2024,
1111         .halt_check = BRANCH_HALT,
1112         .clkr = {
1113                 .enable_reg = 0x2024,
1114                 .enable_mask = BIT(0),
1115                 .hw.init = &(struct clk_init_data){
1116                         .name = "disp_cc_mdss_vsync_clk",
1117                         .parent_hws = (const struct clk_hw*[]){
1118                                 &disp_cc_mdss_vsync_clk_src.clkr.hw,
1119                         },
1120                         .num_parents = 1,
1121                         .flags = CLK_SET_RATE_PARENT,
1122                         .ops = &clk_branch2_ops,
1123                 },
1124         },
1125 };
1126
1127 static struct gdsc mdss_gdsc = {
1128         .gdscr = 0x3000,
1129         .en_rest_wait_val = 0x2,
1130         .en_few_wait_val = 0x2,
1131         .clk_dis_wait_val = 0xf,
1132         .pd = {
1133                 .name = "mdss_gdsc",
1134         },
1135         .pwrsts = PWRSTS_OFF_ON,
1136         .flags = HW_CTRL,
1137         .supply = "mmcx",
1138 };
1139
1140 static struct clk_regmap *disp_cc_sm8250_clocks[] = {
1141         [DISP_CC_MDSS_AHB_CLK] = &disp_cc_mdss_ahb_clk.clkr,
1142         [DISP_CC_MDSS_AHB_CLK_SRC] = &disp_cc_mdss_ahb_clk_src.clkr,
1143         [DISP_CC_MDSS_BYTE0_CLK] = &disp_cc_mdss_byte0_clk.clkr,
1144         [DISP_CC_MDSS_BYTE0_CLK_SRC] = &disp_cc_mdss_byte0_clk_src.clkr,
1145         [DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &disp_cc_mdss_byte0_div_clk_src.clkr,
1146         [DISP_CC_MDSS_BYTE0_INTF_CLK] = &disp_cc_mdss_byte0_intf_clk.clkr,
1147         [DISP_CC_MDSS_BYTE1_CLK] = &disp_cc_mdss_byte1_clk.clkr,
1148         [DISP_CC_MDSS_BYTE1_CLK_SRC] = &disp_cc_mdss_byte1_clk_src.clkr,
1149         [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr,
1150         [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr,
1151         [DISP_CC_MDSS_DP_AUX1_CLK] = &disp_cc_mdss_dp_aux1_clk.clkr,
1152         [DISP_CC_MDSS_DP_AUX1_CLK_SRC] = &disp_cc_mdss_dp_aux1_clk_src.clkr,
1153         [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr,
1154         [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr,
1155         [DISP_CC_MDSS_DP_LINK1_CLK] = &disp_cc_mdss_dp_link1_clk.clkr,
1156         [DISP_CC_MDSS_DP_LINK1_CLK_SRC] = &disp_cc_mdss_dp_link1_clk_src.clkr,
1157         [DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC] = &disp_cc_mdss_dp_link1_div_clk_src.clkr,
1158         [DISP_CC_MDSS_DP_LINK1_INTF_CLK] = &disp_cc_mdss_dp_link1_intf_clk.clkr,
1159         [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr,
1160         [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr,
1161         [DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC] = &disp_cc_mdss_dp_link_div_clk_src.clkr,
1162         [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr,
1163         [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr,
1164         [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = &disp_cc_mdss_dp_pixel1_clk_src.clkr,
1165         [DISP_CC_MDSS_DP_PIXEL2_CLK] = &disp_cc_mdss_dp_pixel2_clk.clkr,
1166         [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
1167         [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
1168         [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
1169         [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
1170         [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
1171         [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
1172         [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
1173         [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
1174         [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
1175         [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
1176         [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
1177         [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
1178         [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
1179         [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
1180         [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,
1181         [DISP_CC_MDSS_ESC1_CLK_SRC] = &disp_cc_mdss_esc1_clk_src.clkr,
1182         [DISP_CC_MDSS_MDP_CLK] = &disp_cc_mdss_mdp_clk.clkr,
1183         [DISP_CC_MDSS_MDP_CLK_SRC] = &disp_cc_mdss_mdp_clk_src.clkr,
1184         [DISP_CC_MDSS_MDP_LUT_CLK] = &disp_cc_mdss_mdp_lut_clk.clkr,
1185         [DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &disp_cc_mdss_non_gdsc_ahb_clk.clkr,
1186         [DISP_CC_MDSS_PCLK0_CLK] = &disp_cc_mdss_pclk0_clk.clkr,
1187         [DISP_CC_MDSS_PCLK0_CLK_SRC] = &disp_cc_mdss_pclk0_clk_src.clkr,
1188         [DISP_CC_MDSS_PCLK1_CLK] = &disp_cc_mdss_pclk1_clk.clkr,
1189         [DISP_CC_MDSS_PCLK1_CLK_SRC] = &disp_cc_mdss_pclk1_clk_src.clkr,
1190         [DISP_CC_MDSS_ROT_CLK] = &disp_cc_mdss_rot_clk.clkr,
1191         [DISP_CC_MDSS_ROT_CLK_SRC] = &disp_cc_mdss_rot_clk_src.clkr,
1192         [DISP_CC_MDSS_RSCC_AHB_CLK] = &disp_cc_mdss_rscc_ahb_clk.clkr,
1193         [DISP_CC_MDSS_RSCC_VSYNC_CLK] = &disp_cc_mdss_rscc_vsync_clk.clkr,
1194         [DISP_CC_MDSS_VSYNC_CLK] = &disp_cc_mdss_vsync_clk.clkr,
1195         [DISP_CC_MDSS_VSYNC_CLK_SRC] = &disp_cc_mdss_vsync_clk_src.clkr,
1196         [DISP_CC_PLL0] = &disp_cc_pll0.clkr,
1197         [DISP_CC_PLL1] = &disp_cc_pll1.clkr,
1198 };
1199
1200 static const struct qcom_reset_map disp_cc_sm8250_resets[] = {
1201         [DISP_CC_MDSS_CORE_BCR] = { 0x2000 },
1202         [DISP_CC_MDSS_RSCC_BCR] = { 0x4000 },
1203 };
1204
1205 static struct gdsc *disp_cc_sm8250_gdscs[] = {
1206         [MDSS_GDSC] = &mdss_gdsc,
1207 };
1208
1209 static const struct regmap_config disp_cc_sm8250_regmap_config = {
1210         .reg_bits       = 32,
1211         .reg_stride     = 4,
1212         .val_bits       = 32,
1213         .max_register   = 0x10000,
1214         .fast_io        = true,
1215 };
1216
1217 static const struct qcom_cc_desc disp_cc_sm8250_desc = {
1218         .config = &disp_cc_sm8250_regmap_config,
1219         .clks = disp_cc_sm8250_clocks,
1220         .num_clks = ARRAY_SIZE(disp_cc_sm8250_clocks),
1221         .resets = disp_cc_sm8250_resets,
1222         .num_resets = ARRAY_SIZE(disp_cc_sm8250_resets),
1223         .gdscs = disp_cc_sm8250_gdscs,
1224         .num_gdscs = ARRAY_SIZE(disp_cc_sm8250_gdscs),
1225 };
1226
1227 static const struct of_device_id disp_cc_sm8250_match_table[] = {
1228         { .compatible = "qcom,sc8180x-dispcc" },
1229         { .compatible = "qcom,sm8150-dispcc" },
1230         { .compatible = "qcom,sm8250-dispcc" },
1231         { }
1232 };
1233 MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
1234
1235 static void disp_cc_sm8250_pm_runtime_disable(void *data)
1236 {
1237         pm_runtime_disable(data);
1238 }
1239
1240 static int disp_cc_sm8250_probe(struct platform_device *pdev)
1241 {
1242         struct regmap *regmap;
1243         int ret;
1244
1245         pm_runtime_enable(&pdev->dev);
1246
1247         ret = devm_add_action_or_reset(&pdev->dev, disp_cc_sm8250_pm_runtime_disable, &pdev->dev);
1248         if (ret)
1249                 return ret;
1250
1251         ret = pm_runtime_resume_and_get(&pdev->dev);
1252         if (ret)
1253                 return ret;
1254
1255         regmap = qcom_cc_map(pdev, &disp_cc_sm8250_desc);
1256         if (IS_ERR(regmap)) {
1257                 pm_runtime_put(&pdev->dev);
1258                 return PTR_ERR(regmap);
1259         }
1260
1261         /* note: trion == lucid, except for the prepare() op */
1262         BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1263         if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1264             of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
1265                 disp_cc_pll0_config.config_ctl_hi_val = 0x00002267;
1266                 disp_cc_pll0_config.config_ctl_hi1_val = 0x00000024;
1267                 disp_cc_pll0_config.user_ctl_hi1_val = 0x000000D0;
1268                 disp_cc_pll0_init.ops = &clk_alpha_pll_trion_ops;
1269                 disp_cc_pll1_config.config_ctl_hi_val = 0x00002267;
1270                 disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1271                 disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1272                 disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1273         }
1274
1275         clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
1276         clk_lucid_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
1277
1278         /* Enable clock gating for MDP clocks */
1279         regmap_update_bits(regmap, 0x8000, 0x10, 0x10);
1280
1281         /* DISP_CC_XO_CLK always-on */
1282         regmap_update_bits(regmap, 0x605c, BIT(0), BIT(0));
1283
1284         ret = qcom_cc_really_probe(pdev, &disp_cc_sm8250_desc, regmap);
1285
1286         pm_runtime_put(&pdev->dev);
1287
1288         return ret;
1289 }
1290
1291 static struct platform_driver disp_cc_sm8250_driver = {
1292         .probe = disp_cc_sm8250_probe,
1293         .driver = {
1294                 .name = "disp_cc-sm8250",
1295                 .of_match_table = disp_cc_sm8250_match_table,
1296         },
1297 };
1298
1299 static int __init disp_cc_sm8250_init(void)
1300 {
1301         return platform_driver_register(&disp_cc_sm8250_driver);
1302 }
1303 subsys_initcall(disp_cc_sm8250_init);
1304
1305 static void __exit disp_cc_sm8250_exit(void)
1306 {
1307         platform_driver_unregister(&disp_cc_sm8250_driver);
1308 }
1309 module_exit(disp_cc_sm8250_exit);
1310
1311 MODULE_DESCRIPTION("QTI DISPCC SM8250 Driver");
1312 MODULE_LICENSE("GPL v2");