drivers/clk/qcom/clk-smd-rpm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, Linaro Limited
   4  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/soc/qcom/smd-rpm.h>
  18
  19 #include <dt-bindings/clock/qcom,rpmcc.h>
  20
  21 #define QCOM_RPM_KEY_SOFTWARE_ENABLE                    0x6e657773
  22 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY     0x62636370
  23 #define QCOM_RPM_SMD_KEY_RATE                           0x007a484b
  24 #define QCOM_RPM_SMD_KEY_ENABLE                         0x62616e45
  25 #define QCOM_RPM_SMD_KEY_STATE                          0x54415453
  26 #define QCOM_RPM_SCALING_ENABLE_ID                      0x2
  27
  28 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \
  29                              key)                                             \
  30         static struct clk_smd_rpm _platform##_##_active;                      \
  31         static struct clk_smd_rpm _platform##_##_name = {                     \
  32                 .rpm_res_type = (type),                                       \
  33                 .rpm_clk_id = (r_id),                                         \
  34                 .rpm_status_id = (stat_id),                                   \
  35                 .rpm_key = (key),                                             \
  36                 .peer = &_platform##_##_active,                               \
  37                 .rate = INT_MAX,                                              \
  38                 .hw.init = &(struct clk_init_data){                           \
  39                         .ops = &clk_smd_rpm_ops,                              \
  40                         .name = #_name,                                       \
  41                         .parent_data =  &(const struct clk_parent_data){ \
  42                                         .fw_name = "xo",                \
  43                                         .name = "xo_board",             \
  44                         },                                              \
  45                         .num_parents = 1,                                     \
  46                 },                                                            \
  47         };                                                                    \
  48         static struct clk_smd_rpm _platform##_##_active = {                   \
  49                 .rpm_res_type = (type),                                       \
  50                 .rpm_clk_id = (r_id),                                         \
  51                 .rpm_status_id = (stat_id),                                   \
  52                 .active_only = true,                                          \
  53                 .rpm_key = (key),                                             \
  54                 .peer = &_platform##_##_name,                                 \
  55                 .rate = INT_MAX,                                              \
  56                 .hw.init = &(struct clk_init_data){                           \
  57                         .ops = &clk_smd_rpm_ops,                              \
  58                         .name = #_active,                                     \
  59                         .parent_data =  &(const struct clk_parent_data){ \
  60                                         .fw_name = "xo",                \
  61                                         .name = "xo_board",             \
  62                         },                                              \
  63                         .num_parents = 1,                                     \
  64                 },                                                            \
  65         }
  66
  67 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \
  68                                     stat_id, r, key)                          \
  69         static struct clk_smd_rpm _platform##_##_active;                      \
  70         static struct clk_smd_rpm _platform##_##_name = {                     \
  71                 .rpm_res_type = (type),                                       \
  72                 .rpm_clk_id = (r_id),                                         \
  73                 .rpm_status_id = (stat_id),                                   \
  74                 .rpm_key = (key),                                             \
  75                 .branch = true,                                               \
  76                 .peer = &_platform##_##_active,                               \
  77                 .rate = (r),                                                  \
  78                 .hw.init = &(struct clk_init_data){                           \
  79                         .ops = &clk_smd_rpm_branch_ops,                       \
  80                         .name = #_name,                                       \
  81                         .parent_data =  &(const struct clk_parent_data){ \
  82                                         .fw_name = "xo",                \
  83                                         .name = "xo_board",             \
  84                         },                                              \
  85                         .num_parents = 1,                                     \
  86                 },                                                            \
  87         };                                                                    \
  88         static struct clk_smd_rpm _platform##_##_active = {                   \
  89                 .rpm_res_type = (type),                                       \
  90                 .rpm_clk_id = (r_id),                                         \
  91                 .rpm_status_id = (stat_id),                                   \
  92                 .active_only = true,                                          \
  93                 .rpm_key = (key),                                             \
  94                 .branch = true,                                               \
  95                 .peer = &_platform##_##_name,                                 \
  96                 .rate = (r),                                                  \
  97                 .hw.init = &(struct clk_init_data){                           \
  98                         .ops = &clk_smd_rpm_branch_ops,                       \
  99                         .name = #_active,                                     \
 100                         .parent_data =  &(const struct clk_parent_data){ \
 101                                         .fw_name = "xo",                \
 102                                         .name = "xo_board",             \
 103                         },                                              \
 104                         .num_parents = 1,                                     \
 105                 },                                                            \
 106         }
 107
 108 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id)             \
 109                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 110                 0, QCOM_RPM_SMD_KEY_RATE)
 111
 112 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r)   \
 113                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type,  \
 114                 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
 115
 116 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id)        \
 117                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 118                 0, QCOM_RPM_SMD_KEY_STATE)
 119
 120 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r)      \
 121                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 122                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 123                 QCOM_RPM_KEY_SOFTWARE_ENABLE)
 124
 125 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active,       \
 126                                              r_id, r)                         \
 127                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 128                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 129                 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
 130
 131 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
 132
 133 struct clk_smd_rpm {
 134         const int rpm_res_type;
 135         const int rpm_key;
 136         const int rpm_clk_id;
 137         const int rpm_status_id;
 138         const bool active_only;
 139         bool enabled;
 140         bool branch;
 141         struct clk_smd_rpm *peer;
 142         struct clk_hw hw;
 143         unsigned long rate;
 144         struct qcom_smd_rpm *rpm;
 145 };
 146
 147 struct clk_smd_rpm_req {
 148         __le32 key;
 149         __le32 nbytes;
 150         __le32 value;
 151 };
 152
 153 struct rpm_smd_clk_desc {
 154         struct clk_smd_rpm **clks;
 155         size_t num_clks;
 156 };
 157
 158 static DEFINE_MUTEX(rpm_smd_clk_lock);
 159
 160 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
 161 {
 162         int ret;
 163         struct clk_smd_rpm_req req = {
 164                 .key = cpu_to_le32(r->rpm_key),
 165                 .nbytes = cpu_to_le32(sizeof(u32)),
 166                 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
 167         };
 168
 169         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 170                                  r->rpm_res_type, r->rpm_clk_id, &req,
 171                                  sizeof(req));
 172         if (ret)
 173                 return ret;
 174         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 175                                  r->rpm_res_type, r->rpm_clk_id, &req,
 176                                  sizeof(req));
 177         if (ret)
 178                 return ret;
 179
 180         return 0;
 181 }
 182
 183 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
 184                                        unsigned long rate)
 185 {
 186         struct clk_smd_rpm_req req = {
 187                 .key = cpu_to_le32(r->rpm_key),
 188                 .nbytes = cpu_to_le32(sizeof(u32)),
 189                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 190         };
 191
 192         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 193                                   r->rpm_res_type, r->rpm_clk_id, &req,
 194                                   sizeof(req));
 195 }
 196
 197 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
 198                                       unsigned long rate)
 199 {
 200         struct clk_smd_rpm_req req = {
 201                 .key = cpu_to_le32(r->rpm_key),
 202                 .nbytes = cpu_to_le32(sizeof(u32)),
 203                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 204         };
 205
 206         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 207                                   r->rpm_res_type, r->rpm_clk_id, &req,
 208                                   sizeof(req));
 209 }
 210
 211 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
 212                             unsigned long *active, unsigned long *sleep)
 213 {
 214         *active = rate;
 215
 216         /*
 217          * Active-only clocks don't care what the rate is during sleep. So,
 218          * they vote for zero.
 219          */
 220         if (r->active_only)
 221                 *sleep = 0;
 222         else
 223                 *sleep = *active;
 224 }
 225
 226 static int clk_smd_rpm_prepare(struct clk_hw *hw)
 227 {
 228         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 229         struct clk_smd_rpm *peer = r->peer;
 230         unsigned long this_rate = 0, this_sleep_rate = 0;
 231         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 232         unsigned long active_rate, sleep_rate;
 233         int ret = 0;
 234
 235         mutex_lock(&rpm_smd_clk_lock);
 236
 237         /* Don't send requests to the RPM if the rate has not been set. */
 238         if (!r->rate)
 239                 goto out;
 240
 241         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
 242
 243         /* Take peer clock's rate into account only if it's enabled. */
 244         if (peer->enabled)
 245                 to_active_sleep(peer, peer->rate,
 246                                 &peer_rate, &peer_sleep_rate);
 247
 248         active_rate = max(this_rate, peer_rate);
 249
 250         if (r->branch)
 251                 active_rate = !!active_rate;
 252
 253         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 254         if (ret)
 255                 goto out;
 256
 257         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 258         if (r->branch)
 259                 sleep_rate = !!sleep_rate;
 260
 261         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 262         if (ret)
 263                 /* Undo the active set vote and restore it */
 264                 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
 265
 266 out:
 267         if (!ret)
 268                 r->enabled = true;
 269
 270         mutex_unlock(&rpm_smd_clk_lock);
 271
 272         return ret;
 273 }
 274
 275 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
 276 {
 277         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 278         struct clk_smd_rpm *peer = r->peer;
 279         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 280         unsigned long active_rate, sleep_rate;
 281         int ret;
 282
 283         mutex_lock(&rpm_smd_clk_lock);
 284
 285         if (!r->rate)
 286                 goto out;
 287
 288         /* Take peer clock's rate into account only if it's enabled. */
 289         if (peer->enabled)
 290                 to_active_sleep(peer, peer->rate, &peer_rate,
 291                                 &peer_sleep_rate);
 292
 293         active_rate = r->branch ? !!peer_rate : peer_rate;
 294         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 295         if (ret)
 296                 goto out;
 297
 298         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 299         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 300         if (ret)
 301                 goto out;
 302
 303         r->enabled = false;
 304
 305 out:
 306         mutex_unlock(&rpm_smd_clk_lock);
 307 }
 308
 309 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
 310                                 unsigned long parent_rate)
 311 {
 312         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 313         struct clk_smd_rpm *peer = r->peer;
 314         unsigned long active_rate, sleep_rate;
 315         unsigned long this_rate = 0, this_sleep_rate = 0;
 316         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 317         int ret = 0;
 318
 319         mutex_lock(&rpm_smd_clk_lock);
 320
 321         if (!r->enabled)
 322                 goto out;
 323
 324         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 325
 326         /* Take peer clock's rate into account only if it's enabled. */
 327         if (peer->enabled)
 328                 to_active_sleep(peer, peer->rate,
 329                                 &peer_rate, &peer_sleep_rate);
 330
 331         active_rate = max(this_rate, peer_rate);
 332         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 333         if (ret)
 334                 goto out;
 335
 336         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 337         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 338         if (ret)
 339                 goto out;
 340
 341         r->rate = rate;
 342
 343 out:
 344         mutex_unlock(&rpm_smd_clk_lock);
 345
 346         return ret;
 347 }
 348
 349 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 350                                    unsigned long *parent_rate)
 351 {
 352         /*
 353          * RPM handles rate rounding and we don't have a way to
 354          * know what the rate will be, so just return whatever
 355          * rate is requested.
 356          */
 357         return rate;
 358 }
 359
 360 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 361                                              unsigned long parent_rate)
 362 {
 363         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 364
 365         /*
 366          * RPM handles rate rounding and we don't have a way to
 367          * know what the rate will be, so just return whatever
 368          * rate was set.
 369          */
 370         return r->rate;
 371 }
 372
 373 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
 374 {
 375         int ret;
 376         struct clk_smd_rpm_req req = {
 377                 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
 378                 .nbytes = cpu_to_le32(sizeof(u32)),
 379                 .value = cpu_to_le32(1),
 380         };
 381
 382         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
 383                                  QCOM_SMD_RPM_MISC_CLK,
 384                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 385         if (ret) {
 386                 pr_err("RPM clock scaling (sleep set) not enabled!\n");
 387                 return ret;
 388         }
 389
 390         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 391                                  QCOM_SMD_RPM_MISC_CLK,
 392                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 393         if (ret) {
 394                 pr_err("RPM clock scaling (active set) not enabled!\n");
 395                 return ret;
 396         }
 397
 398         pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 399         return 0;
 400 }
 401
 402 static const struct clk_ops clk_smd_rpm_ops = {
 403         .prepare        = clk_smd_rpm_prepare,
 404         .unprepare      = clk_smd_rpm_unprepare,
 405         .set_rate       = clk_smd_rpm_set_rate,
 406         .round_rate     = clk_smd_rpm_round_rate,
 407         .recalc_rate    = clk_smd_rpm_recalc_rate,
 408 };
 409
 410 static const struct clk_ops clk_smd_rpm_branch_ops = {
 411         .prepare        = clk_smd_rpm_prepare,
 412         .unprepare      = clk_smd_rpm_unprepare,
 413         .recalc_rate    = clk_smd_rpm_recalc_rate,
 414 };
 415
 416 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
 417 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 418 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 419 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 420 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 421 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
 422 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
 423 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000);
 424 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000);
 425 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000);
 426 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000);
 427 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
 428 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
 429
 430 static struct clk_smd_rpm *msm8916_clks[] = {
 431         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 432         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 433         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 434         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 435         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 436         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 437         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 438         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 439         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 440         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 441         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 442         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 443         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 444         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 445         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 446         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 447         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 448         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 449         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 450         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 451         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 452         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 453         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 454         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 455 };
 456
 457 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 458         .clks = msm8916_clks,
 459         .num_clks = ARRAY_SIZE(msm8916_clks),
 460 };
 461
 462 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 463
 464 static struct clk_smd_rpm *msm8936_clks[] = {
 465         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 466         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 467         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 468         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 469         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 470         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 471         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 472         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 473         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 474         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 475         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 476         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 477         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 478         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 479         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 480         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 481         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 482         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 483         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 484         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 485         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 486         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 487         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 488         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 489         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 490         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 491 };
 492
 493 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
 494                 .clks = msm8936_clks,
 495                 .num_clks = ARRAY_SIZE(msm8936_clks),
 496 };
 497
 498 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 499 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 500 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 501 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 502 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000);
 503 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000);
 504 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000);
 505 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000);
 506 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000);
 507 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000);
 508 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000);
 509 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000);
 510 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000);
 511 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000);
 512 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000);
 513 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000);
 514 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000);
 515
 516 static struct clk_smd_rpm *msm8974_clks[] = {
 517         [RPM_SMD_PNOC_CLK]              = &msm8916_pcnoc_clk,
 518         [RPM_SMD_PNOC_A_CLK]            = &msm8916_pcnoc_a_clk,
 519         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 520         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 521         [RPM_SMD_CNOC_CLK]              = &msm8974_cnoc_clk,
 522         [RPM_SMD_CNOC_A_CLK]            = &msm8974_cnoc_a_clk,
 523         [RPM_SMD_MMSSNOC_AHB_CLK]       = &msm8974_mmssnoc_ahb_clk,
 524         [RPM_SMD_MMSSNOC_AHB_A_CLK]     = &msm8974_mmssnoc_ahb_a_clk,
 525         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 526         [RPM_SMD_GFX3D_CLK_SRC]         = &msm8974_gfx3d_clk_src,
 527         [RPM_SMD_GFX3D_A_CLK_SRC]       = &msm8974_gfx3d_a_clk_src,
 528         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 529         [RPM_SMD_OCMEMGX_CLK]           = &msm8974_ocmemgx_clk,
 530         [RPM_SMD_OCMEMGX_A_CLK]         = &msm8974_ocmemgx_a_clk,
 531         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 532         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 533         [RPM_SMD_CXO_D0]                = &msm8974_cxo_d0,
 534         [RPM_SMD_CXO_D0_A]              = &msm8974_cxo_d0_a,
 535         [RPM_SMD_CXO_D1]                = &msm8974_cxo_d1,
 536         [RPM_SMD_CXO_D1_A]              = &msm8974_cxo_d1_a,
 537         [RPM_SMD_CXO_A0]                = &msm8974_cxo_a0,
 538         [RPM_SMD_CXO_A0_A]              = &msm8974_cxo_a0_a,
 539         [RPM_SMD_CXO_A1]                = &msm8974_cxo_a1,
 540         [RPM_SMD_CXO_A1_A]              = &msm8974_cxo_a1_a,
 541         [RPM_SMD_CXO_A2]                = &msm8974_cxo_a2,
 542         [RPM_SMD_CXO_A2_A]              = &msm8974_cxo_a2_a,
 543         [RPM_SMD_DIFF_CLK]              = &msm8974_diff_clk,
 544         [RPM_SMD_DIFF_A_CLK]            = &msm8974_diff_a_clk,
 545         [RPM_SMD_DIV_CLK1]              = &msm8974_div_clk1,
 546         [RPM_SMD_DIV_A_CLK1]            = &msm8974_div_a_clk1,
 547         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 548         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 549         [RPM_SMD_CXO_D0_PIN]            = &msm8974_cxo_d0_pin,
 550         [RPM_SMD_CXO_D0_A_PIN]          = &msm8974_cxo_d0_a_pin,
 551         [RPM_SMD_CXO_D1_PIN]            = &msm8974_cxo_d1_pin,
 552         [RPM_SMD_CXO_D1_A_PIN]          = &msm8974_cxo_d1_a_pin,
 553         [RPM_SMD_CXO_A0_PIN]            = &msm8974_cxo_a0_pin,
 554         [RPM_SMD_CXO_A0_A_PIN]          = &msm8974_cxo_a0_a_pin,
 555         [RPM_SMD_CXO_A1_PIN]            = &msm8974_cxo_a1_pin,
 556         [RPM_SMD_CXO_A1_A_PIN]          = &msm8974_cxo_a1_a_pin,
 557         [RPM_SMD_CXO_A2_PIN]            = &msm8974_cxo_a2_pin,
 558         [RPM_SMD_CXO_A2_A_PIN]          = &msm8974_cxo_a2_a_pin,
 559 };
 560
 561 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 562         .clks = msm8974_clks,
 563         .num_clks = ARRAY_SIZE(msm8974_clks),
 564 };
 565
 566 DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
 567                    QCOM_SMD_RPM_BUS_CLK, 2);
 568 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 569
 570 static struct clk_smd_rpm *msm8976_clks[] = {
 571         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 572         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 573         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 574         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 575         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 576         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 577         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 578         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 579         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 580         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 581         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 582         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 583         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 584         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 585         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 586         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 587         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 588         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 589         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
 590         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
 591         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 592         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 593         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 594         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 595 };
 596
 597 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 598         .clks = msm8976_clks,
 599         .num_clks = ARRAY_SIZE(msm8976_clks),
 600 };
 601
 602 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000);
 603 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
 604
 605 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
 606 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 607
 608 DEFINE_CLK_SMD_RPM_BRANCH(msm8992, mss_cfg_ahb_clk, mss_cfg_ahb_a_clk,
 609                           QCOM_SMD_RPM_MCFG_CLK, 0, 19200000);
 610 static struct clk_smd_rpm *msm8992_clks[] = {
 611         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 612         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 613         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 614         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 615         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 616         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 617         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 618         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 619         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 620         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 621         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 622         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 623         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 624         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 625         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 626         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 627         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 628         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 629         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 630         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 631         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 632         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 633         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 634         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 635         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 636         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 637         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 638         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 639         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 640         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 641         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 642         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 643         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 644         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 645         [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
 646         [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
 647         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 648         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 649         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 650         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 651         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 652         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 653         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 654         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 655         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 656         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 657         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 658         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 659         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 660         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 661 };
 662
 663 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 664         .clks = msm8992_clks,
 665         .num_clks = ARRAY_SIZE(msm8992_clks),
 666 };
 667
 668 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
 669
 670 static struct clk_smd_rpm *msm8994_clks[] = {
 671         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 672         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 673         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 674         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 675         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 676         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 677         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 678         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 679         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 680         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 681         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 682         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 683         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 684         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 685         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 686         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 687         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 688         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 689         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 690         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 691         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 692         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 693         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 694         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 695         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 696         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 697         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 698         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 699         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 700         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 701         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 702         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 703         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 704         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 705         [RPM_SMD_MSS_CFG_AHB_CLK] = &msm8992_mss_cfg_ahb_clk,
 706         [RPM_SMD_MSS_CFG_AHB_A_CLK] = &msm8992_mss_cfg_ahb_a_clk,
 707         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 708         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 709         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 710         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 711         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 712         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 713         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 714         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 715         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 716         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 717         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 718         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 719         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 720         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 721         [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
 722         [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
 723 };
 724
 725 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
 726         .clks = msm8994_clks,
 727         .num_clks = ARRAY_SIZE(msm8994_clks),
 728 };
 729
 730 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
 731                    QCOM_SMD_RPM_MMAXI_CLK, 0);
 732 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
 733                           QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
 734 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
 735                           QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
 736
 737 static struct clk_smd_rpm *msm8996_clks[] = {
 738         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 739         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 740         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 741         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 742         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 743         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 744         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 745         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 746         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 747         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 748         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 749         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 750         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 751         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 752         [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
 753         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
 754         [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
 755         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
 756         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 757         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 758         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 759         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 760         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 761         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 762         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 763         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 764         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 765         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 766         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 767         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 768         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 769         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 770         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 771         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 772         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 773         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 774         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 775         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 776         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 777         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 778         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 779         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 780         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 781         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 782 };
 783
 784 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 785         .clks = msm8996_clks,
 786         .num_clks = ARRAY_SIZE(msm8996_clks),
 787 };
 788
 789 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 790 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
 791 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
 792
 793 static struct clk_smd_rpm *qcs404_clks[] = {
 794         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 795         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 796         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 797         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 798         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 799         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 800         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 801         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 802         [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
 803         [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
 804         [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
 805         [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
 806         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 807         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 808         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 809         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 810         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 811         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 812 };
 813
 814 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
 815         .clks = qcs404_clks,
 816         .num_clks = ARRAY_SIZE(qcs404_clks),
 817 };
 818
 819 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
 820 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin, 3, 19200000);
 821 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
 822                    QCOM_SMD_RPM_AGGR_CLK, 1);
 823 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
 824                    QCOM_SMD_RPM_AGGR_CLK, 2);
 825 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
 826 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
 827
 828 static struct clk_smd_rpm *msm8998_clks[] = {
 829         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 830         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 831         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 832         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 833         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 834         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 835         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 836         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 837         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 838         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 839         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 840         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 841         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 842         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 843         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 844         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 845         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 846         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 847         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 848         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 849         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
 850         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
 851         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 852         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 853         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
 854         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
 855         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 856         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 857         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 858         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 859         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 860         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 861         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 862         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 863         [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
 864         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
 865         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 866         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 867         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 868         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 869         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 870         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 871         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 872         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 873         [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
 874         [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
 875         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 876         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 877         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 878         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 879         [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
 880         [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
 881 };
 882
 883 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
 884         .clks = msm8998_clks,
 885         .num_clks = ARRAY_SIZE(msm8998_clks),
 886 };
 887
 888 static struct clk_smd_rpm *sdm660_clks[] = {
 889         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 890         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 891         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 892         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 893         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 894         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 895         [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
 896         [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
 897         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 898         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 899         [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 900         [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
 901         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 902         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 903         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 904         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 905         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 906         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 907         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 908         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 909         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 910         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 911         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 912         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 913         [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
 914         [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
 915         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 916         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 917         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
 918         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
 919         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 920         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 921         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 922         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 923         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 924         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 925         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 926         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 927 };
 928
 929 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 930         .clks = sdm660_clks,
 931         .num_clks = ARRAY_SIZE(sdm660_clks),
 932 };
 933
 934 static struct clk_smd_rpm *mdm9607_clks[] = {
 935         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 936         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 937         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 938         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 939         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 940         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 941         [RPM_SMD_QPIC_CLK]              = &qcs404_qpic_clk,
 942         [RPM_SMD_QPIC_CLK_A]            = &qcs404_qpic_a_clk,
 943         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 944         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 945         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 946         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 947         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 948         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 949 };
 950
 951 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
 952         .clks = mdm9607_clks,
 953         .num_clks = ARRAY_SIZE(mdm9607_clks),
 954 };
 955
 956 static struct clk_smd_rpm *msm8953_clks[] = {
 957         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 958         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 959         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 960         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 961         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 962         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 963         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 964         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 965         [RPM_SMD_IPA_CLK]               = &msm8976_ipa_clk,
 966         [RPM_SMD_IPA_A_CLK]             = &msm8976_ipa_a_clk,
 967         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 968         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 969         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 970         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 971         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 972         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 973         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 974         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 975         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 976         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 977         [RPM_SMD_RF_CLK3]               = &msm8992_ln_bb_clk,
 978         [RPM_SMD_RF_CLK3_A]             = &msm8992_ln_bb_a_clk,
 979         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 980         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 981         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 982         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 983         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 984         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 985 };
 986
 987 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
 988         .clks = msm8953_clks,
 989         .num_clks = ARRAY_SIZE(msm8953_clks),
 990 };
 991
 992 /* SM6125 */
 993 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 994 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 995 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk,
 996                                         QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
 997 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
 998 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
 999 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
1000 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk,
1001                                                 QCOM_SMD_RPM_BUS_CLK, 0);
1002 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk,
1003                                                 QCOM_SMD_RPM_BUS_CLK, 5);
1004
1005 static struct clk_smd_rpm *sm6125_clks[] = {
1006         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1007         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1008         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1009         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1010         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1011         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1012         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1013         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1014         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1015         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1016         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1017         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1018         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1019         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1020         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1021         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1022         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1023         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1024         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
1025         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
1026         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
1027         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1028         [RPM_SMD_LN_BB_CLK3] = &msm8998_ln_bb_clk3,
1029         [RPM_SMD_LN_BB_CLK3_A] = &msm8998_ln_bb_clk3_a,
1030         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1031         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1032         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1033         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1034         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1035         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1036         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1037         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1038         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1039         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1040 };
1041
1042 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
1043         .clks = sm6125_clks,
1044         .num_clks = ARRAY_SIZE(sm6125_clks),
1045 };
1046
1047 /* SM6115 */
1048 static struct clk_smd_rpm *sm6115_clks[] = {
1049         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1050         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1051         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1052         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1053         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1054         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1055         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1056         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1057         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1058         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1059         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1060         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1061         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1062         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1063         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1064         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1065         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1066         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1067         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1068         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1069         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1070         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1071         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1072         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1073         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1074         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1075         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1076         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1077         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
1078         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
1079         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
1080         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
1081 };
1082
1083 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
1084         .clks = sm6115_clks,
1085         .num_clks = ARRAY_SIZE(sm6115_clks),
1086 };
1087
1088 /* QCM2290 */
1089 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
1090 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
1091
1092 DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
1093 DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
1094 DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
1095 DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
1096                    QCOM_SMD_RPM_MEM_CLK, 1);
1097 DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
1098                    QCOM_SMD_RPM_MEM_CLK, 2);
1099
1100 static struct clk_smd_rpm *qcm2290_clks[] = {
1101         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1102         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1103         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1104         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1105         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1106         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1107         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1108         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1109         [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2,
1110         [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a,
1111         [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3,
1112         [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a,
1113         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1114         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1115         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1116         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1117         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1118         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1119         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1120         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1121         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1122         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1123         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1124         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1125         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1126         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1127         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1128         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1129         [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk,
1130         [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk,
1131         [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
1132         [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
1133         [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
1134         [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
1135         [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk,
1136         [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk,
1137         [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk,
1138         [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk,
1139 };
1140
1141 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
1142         .clks = qcm2290_clks,
1143         .num_clks = ARRAY_SIZE(qcm2290_clks),
1144 };
1145
1146 static const struct of_device_id rpm_smd_clk_match_table[] = {
1147         { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1148         { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1149         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1150         { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1151         { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1152         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1153         { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1154         { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1155         { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1156         { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1157         { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1158         { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1159         { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
1160         { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
1161         { .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
1162         { .compatible = "qcom,rpmcc-sm6125",  .data = &rpm_clk_sm6125  },
1163         { }
1164 };
1165 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
1166
1167 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
1168                                              void *data)
1169 {
1170         const struct rpm_smd_clk_desc *desc = data;
1171         unsigned int idx = clkspec->args[0];
1172
1173         if (idx >= desc->num_clks) {
1174                 pr_err("%s: invalid index %u\n", __func__, idx);
1175                 return ERR_PTR(-EINVAL);
1176         }
1177
1178         return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1179 }
1180
1181 static int rpm_smd_clk_probe(struct platform_device *pdev)
1182 {
1183         int ret;
1184         size_t num_clks, i;
1185         struct qcom_smd_rpm *rpm;
1186         struct clk_smd_rpm **rpm_smd_clks;
1187         const struct rpm_smd_clk_desc *desc;
1188
1189         rpm = dev_get_drvdata(pdev->dev.parent);
1190         if (!rpm) {
1191                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1192                 return -ENODEV;
1193         }
1194
1195         desc = of_device_get_match_data(&pdev->dev);
1196         if (!desc)
1197                 return -EINVAL;
1198
1199         rpm_smd_clks = desc->clks;
1200         num_clks = desc->num_clks;
1201
1202         for (i = 0; i < num_clks; i++) {
1203                 if (!rpm_smd_clks[i])
1204                         continue;
1205
1206                 rpm_smd_clks[i]->rpm = rpm;
1207
1208                 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1209                 if (ret)
1210                         goto err;
1211         }
1212
1213         ret = clk_smd_rpm_enable_scaling(rpm);
1214         if (ret)
1215                 goto err;
1216
1217         for (i = 0; i < num_clks; i++) {
1218                 if (!rpm_smd_clks[i])
1219                         continue;
1220
1221                 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1222                 if (ret)
1223                         goto err;
1224         }
1225
1226         ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1227                                           (void *)desc);
1228         if (ret)
1229                 goto err;
1230
1231         return 0;
1232 err:
1233         dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1234         return ret;
1235 }
1236
1237 static struct platform_driver rpm_smd_clk_driver = {
1238         .driver = {
1239                 .name = "qcom-clk-smd-rpm",
1240                 .of_match_table = rpm_smd_clk_match_table,
1241         },
1242         .probe = rpm_smd_clk_probe,
1243 };
1244
1245 static int __init rpm_smd_clk_init(void)
1246 {
1247         return platform_driver_register(&rpm_smd_clk_driver);
1248 }
1249 core_initcall(rpm_smd_clk_init);
1250
1251 static void __exit rpm_smd_clk_exit(void)
1252 {
1253         platform_driver_unregister(&rpm_smd_clk_driver);
1254 }
1255 module_exit(rpm_smd_clk_exit);
1256
1257 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1258 MODULE_LICENSE("GPL v2");
1259 MODULE_ALIAS("platform:qcom-clk-smd-rpm");