drivers/clk/qcom/clk-smd-rpm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, Linaro Limited
   4  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/soc/qcom/smd-rpm.h>
  18
  19 #include <dt-bindings/clock/qcom,rpmcc.h>
  20
  21 #define QCOM_RPM_KEY_SOFTWARE_ENABLE                    0x6e657773
  22 #define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY     0x62636370
  23 #define QCOM_RPM_SMD_KEY_RATE                           0x007a484b
  24 #define QCOM_RPM_SMD_KEY_ENABLE                         0x62616e45
  25 #define QCOM_RPM_SMD_KEY_STATE                          0x54415453
  26 #define QCOM_RPM_SCALING_ENABLE_ID                      0x2
  27
  28 #define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id,  \
  29                              key)                                             \
  30         static struct clk_smd_rpm _platform##_##_active;                      \
  31         static struct clk_smd_rpm _platform##_##_name = {                     \
  32                 .rpm_res_type = (type),                                       \
  33                 .rpm_clk_id = (r_id),                                         \
  34                 .rpm_status_id = (stat_id),                                   \
  35                 .rpm_key = (key),                                             \
  36                 .peer = &_platform##_##_active,                               \
  37                 .rate = INT_MAX,                                              \
  38                 .hw.init = &(struct clk_init_data){                           \
  39                         .ops = &clk_smd_rpm_ops,                              \
  40                         .name = #_name,                                       \
  41                         .parent_data =  &(const struct clk_parent_data){ \
  42                                         .fw_name = "xo",                \
  43                                         .name = "xo_board",             \
  44                         },                                              \
  45                         .num_parents = 1,                                     \
  46                 },                                                            \
  47         };                                                                    \
  48         static struct clk_smd_rpm _platform##_##_active = {                   \
  49                 .rpm_res_type = (type),                                       \
  50                 .rpm_clk_id = (r_id),                                         \
  51                 .rpm_status_id = (stat_id),                                   \
  52                 .active_only = true,                                          \
  53                 .rpm_key = (key),                                             \
  54                 .peer = &_platform##_##_name,                                 \
  55                 .rate = INT_MAX,                                              \
  56                 .hw.init = &(struct clk_init_data){                           \
  57                         .ops = &clk_smd_rpm_ops,                              \
  58                         .name = #_active,                                     \
  59                         .parent_data =  &(const struct clk_parent_data){ \
  60                                         .fw_name = "xo",                \
  61                                         .name = "xo_board",             \
  62                         },                                              \
  63                         .num_parents = 1,                                     \
  64                 },                                                            \
  65         }
  66
  67 #define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id,    \
  68                                     stat_id, r, key)                          \
  69         static struct clk_smd_rpm _platform##_##_active;                      \
  70         static struct clk_smd_rpm _platform##_##_name = {                     \
  71                 .rpm_res_type = (type),                                       \
  72                 .rpm_clk_id = (r_id),                                         \
  73                 .rpm_status_id = (stat_id),                                   \
  74                 .rpm_key = (key),                                             \
  75                 .branch = true,                                               \
  76                 .peer = &_platform##_##_active,                               \
  77                 .rate = (r),                                                  \
  78                 .hw.init = &(struct clk_init_data){                           \
  79                         .ops = &clk_smd_rpm_branch_ops,                       \
  80                         .name = #_name,                                       \
  81                         .parent_data =  &(const struct clk_parent_data){ \
  82                                         .fw_name = "xo",                \
  83                                         .name = "xo_board",             \
  84                         },                                              \
  85                         .num_parents = 1,                                     \
  86                 },                                                            \
  87         };                                                                    \
  88         static struct clk_smd_rpm _platform##_##_active = {                   \
  89                 .rpm_res_type = (type),                                       \
  90                 .rpm_clk_id = (r_id),                                         \
  91                 .rpm_status_id = (stat_id),                                   \
  92                 .active_only = true,                                          \
  93                 .rpm_key = (key),                                             \
  94                 .branch = true,                                               \
  95                 .peer = &_platform##_##_name,                                 \
  96                 .rate = (r),                                                  \
  97                 .hw.init = &(struct clk_init_data){                           \
  98                         .ops = &clk_smd_rpm_branch_ops,                       \
  99                         .name = #_active,                                     \
 100                         .parent_data =  &(const struct clk_parent_data){ \
 101                                         .fw_name = "xo",                \
 102                                         .name = "xo_board",             \
 103                         },                                              \
 104                         .num_parents = 1,                                     \
 105                 },                                                            \
 106         }
 107
 108 #define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id)             \
 109                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 110                 0, QCOM_RPM_SMD_KEY_RATE)
 111
 112 #define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r)   \
 113                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type,  \
 114                 r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
 115
 116 #define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id)        \
 117                 __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id,   \
 118                 0, QCOM_RPM_SMD_KEY_STATE)
 119
 120 #define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id, r)      \
 121                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 122                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 123                 QCOM_RPM_KEY_SOFTWARE_ENABLE)
 124
 125 #define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active,       \
 126                                              r_id, r)                         \
 127                 __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active,        \
 128                 QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, r,                           \
 129                 QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
 130
 131 #define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
 132
 133 struct clk_smd_rpm {
 134         const int rpm_res_type;
 135         const int rpm_key;
 136         const int rpm_clk_id;
 137         const int rpm_status_id;
 138         const bool active_only;
 139         bool enabled;
 140         bool branch;
 141         struct clk_smd_rpm *peer;
 142         struct clk_hw hw;
 143         unsigned long rate;
 144         struct qcom_smd_rpm *rpm;
 145 };
 146
 147 struct clk_smd_rpm_req {
 148         __le32 key;
 149         __le32 nbytes;
 150         __le32 value;
 151 };
 152
 153 struct rpm_smd_clk_desc {
 154         struct clk_smd_rpm **clks;
 155         size_t num_clks;
 156 };
 157
 158 static DEFINE_MUTEX(rpm_smd_clk_lock);
 159
 160 static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
 161 {
 162         int ret;
 163         struct clk_smd_rpm_req req = {
 164                 .key = cpu_to_le32(r->rpm_key),
 165                 .nbytes = cpu_to_le32(sizeof(u32)),
 166                 .value = cpu_to_le32(r->branch ? 1 : INT_MAX),
 167         };
 168
 169         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 170                                  r->rpm_res_type, r->rpm_clk_id, &req,
 171                                  sizeof(req));
 172         if (ret)
 173                 return ret;
 174         ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 175                                  r->rpm_res_type, r->rpm_clk_id, &req,
 176                                  sizeof(req));
 177         if (ret)
 178                 return ret;
 179
 180         return 0;
 181 }
 182
 183 static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
 184                                        unsigned long rate)
 185 {
 186         struct clk_smd_rpm_req req = {
 187                 .key = cpu_to_le32(r->rpm_key),
 188                 .nbytes = cpu_to_le32(sizeof(u32)),
 189                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 190         };
 191
 192         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 193                                   r->rpm_res_type, r->rpm_clk_id, &req,
 194                                   sizeof(req));
 195 }
 196
 197 static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
 198                                       unsigned long rate)
 199 {
 200         struct clk_smd_rpm_req req = {
 201                 .key = cpu_to_le32(r->rpm_key),
 202                 .nbytes = cpu_to_le32(sizeof(u32)),
 203                 .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
 204         };
 205
 206         return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
 207                                   r->rpm_res_type, r->rpm_clk_id, &req,
 208                                   sizeof(req));
 209 }
 210
 211 static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
 212                             unsigned long *active, unsigned long *sleep)
 213 {
 214         *active = rate;
 215
 216         /*
 217          * Active-only clocks don't care what the rate is during sleep. So,
 218          * they vote for zero.
 219          */
 220         if (r->active_only)
 221                 *sleep = 0;
 222         else
 223                 *sleep = *active;
 224 }
 225
 226 static int clk_smd_rpm_prepare(struct clk_hw *hw)
 227 {
 228         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 229         struct clk_smd_rpm *peer = r->peer;
 230         unsigned long this_rate = 0, this_sleep_rate = 0;
 231         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 232         unsigned long active_rate, sleep_rate;
 233         int ret = 0;
 234
 235         mutex_lock(&rpm_smd_clk_lock);
 236
 237         /* Don't send requests to the RPM if the rate has not been set. */
 238         if (!r->rate)
 239                 goto out;
 240
 241         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
 242
 243         /* Take peer clock's rate into account only if it's enabled. */
 244         if (peer->enabled)
 245                 to_active_sleep(peer, peer->rate,
 246                                 &peer_rate, &peer_sleep_rate);
 247
 248         active_rate = max(this_rate, peer_rate);
 249
 250         if (r->branch)
 251                 active_rate = !!active_rate;
 252
 253         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 254         if (ret)
 255                 goto out;
 256
 257         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 258         if (r->branch)
 259                 sleep_rate = !!sleep_rate;
 260
 261         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 262         if (ret)
 263                 /* Undo the active set vote and restore it */
 264                 ret = clk_smd_rpm_set_rate_active(r, peer_rate);
 265
 266 out:
 267         if (!ret)
 268                 r->enabled = true;
 269
 270         mutex_unlock(&rpm_smd_clk_lock);
 271
 272         return ret;
 273 }
 274
 275 static void clk_smd_rpm_unprepare(struct clk_hw *hw)
 276 {
 277         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 278         struct clk_smd_rpm *peer = r->peer;
 279         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 280         unsigned long active_rate, sleep_rate;
 281         int ret;
 282
 283         mutex_lock(&rpm_smd_clk_lock);
 284
 285         if (!r->rate)
 286                 goto out;
 287
 288         /* Take peer clock's rate into account only if it's enabled. */
 289         if (peer->enabled)
 290                 to_active_sleep(peer, peer->rate, &peer_rate,
 291                                 &peer_sleep_rate);
 292
 293         active_rate = r->branch ? !!peer_rate : peer_rate;
 294         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 295         if (ret)
 296                 goto out;
 297
 298         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 299         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 300         if (ret)
 301                 goto out;
 302
 303         r->enabled = false;
 304
 305 out:
 306         mutex_unlock(&rpm_smd_clk_lock);
 307 }
 308
 309 static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
 310                                 unsigned long parent_rate)
 311 {
 312         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 313         struct clk_smd_rpm *peer = r->peer;
 314         unsigned long active_rate, sleep_rate;
 315         unsigned long this_rate = 0, this_sleep_rate = 0;
 316         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 317         int ret = 0;
 318
 319         mutex_lock(&rpm_smd_clk_lock);
 320
 321         if (!r->enabled)
 322                 goto out;
 323
 324         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 325
 326         /* Take peer clock's rate into account only if it's enabled. */
 327         if (peer->enabled)
 328                 to_active_sleep(peer, peer->rate,
 329                                 &peer_rate, &peer_sleep_rate);
 330
 331         active_rate = max(this_rate, peer_rate);
 332         ret = clk_smd_rpm_set_rate_active(r, active_rate);
 333         if (ret)
 334                 goto out;
 335
 336         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 337         ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
 338         if (ret)
 339                 goto out;
 340
 341         r->rate = rate;
 342
 343 out:
 344         mutex_unlock(&rpm_smd_clk_lock);
 345
 346         return ret;
 347 }
 348
 349 static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 350                                    unsigned long *parent_rate)
 351 {
 352         /*
 353          * RPM handles rate rounding and we don't have a way to
 354          * know what the rate will be, so just return whatever
 355          * rate is requested.
 356          */
 357         return rate;
 358 }
 359
 360 static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
 361                                              unsigned long parent_rate)
 362 {
 363         struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
 364
 365         /*
 366          * RPM handles rate rounding and we don't have a way to
 367          * know what the rate will be, so just return whatever
 368          * rate was set.
 369          */
 370         return r->rate;
 371 }
 372
 373 static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
 374 {
 375         int ret;
 376         struct clk_smd_rpm_req req = {
 377                 .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
 378                 .nbytes = cpu_to_le32(sizeof(u32)),
 379                 .value = cpu_to_le32(1),
 380         };
 381
 382         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
 383                                  QCOM_SMD_RPM_MISC_CLK,
 384                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 385         if (ret) {
 386                 pr_err("RPM clock scaling (sleep set) not enabled!\n");
 387                 return ret;
 388         }
 389
 390         ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
 391                                  QCOM_SMD_RPM_MISC_CLK,
 392                                  QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
 393         if (ret) {
 394                 pr_err("RPM clock scaling (active set) not enabled!\n");
 395                 return ret;
 396         }
 397
 398         pr_debug("%s: RPM clock scaling is enabled\n", __func__);
 399         return 0;
 400 }
 401
 402 static const struct clk_ops clk_smd_rpm_ops = {
 403         .prepare        = clk_smd_rpm_prepare,
 404         .unprepare      = clk_smd_rpm_unprepare,
 405         .set_rate       = clk_smd_rpm_set_rate,
 406         .round_rate     = clk_smd_rpm_round_rate,
 407         .recalc_rate    = clk_smd_rpm_recalc_rate,
 408 };
 409
 410 static const struct clk_ops clk_smd_rpm_branch_ops = {
 411         .prepare        = clk_smd_rpm_prepare,
 412         .unprepare      = clk_smd_rpm_unprepare,
 413         .recalc_rate    = clk_smd_rpm_recalc_rate,
 414 };
 415
 416 DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
 417 DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 418 DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
 419 DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
 420 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1, 19200000);
 421 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2, 19200000);
 422 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4, 19200000);
 423 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5, 19200000);
 424 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1, 19200000);
 425 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2, 19200000);
 426 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4, 19200000);
 427 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5, 19200000);
 428
 429 static struct clk_smd_rpm *msm8916_clks[] = {
 430         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 431         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 432         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 433         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 434         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 435         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 436         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 437         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 438         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 439         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 440         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 441         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 442         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 443         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 444         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 445         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 446         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 447         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 448         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 449         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 450         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 451         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 452         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 453         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 454 };
 455
 456 static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 457         .clks = msm8916_clks,
 458         .num_clks = ARRAY_SIZE(msm8916_clks),
 459 };
 460
 461 DEFINE_CLK_SMD_RPM(msm8936, sysmmnoc_clk, sysmmnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 462
 463 static struct clk_smd_rpm *msm8936_clks[] = {
 464         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 465         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 466         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 467         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 468         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 469         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 470         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 471         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 472         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 473         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 474         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 475         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 476         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 477         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 478         [RPM_SMD_RF_CLK1]               = &msm8916_rf_clk1,
 479         [RPM_SMD_RF_CLK1_A]             = &msm8916_rf_clk1_a,
 480         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 481         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 482         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 483         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 484         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 485         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 486         [RPM_SMD_RF_CLK1_PIN]           = &msm8916_rf_clk1_pin,
 487         [RPM_SMD_RF_CLK1_A_PIN]         = &msm8916_rf_clk1_a_pin,
 488         [RPM_SMD_RF_CLK2_PIN]           = &msm8916_rf_clk2_pin,
 489         [RPM_SMD_RF_CLK2_A_PIN]         = &msm8916_rf_clk2_a_pin,
 490 };
 491
 492 static const struct rpm_smd_clk_desc rpm_clk_msm8936 = {
 493                 .clks = msm8936_clks,
 494                 .num_clks = ARRAY_SIZE(msm8936_clks),
 495 };
 496
 497 DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 498 DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
 499 DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
 500 DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 501 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1, 19200000);
 502 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2, 19200000);
 503 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4, 19200000);
 504 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5, 19200000);
 505 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6, 19200000);
 506 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7, 19200000);
 507 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11, 19200000);
 508 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12, 19200000);
 509 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1, 19200000);
 510 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2, 19200000);
 511 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4, 19200000);
 512 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5, 19200000);
 513 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6, 19200000);
 514
 515 static struct clk_smd_rpm *msm8974_clks[] = {
 516         [RPM_SMD_PNOC_CLK]              = &msm8916_pcnoc_clk,
 517         [RPM_SMD_PNOC_A_CLK]            = &msm8916_pcnoc_a_clk,
 518         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 519         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 520         [RPM_SMD_CNOC_CLK]              = &msm8974_cnoc_clk,
 521         [RPM_SMD_CNOC_A_CLK]            = &msm8974_cnoc_a_clk,
 522         [RPM_SMD_MMSSNOC_AHB_CLK]       = &msm8974_mmssnoc_ahb_clk,
 523         [RPM_SMD_MMSSNOC_AHB_A_CLK]     = &msm8974_mmssnoc_ahb_a_clk,
 524         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 525         [RPM_SMD_GFX3D_CLK_SRC]         = &msm8974_gfx3d_clk_src,
 526         [RPM_SMD_GFX3D_A_CLK_SRC]       = &msm8974_gfx3d_a_clk_src,
 527         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 528         [RPM_SMD_OCMEMGX_CLK]           = &msm8974_ocmemgx_clk,
 529         [RPM_SMD_OCMEMGX_A_CLK]         = &msm8974_ocmemgx_a_clk,
 530         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 531         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 532         [RPM_SMD_CXO_D0]                = &msm8974_cxo_d0,
 533         [RPM_SMD_CXO_D0_A]              = &msm8974_cxo_d0_a,
 534         [RPM_SMD_CXO_D1]                = &msm8974_cxo_d1,
 535         [RPM_SMD_CXO_D1_A]              = &msm8974_cxo_d1_a,
 536         [RPM_SMD_CXO_A0]                = &msm8974_cxo_a0,
 537         [RPM_SMD_CXO_A0_A]              = &msm8974_cxo_a0_a,
 538         [RPM_SMD_CXO_A1]                = &msm8974_cxo_a1,
 539         [RPM_SMD_CXO_A1_A]              = &msm8974_cxo_a1_a,
 540         [RPM_SMD_CXO_A2]                = &msm8974_cxo_a2,
 541         [RPM_SMD_CXO_A2_A]              = &msm8974_cxo_a2_a,
 542         [RPM_SMD_DIFF_CLK]              = &msm8974_diff_clk,
 543         [RPM_SMD_DIFF_A_CLK]            = &msm8974_diff_a_clk,
 544         [RPM_SMD_DIV_CLK1]              = &msm8974_div_clk1,
 545         [RPM_SMD_DIV_A_CLK1]            = &msm8974_div_a_clk1,
 546         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 547         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 548         [RPM_SMD_CXO_D0_PIN]            = &msm8974_cxo_d0_pin,
 549         [RPM_SMD_CXO_D0_A_PIN]          = &msm8974_cxo_d0_a_pin,
 550         [RPM_SMD_CXO_D1_PIN]            = &msm8974_cxo_d1_pin,
 551         [RPM_SMD_CXO_D1_A_PIN]          = &msm8974_cxo_d1_a_pin,
 552         [RPM_SMD_CXO_A0_PIN]            = &msm8974_cxo_a0_pin,
 553         [RPM_SMD_CXO_A0_A_PIN]          = &msm8974_cxo_a0_a_pin,
 554         [RPM_SMD_CXO_A1_PIN]            = &msm8974_cxo_a1_pin,
 555         [RPM_SMD_CXO_A1_A_PIN]          = &msm8974_cxo_a1_a_pin,
 556         [RPM_SMD_CXO_A2_PIN]            = &msm8974_cxo_a2_pin,
 557         [RPM_SMD_CXO_A2_A_PIN]          = &msm8974_cxo_a2_a_pin,
 558 };
 559
 560 static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
 561         .clks = msm8974_clks,
 562         .num_clks = ARRAY_SIZE(msm8974_clks),
 563 };
 564
 565 DEFINE_CLK_SMD_RPM(msm8976, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
 566                    QCOM_SMD_RPM_BUS_CLK, 2);
 567 DEFINE_CLK_SMD_RPM(msm8976, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
 568
 569 static struct clk_smd_rpm *msm8976_clks[] = {
 570         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 571         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 572         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 573         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 574         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 575         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 576         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 577         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 578         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 579         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 580         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 581         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 582         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 583         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 584         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 585         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 586         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 587         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 588         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8976_mmssnoc_ahb_clk,
 589         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8976_mmssnoc_ahb_a_clk,
 590         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 591         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 592         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 593         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 594 };
 595
 596 static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
 597         .clks = msm8976_clks,
 598         .num_clks = ARRAY_SIZE(msm8976_clks),
 599 };
 600
 601 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13, 19200000);
 602 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8, 19200000);
 603
 604 DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
 605 DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
 606
 607 static struct clk_smd_rpm *msm8992_clks[] = {
 608         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 609         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 610         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 611         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 612         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 613         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 614         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 615         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 616         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 617         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 618         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 619         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 620         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 621         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 622         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 623         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 624         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 625         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 626         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 627         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 628         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 629         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 630         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 631         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 632         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 633         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 634         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 635         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 636         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 637         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 638         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 639         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 640         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 641         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 642         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 643         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 644         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 645         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 646         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 647         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 648         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 649         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 650         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 651         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 652         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 653         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 654 };
 655
 656 static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
 657         .clks = msm8992_clks,
 658         .num_clks = ARRAY_SIZE(msm8992_clks),
 659 };
 660
 661 DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
 662
 663 static struct clk_smd_rpm *msm8994_clks[] = {
 664         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 665         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 666         [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
 667         [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
 668         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 669         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 670         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 671         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 672         [RPM_SMD_GFX3D_CLK_SRC] = &msm8974_gfx3d_clk_src,
 673         [RPM_SMD_GFX3D_A_CLK_SRC] = &msm8974_gfx3d_a_clk_src,
 674         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 675         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 676         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 677         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 678         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 679         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 680         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 681         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 682         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 683         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 684         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 685         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 686         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 687         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 688         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 689         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 690         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 691         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 692         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 693         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 694         [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
 695         [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
 696         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 697         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 698         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 699         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 700         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 701         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 702         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 703         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 704         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 705         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 706         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 707         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 708         [RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
 709         [RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
 710         [RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
 711         [RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
 712 };
 713
 714 static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
 715         .clks = msm8994_clks,
 716         .num_clks = ARRAY_SIZE(msm8994_clks),
 717 };
 718
 719 DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
 720                    QCOM_SMD_RPM_MMAXI_CLK, 0);
 721 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
 722                           QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
 723 DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
 724                           QCOM_SMD_RPM_AGGR_CLK, 2, 1000);
 725
 726 static struct clk_smd_rpm *msm8996_clks[] = {
 727         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 728         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 729         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 730         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 731         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 732         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 733         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 734         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 735         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 736         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 737         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 738         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 739         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 740         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 741         [RPM_SMD_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
 742         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
 743         [RPM_SMD_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
 744         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
 745         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 746         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 747         [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
 748         [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
 749         [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
 750         [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
 751         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 752         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 753         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 754         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 755         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 756         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 757         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 758         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 759         [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
 760         [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
 761         [RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
 762         [RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
 763         [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 764         [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 765         [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 766         [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 767         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 768         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 769         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 770         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 771 };
 772
 773 static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
 774         .clks = msm8996_clks,
 775         .num_clks = ARRAY_SIZE(msm8996_clks),
 776 };
 777
 778 DEFINE_CLK_SMD_RPM(qcs404, bimc_gpu_clk, bimc_gpu_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
 779 DEFINE_CLK_SMD_RPM(qcs404, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
 780 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(qcs404, ln_bb_clk_pin, ln_bb_clk_a_pin, 8, 19200000);
 781
 782 static struct clk_smd_rpm *qcs404_clks[] = {
 783         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 784         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 785         [RPM_SMD_PNOC_CLK] = &msm8916_pcnoc_clk,
 786         [RPM_SMD_PNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 787         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 788         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 789         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 790         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 791         [RPM_SMD_BIMC_GPU_CLK] = &qcs404_bimc_gpu_clk,
 792         [RPM_SMD_BIMC_GPU_A_CLK] = &qcs404_bimc_gpu_a_clk,
 793         [RPM_SMD_QPIC_CLK] = &qcs404_qpic_clk,
 794         [RPM_SMD_QPIC_CLK_A] = &qcs404_qpic_a_clk,
 795         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 796         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 797         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 798         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 799         [RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
 800         [RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
 801 };
 802
 803 static const struct rpm_smd_clk_desc rpm_clk_qcs404 = {
 804         .clks = qcs404_clks,
 805         .num_clks = ARRAY_SIZE(qcs404_clks),
 806 };
 807
 808 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, ln_bb_clk3_pin, ln_bb_clk3_a_pin,
 809                                      3, 19200000);
 810 DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
 811                    QCOM_SMD_RPM_AGGR_CLK, 1);
 812 DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
 813                    QCOM_SMD_RPM_AGGR_CLK, 2);
 814 DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6, 19200000);
 815 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6, 19200000);
 816 static struct clk_smd_rpm *msm8998_clks[] = {
 817         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 818         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 819         [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
 820         [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
 821         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 822         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 823         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 824         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 825         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 826         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 827         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 828         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 829         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 830         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 831         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
 832         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
 833         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 834         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 835         [RPM_SMD_LN_BB_CLK3_PIN] = &msm8998_ln_bb_clk3_pin,
 836         [RPM_SMD_LN_BB_CLK3_A_PIN] = &msm8998_ln_bb_clk3_a_pin,
 837         [RPM_SMD_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 838         [RPM_SMD_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
 839         [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
 840         [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
 841         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 842         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 843         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 844         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 845         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 846         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 847         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
 848         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
 849         [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
 850         [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
 851         [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
 852         [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
 853 };
 854
 855 static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
 856         .clks = msm8998_clks,
 857         .num_clks = ARRAY_SIZE(msm8998_clks),
 858 };
 859
 860 DEFINE_CLK_SMD_RPM_BRANCH(sdm660, bi_tcxo, bi_tcxo_a, QCOM_SMD_RPM_MISC_CLK, 0,
 861                                                                 19200000);
 862 DEFINE_CLK_SMD_RPM_XO_BUFFER(sdm660, ln_bb_clk3, ln_bb_clk3_a, 3, 19200000);
 863 DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(sdm660, ln_bb_clk3_pin, ln_bb_clk3_pin_a, 3, 19200000);
 864
 865 static struct clk_smd_rpm *sdm660_clks[] = {
 866         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 867         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 868         [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
 869         [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
 870         [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
 871         [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
 872         [RPM_SMD_CNOC_PERIPH_CLK] = &msm8916_pcnoc_clk,
 873         [RPM_SMD_CNOC_PERIPH_A_CLK] = &msm8916_pcnoc_a_clk,
 874         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 875         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 876         [RPM_SMD_MMSSNOC_AXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
 877         [RPM_SMD_MMSSNOC_AXI_CLK_A] = &msm8996_mmssnoc_axi_rpm_a_clk,
 878         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 879         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 880         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
 881         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
 882         [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
 883         [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
 884         [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
 885         [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
 886         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 887         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 888         [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
 889         [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
 890         [RPM_SMD_LN_BB_CLK] = &msm8916_bb_clk1,
 891         [RPM_SMD_LN_BB_A_CLK] = &msm8916_bb_clk1_a,
 892         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
 893         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
 894         [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
 895         [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
 896         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
 897         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
 898         [RPM_SMD_LN_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
 899         [RPM_SMD_LN_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
 900         [RPM_SMD_LN_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
 901         [RPM_SMD_LN_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
 902         [RPM_SMD_LN_BB_CLK3_PIN] = &sdm660_ln_bb_clk3_pin,
 903         [RPM_SMD_LN_BB_CLK3_A_PIN] = &sdm660_ln_bb_clk3_pin_a,
 904 };
 905
 906 static const struct rpm_smd_clk_desc rpm_clk_sdm660 = {
 907         .clks = sdm660_clks,
 908         .num_clks = ARRAY_SIZE(sdm660_clks),
 909 };
 910
 911 static struct clk_smd_rpm *mdm9607_clks[] = {
 912         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 913         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 914         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 915         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 916         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 917         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 918         [RPM_SMD_QPIC_CLK]              = &qcs404_qpic_clk,
 919         [RPM_SMD_QPIC_CLK_A]            = &qcs404_qpic_a_clk,
 920         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 921         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 922         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 923         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 924         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 925         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 926 };
 927
 928 static const struct rpm_smd_clk_desc rpm_clk_mdm9607 = {
 929         .clks = mdm9607_clks,
 930         .num_clks = ARRAY_SIZE(mdm9607_clks),
 931 };
 932
 933 static struct clk_smd_rpm *msm8953_clks[] = {
 934         [RPM_SMD_XO_CLK_SRC]            = &sdm660_bi_tcxo,
 935         [RPM_SMD_XO_A_CLK_SRC]          = &sdm660_bi_tcxo_a,
 936         [RPM_SMD_PCNOC_CLK]             = &msm8916_pcnoc_clk,
 937         [RPM_SMD_PCNOC_A_CLK]           = &msm8916_pcnoc_a_clk,
 938         [RPM_SMD_SNOC_CLK]              = &msm8916_snoc_clk,
 939         [RPM_SMD_SNOC_A_CLK]            = &msm8916_snoc_a_clk,
 940         [RPM_SMD_BIMC_CLK]              = &msm8916_bimc_clk,
 941         [RPM_SMD_BIMC_A_CLK]            = &msm8916_bimc_a_clk,
 942         [RPM_SMD_IPA_CLK]               = &msm8976_ipa_clk,
 943         [RPM_SMD_IPA_A_CLK]             = &msm8976_ipa_a_clk,
 944         [RPM_SMD_SYSMMNOC_CLK]          = &msm8936_sysmmnoc_clk,
 945         [RPM_SMD_SYSMMNOC_A_CLK]        = &msm8936_sysmmnoc_a_clk,
 946         [RPM_SMD_QDSS_CLK]              = &msm8916_qdss_clk,
 947         [RPM_SMD_QDSS_A_CLK]            = &msm8916_qdss_a_clk,
 948         [RPM_SMD_BB_CLK1]               = &msm8916_bb_clk1,
 949         [RPM_SMD_BB_CLK1_A]             = &msm8916_bb_clk1_a,
 950         [RPM_SMD_BB_CLK2]               = &msm8916_bb_clk2,
 951         [RPM_SMD_BB_CLK2_A]             = &msm8916_bb_clk2_a,
 952         [RPM_SMD_RF_CLK2]               = &msm8916_rf_clk2,
 953         [RPM_SMD_RF_CLK2_A]             = &msm8916_rf_clk2_a,
 954         [RPM_SMD_RF_CLK3]               = &msm8992_ln_bb_clk,
 955         [RPM_SMD_RF_CLK3_A]             = &msm8992_ln_bb_a_clk,
 956         [RPM_SMD_DIV_CLK2]              = &msm8974_div_clk2,
 957         [RPM_SMD_DIV_A_CLK2]            = &msm8974_div_a_clk2,
 958         [RPM_SMD_BB_CLK1_PIN]           = &msm8916_bb_clk1_pin,
 959         [RPM_SMD_BB_CLK1_A_PIN]         = &msm8916_bb_clk1_a_pin,
 960         [RPM_SMD_BB_CLK2_PIN]           = &msm8916_bb_clk2_pin,
 961         [RPM_SMD_BB_CLK2_A_PIN]         = &msm8916_bb_clk2_a_pin,
 962 };
 963
 964 static const struct rpm_smd_clk_desc rpm_clk_msm8953 = {
 965         .clks = msm8953_clks,
 966         .num_clks = ARRAY_SIZE(msm8953_clks),
 967 };
 968
 969 /* SM6125 */
 970 DEFINE_CLK_SMD_RPM(sm6125, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
 971 DEFINE_CLK_SMD_RPM(sm6125, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
 972 DEFINE_CLK_SMD_RPM_BRANCH(sm6125, qdss_clk, qdss_a_clk,
 973                                         QCOM_SMD_RPM_MISC_CLK, 1, 19200000);
 974 DEFINE_CLK_SMD_RPM(sm6125, qup_clk, qup_a_clk, QCOM_SMD_RPM_QUP_CLK, 0);
 975 DEFINE_CLK_SMD_RPM(sm6125, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 0);
 976 DEFINE_CLK_SMD_RPM(sm6125, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMAXI_CLK, 1);
 977 DEFINE_CLK_SMD_RPM(sm6125, snoc_periph_clk, snoc_periph_a_clk,
 978                                                 QCOM_SMD_RPM_BUS_CLK, 0);
 979 DEFINE_CLK_SMD_RPM(sm6125, snoc_lpass_clk, snoc_lpass_a_clk,
 980                                                 QCOM_SMD_RPM_BUS_CLK, 5);
 981
 982 static struct clk_smd_rpm *sm6125_clks[] = {
 983         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
 984         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
 985         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
 986         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
 987         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
 988         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
 989         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
 990         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
 991         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
 992         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
 993         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
 994         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
 995         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
 996         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
 997         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
 998         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
 999         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1000         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1001         [RPM_SMD_LN_BB_CLK1] = &msm8916_bb_clk1,
1002         [RPM_SMD_LN_BB_CLK1_A] = &msm8916_bb_clk1_a,
1003         [RPM_SMD_LN_BB_CLK2] = &msm8916_bb_clk2,
1004         [RPM_SMD_LN_BB_CLK2_A] = &msm8916_bb_clk2_a,
1005         [RPM_SMD_LN_BB_CLK3] = &sdm660_ln_bb_clk3,
1006         [RPM_SMD_LN_BB_CLK3_A] = &sdm660_ln_bb_clk3_a,
1007         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1008         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1009         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1010         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1011         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1012         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1013         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1014         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1015         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1016         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1017 };
1018
1019 static const struct rpm_smd_clk_desc rpm_clk_sm6125 = {
1020         .clks = sm6125_clks,
1021         .num_clks = ARRAY_SIZE(sm6125_clks),
1022 };
1023
1024 /* SM6115 */
1025 static struct clk_smd_rpm *sm6115_clks[] = {
1026         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1027         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1028         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1029         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1030         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1031         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1032         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1033         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1034         [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
1035         [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
1036         [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
1037         [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
1038         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1039         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1040         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1041         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1042         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1043         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1044         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1045         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1046         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1047         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1048         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1049         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1050         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1051         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1052         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1053         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1054         [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
1055         [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
1056         [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
1057         [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
1058 };
1059
1060 static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
1061         .clks = sm6115_clks,
1062         .num_clks = ARRAY_SIZE(sm6115_clks),
1063 };
1064
1065 /* QCM2290 */
1066 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
1067 DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
1068
1069 DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
1070 DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
1071 DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
1072 DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
1073                    QCOM_SMD_RPM_MEM_CLK, 1);
1074 DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
1075                    QCOM_SMD_RPM_MEM_CLK, 2);
1076
1077 static struct clk_smd_rpm *qcm2290_clks[] = {
1078         [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
1079         [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
1080         [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
1081         [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
1082         [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
1083         [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
1084         [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
1085         [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
1086         [RPM_SMD_LN_BB_CLK2] = &qcm2290_ln_bb_clk2,
1087         [RPM_SMD_LN_BB_CLK2_A] = &qcm2290_ln_bb_clk2_a,
1088         [RPM_SMD_RF_CLK3] = &qcm2290_rf_clk3,
1089         [RPM_SMD_RF_CLK3_A] = &qcm2290_rf_clk3_a,
1090         [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
1091         [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
1092         [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
1093         [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
1094         [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
1095         [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
1096         [RPM_SMD_MMRT_CLK] = &sm6125_mmrt_clk,
1097         [RPM_SMD_MMRT_A_CLK] = &sm6125_mmrt_a_clk,
1098         [RPM_SMD_MMNRT_CLK] = &sm6125_mmnrt_clk,
1099         [RPM_SMD_MMNRT_A_CLK] = &sm6125_mmnrt_a_clk,
1100         [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
1101         [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
1102         [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
1103         [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
1104         [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
1105         [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
1106         [RPM_SMD_QPIC_CLK] = &qcm2290_qpic_clk,
1107         [RPM_SMD_QPIC_CLK_A] = &qcm2290_qpic_a_clk,
1108         [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
1109         [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
1110         [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
1111         [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
1112         [RPM_SMD_BIMC_GPU_CLK] = &qcm2290_bimc_gpu_clk,
1113         [RPM_SMD_BIMC_GPU_A_CLK] = &qcm2290_bimc_gpu_a_clk,
1114         [RPM_SMD_CPUSS_GNOC_CLK] = &qcm2290_cpuss_gnoc_clk,
1115         [RPM_SMD_CPUSS_GNOC_A_CLK] = &qcm2290_cpuss_gnoc_a_clk,
1116 };
1117
1118 static const struct rpm_smd_clk_desc rpm_clk_qcm2290 = {
1119         .clks = qcm2290_clks,
1120         .num_clks = ARRAY_SIZE(qcm2290_clks),
1121 };
1122
1123 static const struct of_device_id rpm_smd_clk_match_table[] = {
1124         { .compatible = "qcom,rpmcc-mdm9607", .data = &rpm_clk_mdm9607 },
1125         { .compatible = "qcom,rpmcc-msm8226", .data = &rpm_clk_msm8974 },
1126         { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
1127         { .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
1128         { .compatible = "qcom,rpmcc-msm8953", .data = &rpm_clk_msm8953 },
1129         { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
1130         { .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
1131         { .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
1132         { .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
1133         { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
1134         { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
1135         { .compatible = "qcom,rpmcc-qcm2290", .data = &rpm_clk_qcm2290 },
1136         { .compatible = "qcom,rpmcc-qcs404",  .data = &rpm_clk_qcs404  },
1137         { .compatible = "qcom,rpmcc-sdm660",  .data = &rpm_clk_sdm660  },
1138         { .compatible = "qcom,rpmcc-sm6115",  .data = &rpm_clk_sm6115  },
1139         { .compatible = "qcom,rpmcc-sm6125",  .data = &rpm_clk_sm6125  },
1140         { }
1141 };
1142 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
1143
1144 static struct clk_hw *qcom_smdrpm_clk_hw_get(struct of_phandle_args *clkspec,
1145                                              void *data)
1146 {
1147         const struct rpm_smd_clk_desc *desc = data;
1148         unsigned int idx = clkspec->args[0];
1149
1150         if (idx >= desc->num_clks) {
1151                 pr_err("%s: invalid index %u\n", __func__, idx);
1152                 return ERR_PTR(-EINVAL);
1153         }
1154
1155         return desc->clks[idx] ? &desc->clks[idx]->hw : ERR_PTR(-ENOENT);
1156 }
1157
1158 static int rpm_smd_clk_probe(struct platform_device *pdev)
1159 {
1160         int ret;
1161         size_t num_clks, i;
1162         struct qcom_smd_rpm *rpm;
1163         struct clk_smd_rpm **rpm_smd_clks;
1164         const struct rpm_smd_clk_desc *desc;
1165
1166         rpm = dev_get_drvdata(pdev->dev.parent);
1167         if (!rpm) {
1168                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
1169                 return -ENODEV;
1170         }
1171
1172         desc = of_device_get_match_data(&pdev->dev);
1173         if (!desc)
1174                 return -EINVAL;
1175
1176         rpm_smd_clks = desc->clks;
1177         num_clks = desc->num_clks;
1178
1179         for (i = 0; i < num_clks; i++) {
1180                 if (!rpm_smd_clks[i])
1181                         continue;
1182
1183                 rpm_smd_clks[i]->rpm = rpm;
1184
1185                 ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
1186                 if (ret)
1187                         goto err;
1188         }
1189
1190         ret = clk_smd_rpm_enable_scaling(rpm);
1191         if (ret)
1192                 goto err;
1193
1194         for (i = 0; i < num_clks; i++) {
1195                 if (!rpm_smd_clks[i])
1196                         continue;
1197
1198                 ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
1199                 if (ret)
1200                         goto err;
1201         }
1202
1203         ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_smdrpm_clk_hw_get,
1204                                           (void *)desc);
1205         if (ret)
1206                 goto err;
1207
1208         return 0;
1209 err:
1210         dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
1211         return ret;
1212 }
1213
1214 static struct platform_driver rpm_smd_clk_driver = {
1215         .driver = {
1216                 .name = "qcom-clk-smd-rpm",
1217                 .of_match_table = rpm_smd_clk_match_table,
1218         },
1219         .probe = rpm_smd_clk_probe,
1220 };
1221
1222 static int __init rpm_smd_clk_init(void)
1223 {
1224         return platform_driver_register(&rpm_smd_clk_driver);
1225 }
1226 core_initcall(rpm_smd_clk_init);
1227
1228 static void __exit rpm_smd_clk_exit(void)
1229 {
1230         platform_driver_unregister(&rpm_smd_clk_driver);
1231 }
1232 module_exit(rpm_smd_clk_exit);
1233
1234 MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
1235 MODULE_LICENSE("GPL v2");
1236 MODULE_ALIAS("platform:qcom-clk-smd-rpm");