drivers/clk/qcom/clk-rpmh.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk-provider.h>
   7 #include <linux/err.h>
   8 #include <linux/kernel.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/platform_device.h>
  13 #include <soc/qcom/cmd-db.h>
  14 #include <soc/qcom/rpmh.h>
  15
  16 #include <dt-bindings/clock/qcom,rpmh.h>
  17
  18 #define CLK_RPMH_ARC_EN_OFFSET          0
  19 #define CLK_RPMH_VRM_EN_OFFSET          4
  20
  21 #define BCM_TCS_CMD_COMMIT_MASK         0x40000000
  22 #define BCM_TCS_CMD_VALID_SHIFT         29
  23 #define BCM_TCS_CMD_VOTE_MASK           0x3fff
  24 #define BCM_TCS_CMD_VOTE_SHIFT          0
  25
  26 #define BCM_TCS_CMD(valid, vote)                                \
  27         (BCM_TCS_CMD_COMMIT_MASK |                              \
  28         ((valid) << BCM_TCS_CMD_VALID_SHIFT) |                  \
  29         ((vote & BCM_TCS_CMD_VOTE_MASK)                         \
  30         << BCM_TCS_CMD_VOTE_SHIFT))
  31
  32 /**
  33  * struct bcm_db - Auxiliary data pertaining to each Bus Clock Manager(BCM)
  34  * @unit: divisor used to convert Hz value to an RPMh msg
  35  * @width: multiplier used to convert Hz value to an RPMh msg
  36  * @vcd: virtual clock domain that this bcm belongs to
  37  * @reserved: reserved to pad the struct
  38  */
  39 struct bcm_db {
  40         __le32 unit;
  41         __le16 width;
  42         u8 vcd;
  43         u8 reserved;
  44 };
  45
  46 /**
  47  * struct clk_rpmh - individual rpmh clock data structure
  48  * @hw:                 handle between common and hardware-specific interfaces
  49  * @res_name:           resource name for the rpmh clock
  50  * @div:                clock divider to compute the clock rate
  51  * @res_addr:           base address of the rpmh resource within the RPMh
  52  * @res_on_val:         rpmh clock enable value
  53  * @state:              rpmh clock requested state
  54  * @aggr_state:         rpmh clock aggregated state
  55  * @last_sent_aggr_state: rpmh clock last aggr state sent to RPMh
  56  * @valid_state_mask:   mask to determine the state of the rpmh clock
  57  * @unit:               divisor to convert rate to rpmh msg in magnitudes of Khz
  58  * @dev:                device to which it is attached
  59  * @peer:               pointer to the clock rpmh sibling
  60  */
  61 struct clk_rpmh {
  62         struct clk_hw hw;
  63         const char *res_name;
  64         u8 div;
  65         u32 res_addr;
  66         u32 res_on_val;
  67         u32 state;
  68         u32 aggr_state;
  69         u32 last_sent_aggr_state;
  70         u32 valid_state_mask;
  71         u32 unit;
  72         struct device *dev;
  73         struct clk_rpmh *peer;
  74 };
  75
  76 struct clk_rpmh_desc {
  77         struct clk_hw **clks;
  78         size_t num_clks;
  79 };
  80
  81 static DEFINE_MUTEX(rpmh_clk_lock);
  82
  83 #define __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,    \
  84                           _res_en_offset, _res_on, _div)                \
  85         static struct clk_rpmh _platform##_##_name_active;              \
  86         static struct clk_rpmh _platform##_##_name = {                  \
  87                 .res_name = _res_name,                                  \
  88                 .res_addr = _res_en_offset,                             \
  89                 .res_on_val = _res_on,                                  \
  90                 .div = _div,                                            \
  91                 .peer = &_platform##_##_name_active,                    \
  92                 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |        \
  93                                       BIT(RPMH_ACTIVE_ONLY_STATE) |     \
  94                                       BIT(RPMH_SLEEP_STATE)),           \
  95                 .hw.init = &(struct clk_init_data){                     \
  96                         .ops = &clk_rpmh_ops,                           \
  97                         .name = #_name,                                 \
  98                         .parent_data =  &(const struct clk_parent_data){ \
  99                                         .fw_name = "xo",                \
 100                                         .name = "xo_board",             \
 101                         },                                              \
 102                         .num_parents = 1,                               \
 103                 },                                                      \
 104         };                                                              \
 105         static struct clk_rpmh _platform##_##_name_active = {           \
 106                 .res_name = _res_name,                                  \
 107                 .res_addr = _res_en_offset,                             \
 108                 .res_on_val = _res_on,                                  \
 109                 .div = _div,                                            \
 110                 .peer = &_platform##_##_name,                           \
 111                 .valid_state_mask = (BIT(RPMH_WAKE_ONLY_STATE) |        \
 112                                         BIT(RPMH_ACTIVE_ONLY_STATE)),   \
 113                 .hw.init = &(struct clk_init_data){                     \
 114                         .ops = &clk_rpmh_ops,                           \
 115                         .name = #_name_active,                          \
 116                         .parent_data =  &(const struct clk_parent_data){ \
 117                                         .fw_name = "xo",                \
 118                                         .name = "xo_board",             \
 119                         },                                              \
 120                         .num_parents = 1,                               \
 121                 },                                                      \
 122         }
 123
 124 #define DEFINE_CLK_RPMH_ARC(_platform, _name, _name_active, _res_name,  \
 125                             _res_on, _div)                              \
 126         __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,    \
 127                           CLK_RPMH_ARC_EN_OFFSET, _res_on, _div)
 128
 129 #define DEFINE_CLK_RPMH_VRM(_platform, _name, _name_active, _res_name,  \
 130                                 _div)                                   \
 131         __DEFINE_CLK_RPMH(_platform, _name, _name_active, _res_name,    \
 132                           CLK_RPMH_VRM_EN_OFFSET, 1, _div)
 133
 134 #define DEFINE_CLK_RPMH_BCM(_platform, _name, _res_name)                \
 135         static struct clk_rpmh _platform##_##_name = {                  \
 136                 .res_name = _res_name,                                  \
 137                 .valid_state_mask = BIT(RPMH_ACTIVE_ONLY_STATE),        \
 138                 .div = 1,                                               \
 139                 .hw.init = &(struct clk_init_data){                     \
 140                         .ops = &clk_rpmh_bcm_ops,                       \
 141                         .name = #_name,                                 \
 142                 },                                                      \
 143         }
 144
 145 static inline struct clk_rpmh *to_clk_rpmh(struct clk_hw *_hw)
 146 {
 147         return container_of(_hw, struct clk_rpmh, hw);
 148 }
 149
 150 static inline bool has_state_changed(struct clk_rpmh *c, u32 state)
 151 {
 152         return (c->last_sent_aggr_state & BIT(state))
 153                 != (c->aggr_state & BIT(state));
 154 }
 155
 156 static int clk_rpmh_send_aggregate_command(struct clk_rpmh *c)
 157 {
 158         struct tcs_cmd cmd = { 0 };
 159         u32 cmd_state, on_val;
 160         enum rpmh_state state = RPMH_SLEEP_STATE;
 161         int ret;
 162
 163         cmd.addr = c->res_addr;
 164         cmd_state = c->aggr_state;
 165         on_val = c->res_on_val;
 166
 167         for (; state <= RPMH_ACTIVE_ONLY_STATE; state++) {
 168                 if (has_state_changed(c, state)) {
 169                         if (cmd_state & BIT(state))
 170                                 cmd.data = on_val;
 171
 172                         ret = rpmh_write_async(c->dev, state, &cmd, 1);
 173                         if (ret) {
 174                                 dev_err(c->dev, "set %s state of %s failed: (%d)\n",
 175                                         !state ? "sleep" :
 176                                         state == RPMH_WAKE_ONLY_STATE   ?
 177                                         "wake" : "active", c->res_name, ret);
 178                                 return ret;
 179                         }
 180                 }
 181         }
 182
 183         c->last_sent_aggr_state = c->aggr_state;
 184         c->peer->last_sent_aggr_state =  c->last_sent_aggr_state;
 185
 186         return 0;
 187 }
 188
 189 /*
 190  * Update state and aggregate state values based on enable value.
 191  */
 192 static int clk_rpmh_aggregate_state_send_command(struct clk_rpmh *c,
 193                                                 bool enable)
 194 {
 195         int ret;
 196
 197         /* Nothing required to be done if already off or on */
 198         if (enable == c->state)
 199                 return 0;
 200
 201         c->state = enable ? c->valid_state_mask : 0;
 202         c->aggr_state = c->state | c->peer->state;
 203         c->peer->aggr_state = c->aggr_state;
 204
 205         ret = clk_rpmh_send_aggregate_command(c);
 206         if (!ret)
 207                 return 0;
 208
 209         if (ret && enable)
 210                 c->state = 0;
 211         else if (ret)
 212                 c->state = c->valid_state_mask;
 213
 214         WARN(1, "clk: %s failed to %s\n", c->res_name,
 215              enable ? "enable" : "disable");
 216         return ret;
 217 }
 218
 219 static int clk_rpmh_prepare(struct clk_hw *hw)
 220 {
 221         struct clk_rpmh *c = to_clk_rpmh(hw);
 222         int ret = 0;
 223
 224         mutex_lock(&rpmh_clk_lock);
 225         ret = clk_rpmh_aggregate_state_send_command(c, true);
 226         mutex_unlock(&rpmh_clk_lock);
 227
 228         return ret;
 229 };
 230
 231 static void clk_rpmh_unprepare(struct clk_hw *hw)
 232 {
 233         struct clk_rpmh *c = to_clk_rpmh(hw);
 234
 235         mutex_lock(&rpmh_clk_lock);
 236         clk_rpmh_aggregate_state_send_command(c, false);
 237         mutex_unlock(&rpmh_clk_lock);
 238 };
 239
 240 static unsigned long clk_rpmh_recalc_rate(struct clk_hw *hw,
 241                                         unsigned long prate)
 242 {
 243         struct clk_rpmh *r = to_clk_rpmh(hw);
 244
 245         /*
 246          * RPMh clocks have a fixed rate. Return static rate.
 247          */
 248         return prate / r->div;
 249 }
 250
 251 static const struct clk_ops clk_rpmh_ops = {
 252         .prepare        = clk_rpmh_prepare,
 253         .unprepare      = clk_rpmh_unprepare,
 254         .recalc_rate    = clk_rpmh_recalc_rate,
 255 };
 256
 257 static int clk_rpmh_bcm_send_cmd(struct clk_rpmh *c, bool enable)
 258 {
 259         struct tcs_cmd cmd = { 0 };
 260         u32 cmd_state;
 261         int ret;
 262
 263         mutex_lock(&rpmh_clk_lock);
 264
 265         cmd_state = 0;
 266         if (enable) {
 267                 cmd_state = 1;
 268                 if (c->aggr_state)
 269                         cmd_state = c->aggr_state;
 270         }
 271
 272         if (c->last_sent_aggr_state == cmd_state) {
 273                 mutex_unlock(&rpmh_clk_lock);
 274                 return 0;
 275         }
 276
 277         cmd.addr = c->res_addr;
 278         cmd.data = BCM_TCS_CMD(enable, cmd_state);
 279
 280         ret = rpmh_write_async(c->dev, RPMH_ACTIVE_ONLY_STATE, &cmd, 1);
 281         if (ret) {
 282                 dev_err(c->dev, "set active state of %s failed: (%d)\n",
 283                         c->res_name, ret);
 284                 mutex_unlock(&rpmh_clk_lock);
 285                 return ret;
 286         }
 287
 288         c->last_sent_aggr_state = cmd_state;
 289
 290         mutex_unlock(&rpmh_clk_lock);
 291
 292         return 0;
 293 }
 294
 295 static int clk_rpmh_bcm_prepare(struct clk_hw *hw)
 296 {
 297         struct clk_rpmh *c = to_clk_rpmh(hw);
 298
 299         return clk_rpmh_bcm_send_cmd(c, true);
 300 };
 301
 302 static void clk_rpmh_bcm_unprepare(struct clk_hw *hw)
 303 {
 304         struct clk_rpmh *c = to_clk_rpmh(hw);
 305
 306         clk_rpmh_bcm_send_cmd(c, false);
 307 };
 308
 309 static int clk_rpmh_bcm_set_rate(struct clk_hw *hw, unsigned long rate,
 310                                  unsigned long parent_rate)
 311 {
 312         struct clk_rpmh *c = to_clk_rpmh(hw);
 313
 314         c->aggr_state = rate / c->unit;
 315         /*
 316          * Since any non-zero value sent to hw would result in enabling the
 317          * clock, only send the value if the clock has already been prepared.
 318          */
 319         if (clk_hw_is_prepared(hw))
 320                 clk_rpmh_bcm_send_cmd(c, true);
 321
 322         return 0;
 323 };
 324
 325 static long clk_rpmh_round_rate(struct clk_hw *hw, unsigned long rate,
 326                                 unsigned long *parent_rate)
 327 {
 328         return rate;
 329 }
 330
 331 static unsigned long clk_rpmh_bcm_recalc_rate(struct clk_hw *hw,
 332                                         unsigned long prate)
 333 {
 334         struct clk_rpmh *c = to_clk_rpmh(hw);
 335
 336         return c->aggr_state * c->unit;
 337 }
 338
 339 static const struct clk_ops clk_rpmh_bcm_ops = {
 340         .prepare        = clk_rpmh_bcm_prepare,
 341         .unprepare      = clk_rpmh_bcm_unprepare,
 342         .set_rate       = clk_rpmh_bcm_set_rate,
 343         .round_rate     = clk_rpmh_round_rate,
 344         .recalc_rate    = clk_rpmh_bcm_recalc_rate,
 345 };
 346
 347 /* Resource name must match resource id present in cmd-db. */
 348 DEFINE_CLK_RPMH_ARC(sdm845, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
 349 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
 350 DEFINE_CLK_RPMH_VRM(sdm845, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
 351 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk1, rf_clk1_ao, "rfclka1", 1);
 352 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk2, rf_clk2_ao, "rfclka2", 1);
 353 DEFINE_CLK_RPMH_VRM(sdm845, rf_clk3, rf_clk3_ao, "rfclka3", 1);
 354 DEFINE_CLK_RPMH_BCM(sdm845, ipa, "IP0");
 355
 356 static struct clk_hw *sdm845_rpmh_clocks[] = {
 357         [RPMH_CXO_CLK]          = &sdm845_bi_tcxo.hw,
 358         [RPMH_CXO_CLK_A]        = &sdm845_bi_tcxo_ao.hw,
 359         [RPMH_LN_BB_CLK2]       = &sdm845_ln_bb_clk2.hw,
 360         [RPMH_LN_BB_CLK2_A]     = &sdm845_ln_bb_clk2_ao.hw,
 361         [RPMH_LN_BB_CLK3]       = &sdm845_ln_bb_clk3.hw,
 362         [RPMH_LN_BB_CLK3_A]     = &sdm845_ln_bb_clk3_ao.hw,
 363         [RPMH_RF_CLK1]          = &sdm845_rf_clk1.hw,
 364         [RPMH_RF_CLK1_A]        = &sdm845_rf_clk1_ao.hw,
 365         [RPMH_RF_CLK2]          = &sdm845_rf_clk2.hw,
 366         [RPMH_RF_CLK2_A]        = &sdm845_rf_clk2_ao.hw,
 367         [RPMH_RF_CLK3]          = &sdm845_rf_clk3.hw,
 368         [RPMH_RF_CLK3_A]        = &sdm845_rf_clk3_ao.hw,
 369         [RPMH_IPA_CLK]          = &sdm845_ipa.hw,
 370 };
 371
 372 static const struct clk_rpmh_desc clk_rpmh_sdm845 = {
 373         .clks = sdm845_rpmh_clocks,
 374         .num_clks = ARRAY_SIZE(sdm845_rpmh_clocks),
 375 };
 376
 377 DEFINE_CLK_RPMH_ARC(sm8150, bi_tcxo, bi_tcxo_ao, "xo.lvl", 0x3, 2);
 378 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk2, ln_bb_clk2_ao, "lnbclka2", 2);
 379 DEFINE_CLK_RPMH_VRM(sm8150, ln_bb_clk3, ln_bb_clk3_ao, "lnbclka3", 2);
 380 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk1, rf_clk1_ao, "rfclka1", 1);
 381 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk2, rf_clk2_ao, "rfclka2", 1);
 382 DEFINE_CLK_RPMH_VRM(sm8150, rf_clk3, rf_clk3_ao, "rfclka3", 1);
 383
 384 static struct clk_hw *sm8150_rpmh_clocks[] = {
 385         [RPMH_CXO_CLK]          = &sm8150_bi_tcxo.hw,
 386         [RPMH_CXO_CLK_A]        = &sm8150_bi_tcxo_ao.hw,
 387         [RPMH_LN_BB_CLK2]       = &sm8150_ln_bb_clk2.hw,
 388         [RPMH_LN_BB_CLK2_A]     = &sm8150_ln_bb_clk2_ao.hw,
 389         [RPMH_LN_BB_CLK3]       = &sm8150_ln_bb_clk3.hw,
 390         [RPMH_LN_BB_CLK3_A]     = &sm8150_ln_bb_clk3_ao.hw,
 391         [RPMH_RF_CLK1]          = &sm8150_rf_clk1.hw,
 392         [RPMH_RF_CLK1_A]        = &sm8150_rf_clk1_ao.hw,
 393         [RPMH_RF_CLK2]          = &sm8150_rf_clk2.hw,
 394         [RPMH_RF_CLK2_A]        = &sm8150_rf_clk2_ao.hw,
 395         [RPMH_RF_CLK3]          = &sm8150_rf_clk3.hw,
 396         [RPMH_RF_CLK3_A]        = &sm8150_rf_clk3_ao.hw,
 397 };
 398
 399 static const struct clk_rpmh_desc clk_rpmh_sm8150 = {
 400         .clks = sm8150_rpmh_clocks,
 401         .num_clks = ARRAY_SIZE(sm8150_rpmh_clocks),
 402 };
 403
 404 static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
 405                                          void *data)
 406 {
 407         struct clk_rpmh_desc *rpmh = data;
 408         unsigned int idx = clkspec->args[0];
 409
 410         if (idx >= rpmh->num_clks) {
 411                 pr_err("%s: invalid index %u\n", __func__, idx);
 412                 return ERR_PTR(-EINVAL);
 413         }
 414
 415         return rpmh->clks[idx];
 416 }
 417
 418 static int clk_rpmh_probe(struct platform_device *pdev)
 419 {
 420         struct clk_hw **hw_clks;
 421         struct clk_rpmh *rpmh_clk;
 422         const struct clk_rpmh_desc *desc;
 423         int ret, i;
 424
 425         desc = of_device_get_match_data(&pdev->dev);
 426         if (!desc)
 427                 return -ENODEV;
 428
 429         hw_clks = desc->clks;
 430
 431         for (i = 0; i < desc->num_clks; i++) {
 432                 const char *name = hw_clks[i]->init->name;
 433                 u32 res_addr;
 434                 size_t aux_data_len;
 435                 const struct bcm_db *data;
 436
 437                 rpmh_clk = to_clk_rpmh(hw_clks[i]);
 438                 res_addr = cmd_db_read_addr(rpmh_clk->res_name);
 439                 if (!res_addr) {
 440                         dev_err(&pdev->dev, "missing RPMh resource address for %s\n",
 441                                 rpmh_clk->res_name);
 442                         return -ENODEV;
 443                 }
 444
 445                 data = cmd_db_read_aux_data(rpmh_clk->res_name, &aux_data_len);
 446                 if (IS_ERR(data)) {
 447                         ret = PTR_ERR(data);
 448                         dev_err(&pdev->dev,
 449                                 "error reading RPMh aux data for %s (%d)\n",
 450                                 rpmh_clk->res_name, ret);
 451                         return ret;
 452                 }
 453
 454                 /* Convert unit from Khz to Hz */
 455                 if (aux_data_len == sizeof(*data))
 456                         rpmh_clk->unit = le32_to_cpu(data->unit) * 1000ULL;
 457
 458                 rpmh_clk->res_addr += res_addr;
 459                 rpmh_clk->dev = &pdev->dev;
 460
 461                 ret = devm_clk_hw_register(&pdev->dev, hw_clks[i]);
 462                 if (ret) {
 463                         dev_err(&pdev->dev, "failed to register %s\n", name);
 464                         return ret;
 465                 }
 466         }
 467
 468         /* typecast to silence compiler warning */
 469         ret = devm_of_clk_add_hw_provider(&pdev->dev, of_clk_rpmh_hw_get,
 470                                           (void *)desc);
 471         if (ret) {
 472                 dev_err(&pdev->dev, "Failed to add clock provider\n");
 473                 return ret;
 474         }
 475
 476         dev_dbg(&pdev->dev, "Registered RPMh clocks\n");
 477
 478         return 0;
 479 }
 480
 481 static const struct of_device_id clk_rpmh_match_table[] = {
 482         { .compatible = "qcom,sdm845-rpmh-clk", .data = &clk_rpmh_sdm845},
 483         { .compatible = "qcom,sm8150-rpmh-clk", .data = &clk_rpmh_sm8150},
 484         { }
 485 };
 486 MODULE_DEVICE_TABLE(of, clk_rpmh_match_table);
 487
 488 static struct platform_driver clk_rpmh_driver = {
 489         .probe          = clk_rpmh_probe,
 490         .driver         = {
 491                 .name   = "clk-rpmh",
 492                 .of_match_table = clk_rpmh_match_table,
 493         },
 494 };
 495
 496 static int __init clk_rpmh_init(void)
 497 {
 498         return platform_driver_register(&clk_rpmh_driver);
 499 }
 500 subsys_initcall(clk_rpmh_init);
 501
 502 static void __exit clk_rpmh_exit(void)
 503 {
 504         platform_driver_unregister(&clk_rpmh_driver);
 505 }
 506 module_exit(clk_rpmh_exit);
 507
 508 MODULE_DESCRIPTION("QCOM RPMh Clock Driver");
 509 MODULE_LICENSE("GPL v2");