drivers/clk/qcom/clk-rpm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2016, Linaro Limited
   4  * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/export.h>
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/mutex.h>
  14 #include <linux/mfd/qcom_rpm.h>
  15 #include <linux/of.h>
  16 #include <linux/platform_device.h>
  17
  18 #include <dt-bindings/mfd/qcom-rpm.h>
  19 #include <dt-bindings/clock/qcom,rpmcc.h>
  20
  21 #define QCOM_RPM_MISC_CLK_TYPE                          0x306b6c63
  22 #define QCOM_RPM_SCALING_ENABLE_ID                      0x2
  23 #define QCOM_RPM_XO_MODE_ON                             0x2
  24
  25 static const struct clk_parent_data gcc_pxo[] = {
  26         { .fw_name = "pxo", .name = "pxo_board" },
  27 };
  28
  29 static const struct clk_parent_data gcc_cxo[] = {
  30         { .fw_name = "cxo", .name = "cxo_board" },
  31 };
  32
  33 #define DEFINE_CLK_RPM(_name, r_id)                                           \
  34         static struct clk_rpm clk_rpm_##_name##_a_clk;                        \
  35         static struct clk_rpm clk_rpm_##_name##_clk = {                       \
  36                 .rpm_clk_id = (r_id),                                         \
  37                 .peer = &clk_rpm_##_name##_a_clk,                             \
  38                 .rate = INT_MAX,                                              \
  39                 .hw.init = &(struct clk_init_data){                           \
  40                         .ops = &clk_rpm_ops,                                  \
  41                         .name = #_name "_clk",                                \
  42                         .parent_data = gcc_pxo,                               \
  43                         .num_parents = ARRAY_SIZE(gcc_pxo),                   \
  44                 },                                                            \
  45         };                                                                    \
  46         static struct clk_rpm clk_rpm_##_name##_a_clk = {                     \
  47                 .rpm_clk_id = (r_id),                                         \
  48                 .peer = &clk_rpm_##_name##_clk,                               \
  49                 .active_only = true,                                          \
  50                 .rate = INT_MAX,                                              \
  51                 .hw.init = &(struct clk_init_data){                           \
  52                         .ops = &clk_rpm_ops,                                  \
  53                         .name = #_name "_a_clk",                              \
  54                         .parent_data = gcc_pxo,                               \
  55                         .num_parents = ARRAY_SIZE(gcc_pxo),                   \
  56                 },                                                            \
  57         }
  58
  59 #define DEFINE_CLK_RPM_XO_BUFFER(_name, offset)                               \
  60         static struct clk_rpm clk_rpm_##_name##_clk = {                       \
  61                 .rpm_clk_id = QCOM_RPM_CXO_BUFFERS,                           \
  62                 .xo_offset = (offset),                                        \
  63                 .hw.init = &(struct clk_init_data){                           \
  64                         .ops = &clk_rpm_xo_ops,                               \
  65                         .name = #_name "_clk",                                \
  66                         .parent_data = gcc_cxo,                               \
  67                         .num_parents = ARRAY_SIZE(gcc_cxo),                   \
  68                 },                                                            \
  69         }
  70
  71 #define DEFINE_CLK_RPM_FIXED(_name, r_id, r)                                  \
  72         static struct clk_rpm clk_rpm_##_name##_clk = {                       \
  73                 .rpm_clk_id = (r_id),                                         \
  74                 .rate = (r),                                                  \
  75                 .hw.init = &(struct clk_init_data){                           \
  76                         .ops = &clk_rpm_fixed_ops,                            \
  77                         .name = #_name "_clk",                                \
  78                         .parent_data = gcc_pxo,                               \
  79                         .num_parents = ARRAY_SIZE(gcc_pxo),                   \
  80                 },                                                            \
  81         }
  82
  83 #define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
  84
  85 struct rpm_cc;
  86
  87 struct clk_rpm {
  88         const int rpm_clk_id;
  89         const int xo_offset;
  90         const bool active_only;
  91         unsigned long rate;
  92         bool enabled;
  93         bool branch;
  94         struct clk_rpm *peer;
  95         struct clk_hw hw;
  96         struct qcom_rpm *rpm;
  97         struct rpm_cc *rpm_cc;
  98 };
  99
 100 struct rpm_cc {
 101         struct qcom_rpm *rpm;
 102         struct clk_rpm **clks;
 103         size_t num_clks;
 104         u32 xo_buffer_value;
 105         struct mutex xo_lock;
 106 };
 107
 108 struct rpm_clk_desc {
 109         struct clk_rpm **clks;
 110         size_t num_clks;
 111 };
 112
 113 static DEFINE_MUTEX(rpm_clk_lock);
 114
 115 static int clk_rpm_handoff(struct clk_rpm *r)
 116 {
 117         int ret;
 118         u32 value = INT_MAX;
 119
 120         /*
 121          * The vendor tree simply reads the status for this
 122          * RPM clock.
 123          */
 124         if (r->rpm_clk_id == QCOM_RPM_PLL_4 ||
 125                 r->rpm_clk_id == QCOM_RPM_CXO_BUFFERS)
 126                 return 0;
 127
 128         ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
 129                              r->rpm_clk_id, &value, 1);
 130         if (ret)
 131                 return ret;
 132         ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
 133                              r->rpm_clk_id, &value, 1);
 134         if (ret)
 135                 return ret;
 136
 137         return 0;
 138 }
 139
 140 static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
 141 {
 142         u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
 143
 144         return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
 145                               r->rpm_clk_id, &value, 1);
 146 }
 147
 148 static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
 149 {
 150         u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
 151
 152         return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
 153                               r->rpm_clk_id, &value, 1);
 154 }
 155
 156 static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
 157                             unsigned long *active, unsigned long *sleep)
 158 {
 159         *active = rate;
 160
 161         /*
 162          * Active-only clocks don't care what the rate is during sleep. So,
 163          * they vote for zero.
 164          */
 165         if (r->active_only)
 166                 *sleep = 0;
 167         else
 168                 *sleep = *active;
 169 }
 170
 171 static int clk_rpm_prepare(struct clk_hw *hw)
 172 {
 173         struct clk_rpm *r = to_clk_rpm(hw);
 174         struct clk_rpm *peer = r->peer;
 175         unsigned long this_rate = 0, this_sleep_rate = 0;
 176         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 177         unsigned long active_rate, sleep_rate;
 178         int ret = 0;
 179
 180         mutex_lock(&rpm_clk_lock);
 181
 182         /* Don't send requests to the RPM if the rate has not been set. */
 183         if (!r->rate)
 184                 goto out;
 185
 186         to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
 187
 188         /* Take peer clock's rate into account only if it's enabled. */
 189         if (peer->enabled)
 190                 to_active_sleep(peer, peer->rate,
 191                                 &peer_rate, &peer_sleep_rate);
 192
 193         active_rate = max(this_rate, peer_rate);
 194
 195         if (r->branch)
 196                 active_rate = !!active_rate;
 197
 198         ret = clk_rpm_set_rate_active(r, active_rate);
 199         if (ret)
 200                 goto out;
 201
 202         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 203         if (r->branch)
 204                 sleep_rate = !!sleep_rate;
 205
 206         ret = clk_rpm_set_rate_sleep(r, sleep_rate);
 207         if (ret)
 208                 /* Undo the active set vote and restore it */
 209                 ret = clk_rpm_set_rate_active(r, peer_rate);
 210
 211 out:
 212         if (!ret)
 213                 r->enabled = true;
 214
 215         mutex_unlock(&rpm_clk_lock);
 216
 217         return ret;
 218 }
 219
 220 static void clk_rpm_unprepare(struct clk_hw *hw)
 221 {
 222         struct clk_rpm *r = to_clk_rpm(hw);
 223         struct clk_rpm *peer = r->peer;
 224         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 225         unsigned long active_rate, sleep_rate;
 226         int ret;
 227
 228         mutex_lock(&rpm_clk_lock);
 229
 230         if (!r->rate)
 231                 goto out;
 232
 233         /* Take peer clock's rate into account only if it's enabled. */
 234         if (peer->enabled)
 235                 to_active_sleep(peer, peer->rate, &peer_rate,
 236                                 &peer_sleep_rate);
 237
 238         active_rate = r->branch ? !!peer_rate : peer_rate;
 239         ret = clk_rpm_set_rate_active(r, active_rate);
 240         if (ret)
 241                 goto out;
 242
 243         sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
 244         ret = clk_rpm_set_rate_sleep(r, sleep_rate);
 245         if (ret)
 246                 goto out;
 247
 248         r->enabled = false;
 249
 250 out:
 251         mutex_unlock(&rpm_clk_lock);
 252 }
 253
 254 static int clk_rpm_xo_prepare(struct clk_hw *hw)
 255 {
 256         struct clk_rpm *r = to_clk_rpm(hw);
 257         struct rpm_cc *rcc = r->rpm_cc;
 258         int ret, clk_id = r->rpm_clk_id;
 259         u32 value;
 260
 261         mutex_lock(&rcc->xo_lock);
 262
 263         value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset);
 264         ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
 265         if (!ret) {
 266                 r->enabled = true;
 267                 rcc->xo_buffer_value = value;
 268         }
 269
 270         mutex_unlock(&rcc->xo_lock);
 271
 272         return ret;
 273 }
 274
 275 static void clk_rpm_xo_unprepare(struct clk_hw *hw)
 276 {
 277         struct clk_rpm *r = to_clk_rpm(hw);
 278         struct rpm_cc *rcc = r->rpm_cc;
 279         int ret, clk_id = r->rpm_clk_id;
 280         u32 value;
 281
 282         mutex_lock(&rcc->xo_lock);
 283
 284         value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset);
 285         ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE, clk_id, &value, 1);
 286         if (!ret) {
 287                 r->enabled = false;
 288                 rcc->xo_buffer_value = value;
 289         }
 290
 291         mutex_unlock(&rcc->xo_lock);
 292 }
 293
 294 static int clk_rpm_fixed_prepare(struct clk_hw *hw)
 295 {
 296         struct clk_rpm *r = to_clk_rpm(hw);
 297         u32 value = 1;
 298         int ret;
 299
 300         ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
 301                              r->rpm_clk_id, &value, 1);
 302         if (!ret)
 303                 r->enabled = true;
 304
 305         return ret;
 306 }
 307
 308 static void clk_rpm_fixed_unprepare(struct clk_hw *hw)
 309 {
 310         struct clk_rpm *r = to_clk_rpm(hw);
 311         u32 value = 0;
 312         int ret;
 313
 314         ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
 315                              r->rpm_clk_id, &value, 1);
 316         if (!ret)
 317                 r->enabled = false;
 318 }
 319
 320 static int clk_rpm_set_rate(struct clk_hw *hw,
 321                             unsigned long rate, unsigned long parent_rate)
 322 {
 323         struct clk_rpm *r = to_clk_rpm(hw);
 324         struct clk_rpm *peer = r->peer;
 325         unsigned long active_rate, sleep_rate;
 326         unsigned long this_rate = 0, this_sleep_rate = 0;
 327         unsigned long peer_rate = 0, peer_sleep_rate = 0;
 328         int ret = 0;
 329
 330         mutex_lock(&rpm_clk_lock);
 331
 332         if (!r->enabled)
 333                 goto out;
 334
 335         to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
 336
 337         /* Take peer clock's rate into account only if it's enabled. */
 338         if (peer->enabled)
 339                 to_active_sleep(peer, peer->rate,
 340                                 &peer_rate, &peer_sleep_rate);
 341
 342         active_rate = max(this_rate, peer_rate);
 343         ret = clk_rpm_set_rate_active(r, active_rate);
 344         if (ret)
 345                 goto out;
 346
 347         sleep_rate = max(this_sleep_rate, peer_sleep_rate);
 348         ret = clk_rpm_set_rate_sleep(r, sleep_rate);
 349         if (ret)
 350                 goto out;
 351
 352         r->rate = rate;
 353
 354 out:
 355         mutex_unlock(&rpm_clk_lock);
 356
 357         return ret;
 358 }
 359
 360 static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
 361                                unsigned long *parent_rate)
 362 {
 363         /*
 364          * RPM handles rate rounding and we don't have a way to
 365          * know what the rate will be, so just return whatever
 366          * rate is requested.
 367          */
 368         return rate;
 369 }
 370
 371 static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
 372                                          unsigned long parent_rate)
 373 {
 374         struct clk_rpm *r = to_clk_rpm(hw);
 375
 376         /*
 377          * RPM handles rate rounding and we don't have a way to
 378          * know what the rate will be, so just return whatever
 379          * rate was set.
 380          */
 381         return r->rate;
 382 }
 383
 384 static const struct clk_ops clk_rpm_xo_ops = {
 385         .prepare        = clk_rpm_xo_prepare,
 386         .unprepare      = clk_rpm_xo_unprepare,
 387 };
 388
 389 static const struct clk_ops clk_rpm_fixed_ops = {
 390         .prepare        = clk_rpm_fixed_prepare,
 391         .unprepare      = clk_rpm_fixed_unprepare,
 392         .round_rate     = clk_rpm_round_rate,
 393         .recalc_rate    = clk_rpm_recalc_rate,
 394 };
 395
 396 static const struct clk_ops clk_rpm_ops = {
 397         .prepare        = clk_rpm_prepare,
 398         .unprepare      = clk_rpm_unprepare,
 399         .set_rate       = clk_rpm_set_rate,
 400         .round_rate     = clk_rpm_round_rate,
 401         .recalc_rate    = clk_rpm_recalc_rate,
 402 };
 403
 404 DEFINE_CLK_RPM(afab, QCOM_RPM_APPS_FABRIC_CLK);
 405 DEFINE_CLK_RPM(sfab, QCOM_RPM_SYS_FABRIC_CLK);
 406 DEFINE_CLK_RPM(mmfab, QCOM_RPM_MM_FABRIC_CLK);
 407 DEFINE_CLK_RPM(daytona, QCOM_RPM_DAYTONA_FABRIC_CLK);
 408 DEFINE_CLK_RPM(sfpb, QCOM_RPM_SFPB_CLK);
 409 DEFINE_CLK_RPM(cfpb, QCOM_RPM_CFPB_CLK);
 410 DEFINE_CLK_RPM(mmfpb, QCOM_RPM_MMFPB_CLK);
 411 DEFINE_CLK_RPM(smi, QCOM_RPM_SMI_CLK);
 412 DEFINE_CLK_RPM(ebi1, QCOM_RPM_EBI1_CLK);
 413
 414 DEFINE_CLK_RPM(qdss, QCOM_RPM_QDSS_CLK);
 415 DEFINE_CLK_RPM(nss_fabric_0, QCOM_RPM_NSS_FABRIC_0_CLK);
 416 DEFINE_CLK_RPM(nss_fabric_1, QCOM_RPM_NSS_FABRIC_1_CLK);
 417
 418 DEFINE_CLK_RPM_FIXED(pll4, QCOM_RPM_PLL_4, 540672000);
 419
 420 DEFINE_CLK_RPM_XO_BUFFER(xo_d0, 0);
 421 DEFINE_CLK_RPM_XO_BUFFER(xo_d1, 8);
 422 DEFINE_CLK_RPM_XO_BUFFER(xo_a0, 16);
 423 DEFINE_CLK_RPM_XO_BUFFER(xo_a1, 24);
 424 DEFINE_CLK_RPM_XO_BUFFER(xo_a2, 28);
 425
 426 static struct clk_rpm *msm8660_clks[] = {
 427         [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
 428         [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
 429         [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
 430         [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
 431         [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
 432         [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
 433         [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
 434         [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
 435         [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
 436         [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
 437         [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
 438         [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
 439         [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
 440         [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
 441         [RPM_SMI_CLK] = &clk_rpm_smi_clk,
 442         [RPM_SMI_A_CLK] = &clk_rpm_smi_a_clk,
 443         [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
 444         [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
 445         [RPM_PLL4_CLK] = &clk_rpm_pll4_clk,
 446 };
 447
 448 static const struct rpm_clk_desc rpm_clk_msm8660 = {
 449         .clks = msm8660_clks,
 450         .num_clks = ARRAY_SIZE(msm8660_clks),
 451 };
 452
 453 static struct clk_rpm *apq8064_clks[] = {
 454         [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
 455         [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
 456         [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
 457         [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
 458         [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
 459         [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
 460         [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
 461         [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
 462         [RPM_MM_FABRIC_CLK] = &clk_rpm_mmfab_clk,
 463         [RPM_MM_FABRIC_A_CLK] = &clk_rpm_mmfab_a_clk,
 464         [RPM_MMFPB_CLK] = &clk_rpm_mmfpb_clk,
 465         [RPM_MMFPB_A_CLK] = &clk_rpm_mmfpb_a_clk,
 466         [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
 467         [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
 468         [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
 469         [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
 470         [RPM_QDSS_CLK] = &clk_rpm_qdss_clk,
 471         [RPM_QDSS_A_CLK] = &clk_rpm_qdss_a_clk,
 472         [RPM_XO_D0] = &clk_rpm_xo_d0_clk,
 473         [RPM_XO_D1] = &clk_rpm_xo_d1_clk,
 474         [RPM_XO_A0] = &clk_rpm_xo_a0_clk,
 475         [RPM_XO_A1] = &clk_rpm_xo_a1_clk,
 476         [RPM_XO_A2] = &clk_rpm_xo_a2_clk,
 477 };
 478
 479 static const struct rpm_clk_desc rpm_clk_apq8064 = {
 480         .clks = apq8064_clks,
 481         .num_clks = ARRAY_SIZE(apq8064_clks),
 482 };
 483
 484 static struct clk_rpm *ipq806x_clks[] = {
 485         [RPM_APPS_FABRIC_CLK] = &clk_rpm_afab_clk,
 486         [RPM_APPS_FABRIC_A_CLK] = &clk_rpm_afab_a_clk,
 487         [RPM_CFPB_CLK] = &clk_rpm_cfpb_clk,
 488         [RPM_CFPB_A_CLK] = &clk_rpm_cfpb_a_clk,
 489         [RPM_DAYTONA_FABRIC_CLK] = &clk_rpm_daytona_clk,
 490         [RPM_DAYTONA_FABRIC_A_CLK] = &clk_rpm_daytona_a_clk,
 491         [RPM_EBI1_CLK] = &clk_rpm_ebi1_clk,
 492         [RPM_EBI1_A_CLK] = &clk_rpm_ebi1_a_clk,
 493         [RPM_SYS_FABRIC_CLK] = &clk_rpm_sfab_clk,
 494         [RPM_SYS_FABRIC_A_CLK] = &clk_rpm_sfab_a_clk,
 495         [RPM_SFPB_CLK] = &clk_rpm_sfpb_clk,
 496         [RPM_SFPB_A_CLK] = &clk_rpm_sfpb_a_clk,
 497         [RPM_NSS_FABRIC_0_CLK] = &clk_rpm_nss_fabric_0_clk,
 498         [RPM_NSS_FABRIC_0_A_CLK] = &clk_rpm_nss_fabric_0_a_clk,
 499         [RPM_NSS_FABRIC_1_CLK] = &clk_rpm_nss_fabric_1_clk,
 500         [RPM_NSS_FABRIC_1_A_CLK] = &clk_rpm_nss_fabric_1_a_clk,
 501 };
 502
 503 static const struct rpm_clk_desc rpm_clk_ipq806x = {
 504         .clks = ipq806x_clks,
 505         .num_clks = ARRAY_SIZE(ipq806x_clks),
 506 };
 507
 508 static const struct of_device_id rpm_clk_match_table[] = {
 509         { .compatible = "qcom,rpmcc-msm8660", .data = &rpm_clk_msm8660 },
 510         { .compatible = "qcom,rpmcc-apq8060", .data = &rpm_clk_msm8660 },
 511         { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
 512         { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
 513         { }
 514 };
 515 MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
 516
 517 static struct clk_hw *qcom_rpm_clk_hw_get(struct of_phandle_args *clkspec,
 518                                           void *data)
 519 {
 520         struct rpm_cc *rcc = data;
 521         unsigned int idx = clkspec->args[0];
 522
 523         if (idx >= rcc->num_clks) {
 524                 pr_err("%s: invalid index %u\n", __func__, idx);
 525                 return ERR_PTR(-EINVAL);
 526         }
 527
 528         return rcc->clks[idx] ? &rcc->clks[idx]->hw : ERR_PTR(-ENOENT);
 529 }
 530
 531 static int rpm_clk_probe(struct platform_device *pdev)
 532 {
 533         struct rpm_cc *rcc;
 534         int ret;
 535         size_t num_clks, i;
 536         struct qcom_rpm *rpm;
 537         struct clk_rpm **rpm_clks;
 538         const struct rpm_clk_desc *desc;
 539
 540         rpm = dev_get_drvdata(pdev->dev.parent);
 541         if (!rpm) {
 542                 dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
 543                 return -ENODEV;
 544         }
 545
 546         desc = of_device_get_match_data(&pdev->dev);
 547         if (!desc)
 548                 return -EINVAL;
 549
 550         rpm_clks = desc->clks;
 551         num_clks = desc->num_clks;
 552
 553         rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc), GFP_KERNEL);
 554         if (!rcc)
 555                 return -ENOMEM;
 556
 557         rcc->clks = rpm_clks;
 558         rcc->num_clks = num_clks;
 559         mutex_init(&rcc->xo_lock);
 560
 561         for (i = 0; i < num_clks; i++) {
 562                 if (!rpm_clks[i])
 563                         continue;
 564
 565                 rpm_clks[i]->rpm = rpm;
 566                 rpm_clks[i]->rpm_cc = rcc;
 567
 568                 ret = clk_rpm_handoff(rpm_clks[i]);
 569                 if (ret)
 570                         goto err;
 571         }
 572
 573         for (i = 0; i < num_clks; i++) {
 574                 if (!rpm_clks[i])
 575                         continue;
 576
 577                 ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
 578                 if (ret)
 579                         goto err;
 580         }
 581
 582         ret = devm_of_clk_add_hw_provider(&pdev->dev, qcom_rpm_clk_hw_get,
 583                                           rcc);
 584         if (ret)
 585                 goto err;
 586
 587         return 0;
 588 err:
 589         dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
 590         return ret;
 591 }
 592
 593 static struct platform_driver rpm_clk_driver = {
 594         .driver = {
 595                 .name = "qcom-clk-rpm",
 596                 .of_match_table = rpm_clk_match_table,
 597         },
 598         .probe = rpm_clk_probe,
 599 };
 600
 601 static int __init rpm_clk_init(void)
 602 {
 603         return platform_driver_register(&rpm_clk_driver);
 604 }
 605 core_initcall(rpm_clk_init);
 606
 607 static void __exit rpm_clk_exit(void)
 608 {
 609         platform_driver_unregister(&rpm_clk_driver);
 610 }
 611 module_exit(rpm_clk_exit);
 612
 613 MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
 614 MODULE_LICENSE("GPL v2");
 615 MODULE_ALIAS("platform:qcom-clk-rpm");