1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013, 2018, The Linux Foundation. All rights reserved.
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
10 #include <linux/export.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/rational.h>
14 #include <linux/regmap.h>
15 #include <linux/math64.h>
16 #include <linux/slab.h>
18 #include <asm/div64.h>
24 #define CMD_UPDATE BIT(0)
25 #define CMD_ROOT_EN BIT(1)
26 #define CMD_DIRTY_CFG BIT(4)
27 #define CMD_DIRTY_N BIT(5)
28 #define CMD_DIRTY_M BIT(6)
29 #define CMD_DIRTY_D BIT(7)
30 #define CMD_ROOT_OFF BIT(31)
33 #define CFG_SRC_DIV_SHIFT 0
34 #define CFG_SRC_SEL_SHIFT 8
35 #define CFG_SRC_SEL_MASK (0x7 << CFG_SRC_SEL_SHIFT)
36 #define CFG_MODE_SHIFT 12
37 #define CFG_MODE_MASK (0x3 << CFG_MODE_SHIFT)
38 #define CFG_MODE_DUAL_EDGE (0x2 << CFG_MODE_SHIFT)
39 #define CFG_HW_CLK_CTRL_MASK BIT(20)
45 #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG)
46 #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG)
47 #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG)
48 #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG)
50 /* Dynamic Frequency Scaling */
51 #define MAX_PERF_LEVEL 8
52 #define SE_CMD_DFSR_OFFSET 0x14
53 #define SE_CMD_DFS_EN BIT(0)
54 #define SE_PERF_DFSR(level) (0x1c + 0x4 * (level))
55 #define SE_PERF_M_DFSR(level) (0x5c + 0x4 * (level))
56 #define SE_PERF_N_DFSR(level) (0x9c + 0x4 * (level))
63 static int clk_rcg2_is_enabled(struct clk_hw *hw)
65 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
69 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
73 return (cmd & CMD_ROOT_OFF) == 0;
76 static u8 clk_rcg2_get_parent(struct clk_hw *hw)
78 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
79 int num_parents = clk_hw_get_num_parents(hw);
83 ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
87 cfg &= CFG_SRC_SEL_MASK;
88 cfg >>= CFG_SRC_SEL_SHIFT;
90 for (i = 0; i < num_parents; i++)
91 if (cfg == rcg->parent_map[i].cfg)
95 pr_debug("%s: Clock %s has invalid parent, using default.\n",
96 __func__, clk_hw_get_name(hw));
100 static int update_config(struct clk_rcg2 *rcg)
104 struct clk_hw *hw = &rcg->clkr.hw;
105 const char *name = clk_hw_get_name(hw);
107 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
108 CMD_UPDATE, CMD_UPDATE);
112 /* Wait for update to take effect */
113 for (count = 500; count > 0; count--) {
114 ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd);
117 if (!(cmd & CMD_UPDATE))
122 WARN(1, "%s: rcg didn't update its configuration.", name);
126 static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
128 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
130 u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
132 ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
133 CFG_SRC_SEL_MASK, cfg);
137 return update_config(rcg);
141 * Calculate m/n:d rate
144 * rate = ----------- x ---
148 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
166 clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
168 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
169 u32 cfg, hid_div, m = 0, n = 0, mode = 0, mask;
171 regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
173 if (rcg->mnd_width) {
174 mask = BIT(rcg->mnd_width) - 1;
175 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
177 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n);
181 mode = cfg & CFG_MODE_MASK;
182 mode >>= CFG_MODE_SHIFT;
185 mask = BIT(rcg->hid_width) - 1;
186 hid_div = cfg >> CFG_SRC_DIV_SHIFT;
189 return calc_rate(parent_rate, m, n, mode, hid_div);
192 static int _freq_tbl_determine_rate(struct clk_hw *hw, const struct freq_tbl *f,
193 struct clk_rate_request *req,
194 enum freq_policy policy)
196 unsigned long clk_flags, rate = req->rate;
198 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
203 f = qcom_find_freq_floor(f, rate);
206 f = qcom_find_freq(f, rate);
215 index = qcom_find_src_index(hw, rcg->parent_map, f->src);
219 clk_flags = clk_hw_get_flags(hw);
220 p = clk_hw_get_parent_by_index(hw, index);
224 if (clk_flags & CLK_SET_RATE_PARENT) {
230 rate *= f->pre_div + 1;
240 rate = clk_hw_get_rate(p);
242 req->best_parent_hw = p;
243 req->best_parent_rate = rate;
249 static int clk_rcg2_determine_rate(struct clk_hw *hw,
250 struct clk_rate_request *req)
252 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
254 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL);
257 static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,
258 struct clk_rate_request *req)
260 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
262 return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR);
265 static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
268 struct clk_hw *hw = &rcg->clkr.hw;
269 int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);
274 if (rcg->mnd_width && f->n) {
275 mask = BIT(rcg->mnd_width) - 1;
276 ret = regmap_update_bits(rcg->clkr.regmap,
277 RCG_M_OFFSET(rcg), mask, f->m);
281 ret = regmap_update_bits(rcg->clkr.regmap,
282 RCG_N_OFFSET(rcg), mask, ~(f->n - f->m));
286 ret = regmap_update_bits(rcg->clkr.regmap,
287 RCG_D_OFFSET(rcg), mask, ~f->n);
292 mask = BIT(rcg->hid_width) - 1;
293 mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK | CFG_HW_CLK_CTRL_MASK;
294 cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
295 cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
296 if (rcg->mnd_width && f->n && (f->m != f->n))
297 cfg |= CFG_MODE_DUAL_EDGE;
298 return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg),
302 static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
306 ret = __clk_rcg2_configure(rcg, f);
310 return update_config(rcg);
313 static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
314 enum freq_policy policy)
316 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
317 const struct freq_tbl *f;
321 f = qcom_find_freq_floor(rcg->freq_tbl, rate);
324 f = qcom_find_freq(rcg->freq_tbl, rate);
333 return clk_rcg2_configure(rcg, f);
336 static int clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate,
337 unsigned long parent_rate)
339 return __clk_rcg2_set_rate(hw, rate, CEIL);
342 static int clk_rcg2_set_floor_rate(struct clk_hw *hw, unsigned long rate,
343 unsigned long parent_rate)
345 return __clk_rcg2_set_rate(hw, rate, FLOOR);
348 static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
349 unsigned long rate, unsigned long parent_rate, u8 index)
351 return __clk_rcg2_set_rate(hw, rate, CEIL);
354 static int clk_rcg2_set_floor_rate_and_parent(struct clk_hw *hw,
355 unsigned long rate, unsigned long parent_rate, u8 index)
357 return __clk_rcg2_set_rate(hw, rate, FLOOR);
360 static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
362 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
363 u32 notn_m, n, m, d, not2d, mask;
365 if (!rcg->mnd_width) {
366 /* 50 % duty-cycle for Non-MND RCGs */
372 regmap_read(rcg->clkr.regmap, RCG_D_OFFSET(rcg), ¬2d);
373 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
374 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
376 if (!not2d && !m && !notn_m) {
377 /* 50 % duty-cycle always */
383 mask = BIT(rcg->mnd_width) - 1;
386 d = DIV_ROUND_CLOSEST(d, 2);
388 n = (~(notn_m) + m) & mask;
396 static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
398 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
399 u32 notn_m, n, m, d, not2d, mask, duty_per;
402 /* Duty-cycle cannot be modified for non-MND RCGs */
406 mask = BIT(rcg->mnd_width) - 1;
408 regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
409 regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
411 n = (~(notn_m) + m) & mask;
413 duty_per = (duty->num * 100) / duty->den;
415 /* Calculate 2d value */
416 d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
418 /* Check bit widths of 2d. If D is too big reduce duty cycle. */
422 if ((d / 2) > (n - m))
424 else if ((d / 2) < (m / 2))
429 ret = regmap_update_bits(rcg->clkr.regmap, RCG_D_OFFSET(rcg), mask,
434 return update_config(rcg);
437 const struct clk_ops clk_rcg2_ops = {
438 .is_enabled = clk_rcg2_is_enabled,
439 .get_parent = clk_rcg2_get_parent,
440 .set_parent = clk_rcg2_set_parent,
441 .recalc_rate = clk_rcg2_recalc_rate,
442 .determine_rate = clk_rcg2_determine_rate,
443 .set_rate = clk_rcg2_set_rate,
444 .set_rate_and_parent = clk_rcg2_set_rate_and_parent,
445 .get_duty_cycle = clk_rcg2_get_duty_cycle,
446 .set_duty_cycle = clk_rcg2_set_duty_cycle,
448 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
450 const struct clk_ops clk_rcg2_floor_ops = {
451 .is_enabled = clk_rcg2_is_enabled,
452 .get_parent = clk_rcg2_get_parent,
453 .set_parent = clk_rcg2_set_parent,
454 .recalc_rate = clk_rcg2_recalc_rate,
455 .determine_rate = clk_rcg2_determine_floor_rate,
456 .set_rate = clk_rcg2_set_floor_rate,
457 .set_rate_and_parent = clk_rcg2_set_floor_rate_and_parent,
458 .get_duty_cycle = clk_rcg2_get_duty_cycle,
459 .set_duty_cycle = clk_rcg2_set_duty_cycle,
461 EXPORT_SYMBOL_GPL(clk_rcg2_floor_ops);
468 static const struct frac_entry frac_table_675m[] = { /* link rate of 270M */
469 { 52, 295 }, /* 119 M */
470 { 11, 57 }, /* 130.25 M */
471 { 63, 307 }, /* 138.50 M */
472 { 11, 50 }, /* 148.50 M */
473 { 47, 206 }, /* 154 M */
474 { 31, 100 }, /* 205.25 M */
475 { 107, 269 }, /* 268.50 M */
479 static struct frac_entry frac_table_810m[] = { /* Link rate of 162M */
480 { 31, 211 }, /* 119 M */
481 { 32, 199 }, /* 130.25 M */
482 { 63, 307 }, /* 138.50 M */
483 { 11, 60 }, /* 148.50 M */
484 { 50, 263 }, /* 154 M */
485 { 31, 120 }, /* 205.25 M */
486 { 119, 359 }, /* 268.50 M */
490 static int clk_edp_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
491 unsigned long parent_rate)
493 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
494 struct freq_tbl f = *rcg->freq_tbl;
495 const struct frac_entry *frac;
497 s64 src_rate = parent_rate;
499 u32 mask = BIT(rcg->hid_width) - 1;
502 if (src_rate == 810000000)
503 frac = frac_table_810m;
505 frac = frac_table_675m;
507 for (; frac->num; frac++) {
509 request *= frac->den;
510 request = div_s64(request, frac->num);
511 if ((src_rate < (request - delta)) ||
512 (src_rate > (request + delta)))
515 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
518 f.pre_div >>= CFG_SRC_DIV_SHIFT;
523 return clk_rcg2_configure(rcg, &f);
529 static int clk_edp_pixel_set_rate_and_parent(struct clk_hw *hw,
530 unsigned long rate, unsigned long parent_rate, u8 index)
532 /* Parent index is set statically in frequency table */
533 return clk_edp_pixel_set_rate(hw, rate, parent_rate);
536 static int clk_edp_pixel_determine_rate(struct clk_hw *hw,
537 struct clk_rate_request *req)
539 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
540 const struct freq_tbl *f = rcg->freq_tbl;
541 const struct frac_entry *frac;
544 u32 mask = BIT(rcg->hid_width) - 1;
546 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
548 /* Force the correct parent */
549 req->best_parent_hw = clk_hw_get_parent_by_index(hw, index);
550 req->best_parent_rate = clk_hw_get_rate(req->best_parent_hw);
552 if (req->best_parent_rate == 810000000)
553 frac = frac_table_810m;
555 frac = frac_table_675m;
557 for (; frac->num; frac++) {
559 request *= frac->den;
560 request = div_s64(request, frac->num);
561 if ((req->best_parent_rate < (request - delta)) ||
562 (req->best_parent_rate > (request + delta)))
565 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
567 hid_div >>= CFG_SRC_DIV_SHIFT;
570 req->rate = calc_rate(req->best_parent_rate,
571 frac->num, frac->den,
572 !!frac->den, hid_div);
579 const struct clk_ops clk_edp_pixel_ops = {
580 .is_enabled = clk_rcg2_is_enabled,
581 .get_parent = clk_rcg2_get_parent,
582 .set_parent = clk_rcg2_set_parent,
583 .recalc_rate = clk_rcg2_recalc_rate,
584 .set_rate = clk_edp_pixel_set_rate,
585 .set_rate_and_parent = clk_edp_pixel_set_rate_and_parent,
586 .determine_rate = clk_edp_pixel_determine_rate,
588 EXPORT_SYMBOL_GPL(clk_edp_pixel_ops);
590 static int clk_byte_determine_rate(struct clk_hw *hw,
591 struct clk_rate_request *req)
593 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
594 const struct freq_tbl *f = rcg->freq_tbl;
595 int index = qcom_find_src_index(hw, rcg->parent_map, f->src);
596 unsigned long parent_rate, div;
597 u32 mask = BIT(rcg->hid_width) - 1;
603 req->best_parent_hw = p = clk_hw_get_parent_by_index(hw, index);
604 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, req->rate);
606 div = DIV_ROUND_UP((2 * parent_rate), req->rate) - 1;
607 div = min_t(u32, div, mask);
609 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
614 static int clk_byte_set_rate(struct clk_hw *hw, unsigned long rate,
615 unsigned long parent_rate)
617 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
618 struct freq_tbl f = *rcg->freq_tbl;
620 u32 mask = BIT(rcg->hid_width) - 1;
622 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
623 div = min_t(u32, div, mask);
627 return clk_rcg2_configure(rcg, &f);
630 static int clk_byte_set_rate_and_parent(struct clk_hw *hw,
631 unsigned long rate, unsigned long parent_rate, u8 index)
633 /* Parent index is set statically in frequency table */
634 return clk_byte_set_rate(hw, rate, parent_rate);
637 const struct clk_ops clk_byte_ops = {
638 .is_enabled = clk_rcg2_is_enabled,
639 .get_parent = clk_rcg2_get_parent,
640 .set_parent = clk_rcg2_set_parent,
641 .recalc_rate = clk_rcg2_recalc_rate,
642 .set_rate = clk_byte_set_rate,
643 .set_rate_and_parent = clk_byte_set_rate_and_parent,
644 .determine_rate = clk_byte_determine_rate,
646 EXPORT_SYMBOL_GPL(clk_byte_ops);
648 static int clk_byte2_determine_rate(struct clk_hw *hw,
649 struct clk_rate_request *req)
651 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
652 unsigned long parent_rate, div;
653 u32 mask = BIT(rcg->hid_width) - 1;
655 unsigned long rate = req->rate;
660 p = req->best_parent_hw;
661 req->best_parent_rate = parent_rate = clk_hw_round_rate(p, rate);
663 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
664 div = min_t(u32, div, mask);
666 req->rate = calc_rate(parent_rate, 0, 0, 0, div);
671 static int clk_byte2_set_rate(struct clk_hw *hw, unsigned long rate,
672 unsigned long parent_rate)
674 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
675 struct freq_tbl f = { 0 };
677 int i, num_parents = clk_hw_get_num_parents(hw);
678 u32 mask = BIT(rcg->hid_width) - 1;
681 div = DIV_ROUND_UP((2 * parent_rate), rate) - 1;
682 div = min_t(u32, div, mask);
686 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
687 cfg &= CFG_SRC_SEL_MASK;
688 cfg >>= CFG_SRC_SEL_SHIFT;
690 for (i = 0; i < num_parents; i++) {
691 if (cfg == rcg->parent_map[i].cfg) {
692 f.src = rcg->parent_map[i].src;
693 return clk_rcg2_configure(rcg, &f);
700 static int clk_byte2_set_rate_and_parent(struct clk_hw *hw,
701 unsigned long rate, unsigned long parent_rate, u8 index)
703 /* Read the hardware to determine parent during set_rate */
704 return clk_byte2_set_rate(hw, rate, parent_rate);
707 const struct clk_ops clk_byte2_ops = {
708 .is_enabled = clk_rcg2_is_enabled,
709 .get_parent = clk_rcg2_get_parent,
710 .set_parent = clk_rcg2_set_parent,
711 .recalc_rate = clk_rcg2_recalc_rate,
712 .set_rate = clk_byte2_set_rate,
713 .set_rate_and_parent = clk_byte2_set_rate_and_parent,
714 .determine_rate = clk_byte2_determine_rate,
716 EXPORT_SYMBOL_GPL(clk_byte2_ops);
718 static const struct frac_entry frac_table_pixel[] = {
726 static int clk_pixel_determine_rate(struct clk_hw *hw,
727 struct clk_rate_request *req)
729 unsigned long request, src_rate;
731 const struct frac_entry *frac = frac_table_pixel;
733 for (; frac->num; frac++) {
734 request = (req->rate * frac->den) / frac->num;
736 src_rate = clk_hw_round_rate(req->best_parent_hw, request);
737 if ((src_rate < (request - delta)) ||
738 (src_rate > (request + delta)))
741 req->best_parent_rate = src_rate;
742 req->rate = (src_rate * frac->num) / frac->den;
749 static int clk_pixel_set_rate(struct clk_hw *hw, unsigned long rate,
750 unsigned long parent_rate)
752 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
753 struct freq_tbl f = { 0 };
754 const struct frac_entry *frac = frac_table_pixel;
755 unsigned long request;
757 u32 mask = BIT(rcg->hid_width) - 1;
759 int i, num_parents = clk_hw_get_num_parents(hw);
761 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
762 cfg &= CFG_SRC_SEL_MASK;
763 cfg >>= CFG_SRC_SEL_SHIFT;
765 for (i = 0; i < num_parents; i++)
766 if (cfg == rcg->parent_map[i].cfg) {
767 f.src = rcg->parent_map[i].src;
771 for (; frac->num; frac++) {
772 request = (rate * frac->den) / frac->num;
774 if ((parent_rate < (request - delta)) ||
775 (parent_rate > (request + delta)))
778 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
781 f.pre_div >>= CFG_SRC_DIV_SHIFT;
786 return clk_rcg2_configure(rcg, &f);
791 static int clk_pixel_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
792 unsigned long parent_rate, u8 index)
794 return clk_pixel_set_rate(hw, rate, parent_rate);
797 const struct clk_ops clk_pixel_ops = {
798 .is_enabled = clk_rcg2_is_enabled,
799 .get_parent = clk_rcg2_get_parent,
800 .set_parent = clk_rcg2_set_parent,
801 .recalc_rate = clk_rcg2_recalc_rate,
802 .set_rate = clk_pixel_set_rate,
803 .set_rate_and_parent = clk_pixel_set_rate_and_parent,
804 .determine_rate = clk_pixel_determine_rate,
806 EXPORT_SYMBOL_GPL(clk_pixel_ops);
808 static int clk_gfx3d_determine_rate(struct clk_hw *hw,
809 struct clk_rate_request *req)
811 struct clk_rate_request parent_req = { };
812 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
813 struct clk_hw *xo, *p0, *p1, *p2;
814 unsigned long p0_rate;
815 u8 mux_div = cgfx->div;
822 * This function does ping-pong the RCG between PLLs: if we don't
823 * have at least one fixed PLL and two variable ones,
824 * then it's not going to work correctly.
826 if (WARN_ON(!p0 || !p1 || !p2))
829 xo = clk_hw_get_parent_by_index(hw, 0);
830 if (req->rate == clk_hw_get_rate(xo)) {
831 req->best_parent_hw = xo;
838 parent_req.rate = req->rate * mux_div;
840 /* This has to be a fixed rate PLL */
841 p0_rate = clk_hw_get_rate(p0);
843 if (parent_req.rate == p0_rate) {
844 req->rate = req->best_parent_rate = p0_rate;
845 req->best_parent_hw = p0;
849 if (req->best_parent_hw == p0) {
850 /* Are we going back to a previously used rate? */
851 if (clk_hw_get_rate(p2) == parent_req.rate)
852 req->best_parent_hw = p2;
854 req->best_parent_hw = p1;
855 } else if (req->best_parent_hw == p2) {
856 req->best_parent_hw = p1;
858 req->best_parent_hw = p2;
861 ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
865 req->rate = req->best_parent_rate = parent_req.rate;
866 req->rate /= mux_div;
871 static int clk_gfx3d_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
872 unsigned long parent_rate, u8 index)
874 struct clk_rcg2_gfx3d *cgfx = to_clk_rcg2_gfx3d(hw);
875 struct clk_rcg2 *rcg = &cgfx->rcg;
879 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
880 /* On some targets, the GFX3D RCG may need to divide PLL frequency */
882 cfg |= ((2 * cgfx->div) - 1) << CFG_SRC_DIV_SHIFT;
884 ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
888 return update_config(rcg);
891 static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
892 unsigned long parent_rate)
895 * We should never get here; clk_gfx3d_determine_rate() should always
896 * make us use a different parent than what we're currently using, so
897 * clk_gfx3d_set_rate_and_parent() should always be called.
902 const struct clk_ops clk_gfx3d_ops = {
903 .is_enabled = clk_rcg2_is_enabled,
904 .get_parent = clk_rcg2_get_parent,
905 .set_parent = clk_rcg2_set_parent,
906 .recalc_rate = clk_rcg2_recalc_rate,
907 .set_rate = clk_gfx3d_set_rate,
908 .set_rate_and_parent = clk_gfx3d_set_rate_and_parent,
909 .determine_rate = clk_gfx3d_determine_rate,
911 EXPORT_SYMBOL_GPL(clk_gfx3d_ops);
913 static int clk_rcg2_set_force_enable(struct clk_hw *hw)
915 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
916 const char *name = clk_hw_get_name(hw);
919 ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
920 CMD_ROOT_EN, CMD_ROOT_EN);
924 /* wait for RCG to turn ON */
925 for (count = 500; count > 0; count--) {
926 if (clk_rcg2_is_enabled(hw))
932 pr_err("%s: RCG did not turn on\n", name);
936 static int clk_rcg2_clear_force_enable(struct clk_hw *hw)
938 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
940 return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
945 clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f)
947 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
950 ret = clk_rcg2_set_force_enable(hw);
954 ret = clk_rcg2_configure(rcg, f);
958 return clk_rcg2_clear_force_enable(hw);
961 static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
962 unsigned long parent_rate)
964 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
965 const struct freq_tbl *f;
967 f = qcom_find_freq(rcg->freq_tbl, rate);
972 * In case clock is disabled, update the CFG, M, N and D registers
973 * and don't hit the update bit of CMD register.
975 if (!__clk_is_enabled(hw->clk))
976 return __clk_rcg2_configure(rcg, f);
978 return clk_rcg2_shared_force_enable_clear(hw, f);
981 static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,
982 unsigned long rate, unsigned long parent_rate, u8 index)
984 return clk_rcg2_shared_set_rate(hw, rate, parent_rate);
987 static int clk_rcg2_shared_enable(struct clk_hw *hw)
989 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
993 * Set the update bit because required configuration has already
994 * been written in clk_rcg2_shared_set_rate()
996 ret = clk_rcg2_set_force_enable(hw);
1000 ret = update_config(rcg);
1004 return clk_rcg2_clear_force_enable(hw);
1007 static void clk_rcg2_shared_disable(struct clk_hw *hw)
1009 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1013 * Store current configuration as switching to safe source would clear
1014 * the SRC and DIV of CFG register
1016 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
1019 * Park the RCG at a safe configuration - sourced off of safe source.
1020 * Force enable and disable the RCG while configuring it to safeguard
1021 * against any update signal coming from the downstream clock.
1022 * The current parent is still prepared and enabled at this point, and
1023 * the safe source is always on while application processor subsystem
1024 * is online. Therefore, the RCG can safely switch its parent.
1026 clk_rcg2_set_force_enable(hw);
1028 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
1029 rcg->safe_src_index << CFG_SRC_SEL_SHIFT);
1033 clk_rcg2_clear_force_enable(hw);
1035 /* Write back the stored configuration corresponding to current rate */
1036 regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg);
1039 const struct clk_ops clk_rcg2_shared_ops = {
1040 .enable = clk_rcg2_shared_enable,
1041 .disable = clk_rcg2_shared_disable,
1042 .get_parent = clk_rcg2_get_parent,
1043 .set_parent = clk_rcg2_set_parent,
1044 .recalc_rate = clk_rcg2_recalc_rate,
1045 .determine_rate = clk_rcg2_determine_rate,
1046 .set_rate = clk_rcg2_shared_set_rate,
1047 .set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
1049 EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
1051 /* Common APIs to be used for DFS based RCGR */
1052 static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
1055 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1057 unsigned long prate = 0;
1058 u32 val, mask, cfg, mode, src;
1061 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg);
1063 mask = BIT(rcg->hid_width) - 1;
1066 f->pre_div = cfg & mask;
1068 src = cfg & CFG_SRC_SEL_MASK;
1069 src >>= CFG_SRC_SEL_SHIFT;
1071 num_parents = clk_hw_get_num_parents(hw);
1072 for (i = 0; i < num_parents; i++) {
1073 if (src == rcg->parent_map[i].cfg) {
1074 f->src = rcg->parent_map[i].src;
1075 p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i);
1076 prate = clk_hw_get_rate(p);
1080 mode = cfg & CFG_MODE_MASK;
1081 mode >>= CFG_MODE_SHIFT;
1083 mask = BIT(rcg->mnd_width) - 1;
1084 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l),
1089 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l),
1097 f->freq = calc_rate(prate, f->m, f->n, mode, f->pre_div);
1100 static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg)
1102 struct freq_tbl *freq_tbl;
1105 /* Allocate space for 1 extra since table is NULL terminated */
1106 freq_tbl = kcalloc(MAX_PERF_LEVEL + 1, sizeof(*freq_tbl), GFP_KERNEL);
1109 rcg->freq_tbl = freq_tbl;
1111 for (i = 0; i < MAX_PERF_LEVEL; i++)
1112 clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i);
1117 static int clk_rcg2_dfs_determine_rate(struct clk_hw *hw,
1118 struct clk_rate_request *req)
1120 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1123 if (!rcg->freq_tbl) {
1124 ret = clk_rcg2_dfs_populate_freq_table(rcg);
1126 pr_err("Failed to update DFS tables for %s\n",
1127 clk_hw_get_name(hw));
1132 return clk_rcg2_determine_rate(hw, req);
1135 static unsigned long
1136 clk_rcg2_dfs_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1138 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1139 u32 level, mask, cfg, m = 0, n = 0, mode, pre_div;
1141 regmap_read(rcg->clkr.regmap,
1142 rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level);
1143 level &= GENMASK(4, 1);
1147 return rcg->freq_tbl[level].freq;
1150 * Assume that parent_rate is actually the parent because
1151 * we can't do any better at figuring it out when the table
1152 * hasn't been populated yet. We only populate the table
1153 * in determine_rate because we can't guarantee the parents
1154 * will be registered with the framework until then.
1156 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level),
1159 mask = BIT(rcg->hid_width) - 1;
1162 pre_div = cfg & mask;
1164 mode = cfg & CFG_MODE_MASK;
1165 mode >>= CFG_MODE_SHIFT;
1167 mask = BIT(rcg->mnd_width) - 1;
1168 regmap_read(rcg->clkr.regmap,
1169 rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m);
1172 regmap_read(rcg->clkr.regmap,
1173 rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n);
1179 return calc_rate(parent_rate, m, n, mode, pre_div);
1182 static const struct clk_ops clk_rcg2_dfs_ops = {
1183 .is_enabled = clk_rcg2_is_enabled,
1184 .get_parent = clk_rcg2_get_parent,
1185 .determine_rate = clk_rcg2_dfs_determine_rate,
1186 .recalc_rate = clk_rcg2_dfs_recalc_rate,
1189 static int clk_rcg2_enable_dfs(const struct clk_rcg_dfs_data *data,
1190 struct regmap *regmap)
1192 struct clk_rcg2 *rcg = data->rcg;
1193 struct clk_init_data *init = data->init;
1197 ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val);
1201 if (!(val & SE_CMD_DFS_EN))
1205 * Rate changes with consumer writing a register in
1206 * their own I/O region
1208 init->flags |= CLK_GET_RATE_NOCACHE;
1209 init->ops = &clk_rcg2_dfs_ops;
1211 rcg->freq_tbl = NULL;
1216 int qcom_cc_register_rcg_dfs(struct regmap *regmap,
1217 const struct clk_rcg_dfs_data *rcgs, size_t len)
1221 for (i = 0; i < len; i++) {
1222 ret = clk_rcg2_enable_dfs(&rcgs[i], regmap);
1229 EXPORT_SYMBOL_GPL(qcom_cc_register_rcg_dfs);
1231 static int clk_rcg2_dp_set_rate(struct clk_hw *hw, unsigned long rate,
1232 unsigned long parent_rate)
1234 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1235 struct freq_tbl f = { 0 };
1236 u32 mask = BIT(rcg->hid_width) - 1;
1238 int i, num_parents = clk_hw_get_num_parents(hw);
1239 unsigned long num, den;
1241 rational_best_approximation(parent_rate, rate,
1242 GENMASK(rcg->mnd_width - 1, 0),
1243 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1248 regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
1250 cfg &= CFG_SRC_SEL_MASK;
1251 cfg >>= CFG_SRC_SEL_SHIFT;
1253 for (i = 0; i < num_parents; i++) {
1254 if (cfg == rcg->parent_map[i].cfg) {
1255 f.src = rcg->parent_map[i].src;
1260 f.pre_div = hid_div;
1261 f.pre_div >>= CFG_SRC_DIV_SHIFT;
1272 return clk_rcg2_configure(rcg, &f);
1275 static int clk_rcg2_dp_set_rate_and_parent(struct clk_hw *hw,
1276 unsigned long rate, unsigned long parent_rate, u8 index)
1278 return clk_rcg2_dp_set_rate(hw, rate, parent_rate);
1281 static int clk_rcg2_dp_determine_rate(struct clk_hw *hw,
1282 struct clk_rate_request *req)
1284 struct clk_rcg2 *rcg = to_clk_rcg2(hw);
1285 unsigned long num, den;
1288 /* Parent rate is a fixed phy link rate */
1289 rational_best_approximation(req->best_parent_rate, req->rate,
1290 GENMASK(rcg->mnd_width - 1, 0),
1291 GENMASK(rcg->mnd_width - 1, 0), &den, &num);
1296 tmp = req->best_parent_rate * num;
1303 const struct clk_ops clk_dp_ops = {
1304 .is_enabled = clk_rcg2_is_enabled,
1305 .get_parent = clk_rcg2_get_parent,
1306 .set_parent = clk_rcg2_set_parent,
1307 .recalc_rate = clk_rcg2_recalc_rate,
1308 .set_rate = clk_rcg2_dp_set_rate,
1309 .set_rate_and_parent = clk_rcg2_dp_set_rate_and_parent,
1310 .determine_rate = clk_rcg2_dp_determine_rate,
1312 EXPORT_SYMBOL_GPL(clk_dp_ops);