2 * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #ifndef __QCOM_CLK_ALPHA_PLL_H__
15 #define __QCOM_CLK_ALPHA_PLL_H__
17 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
22 CLK_ALPHA_PLL_TYPE_DEFAULT,
23 CLK_ALPHA_PLL_TYPE_HUAYRA,
24 CLK_ALPHA_PLL_TYPE_BRAMMO,
25 CLK_ALPHA_PLL_TYPE_FABIA,
26 CLK_ALPHA_PLL_TYPE_MAX,
45 extern const u8 clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_MAX][PLL_OFF_MAX_REGS];
48 unsigned long min_freq;
49 unsigned long max_freq;
54 * struct clk_alpha_pll - phase locked loop (PLL)
55 * @offset: base address of registers
56 * @vco_table: array of VCO settings
57 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
58 * @clkr: regmap clock handle
60 struct clk_alpha_pll {
64 const struct pll_vco *vco_table;
66 #define SUPPORTS_OFFLINE_REQ BIT(0)
67 #define SUPPORTS_FSM_MODE BIT(2)
68 #define SUPPORTS_DYNAMIC_UPDATE BIT(3)
71 struct clk_regmap clkr;
75 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider
76 * @offset: base address of registers
77 * @regs: alpha pll register map (see @clk_alpha_pll_regs)
78 * @width: width of post-divider
79 * @post_div_shift: shift to differentiate between odd & even post-divider
80 * @post_div_table: table with PLL odd and even post-divider settings
81 * @num_post_div: Number of PLL post-divider settings
83 * @clkr: regmap clock handle
85 struct clk_alpha_pll_postdiv {
90 struct clk_regmap clkr;
92 const struct clk_div_table *post_div_table;
96 struct alpha_pll_config {
101 u32 config_ctl_hi_val;
102 u32 main_output_mask;
104 u32 aux2_output_mask;
105 u32 early_output_mask;
116 extern const struct clk_ops clk_alpha_pll_ops;
117 extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
118 extern const struct clk_ops clk_alpha_pll_postdiv_ops;
119 extern const struct clk_ops clk_alpha_pll_huayra_ops;
120 extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
122 extern const struct clk_ops clk_alpha_pll_fabia_ops;
123 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
124 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
126 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
127 const struct alpha_pll_config *config);
128 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
129 const struct alpha_pll_config *config);