drivers/clk/qcom/clk-alpha-pll.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015, 2018, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/export.h>
   9 #include <linux/clk-provider.h>
  10 #include <linux/regmap.h>
  11 #include <linux/delay.h>
  12
  13 #include "clk-alpha-pll.h"
  14 #include "common.h"
  15
  16 #define PLL_MODE(p)             ((p)->offset + 0x0)
  17 # define PLL_OUTCTRL            BIT(0)
  18 # define PLL_BYPASSNL           BIT(1)
  19 # define PLL_RESET_N            BIT(2)
  20 # define PLL_OFFLINE_REQ        BIT(7)
  21 # define PLL_LOCK_COUNT_SHIFT   8
  22 # define PLL_LOCK_COUNT_MASK    0x3f
  23 # define PLL_BIAS_COUNT_SHIFT   14
  24 # define PLL_BIAS_COUNT_MASK    0x3f
  25 # define PLL_VOTE_FSM_ENA       BIT(20)
  26 # define PLL_FSM_ENA            BIT(20)
  27 # define PLL_VOTE_FSM_RESET     BIT(21)
  28 # define PLL_UPDATE             BIT(22)
  29 # define PLL_UPDATE_BYPASS      BIT(23)
  30 # define PLL_OFFLINE_ACK        BIT(28)
  31 # define ALPHA_PLL_ACK_LATCH    BIT(29)
  32 # define PLL_ACTIVE_FLAG        BIT(30)
  33 # define PLL_LOCK_DET           BIT(31)
  34
  35 #define PLL_L_VAL(p)            ((p)->offset + (p)->regs[PLL_OFF_L_VAL])
  36 #define PLL_CAL_L_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_CAL_L_VAL])
  37 #define PLL_ALPHA_VAL(p)        ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL])
  38 #define PLL_ALPHA_VAL_U(p)      ((p)->offset + (p)->regs[PLL_OFF_ALPHA_VAL_U])
  39
  40 #define PLL_USER_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
  41 # define PLL_POST_DIV_SHIFT     8
  42 # define PLL_POST_DIV_MASK(p)   GENMASK((p)->width, 0)
  43 # define PLL_ALPHA_EN           BIT(24)
  44 # define PLL_ALPHA_MODE         BIT(25)
  45 # define PLL_VCO_SHIFT          20
  46 # define PLL_VCO_MASK           0x3
  47
  48 #define PLL_USER_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U])
  49 #define PLL_USER_CTL_U1(p)      ((p)->offset + (p)->regs[PLL_OFF_USER_CTL_U1])
  50
  51 #define PLL_CONFIG_CTL(p)       ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL])
  52 #define PLL_CONFIG_CTL_U(p)     ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U])
  53 #define PLL_CONFIG_CTL_U1(p)    ((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
  54 #define PLL_TEST_CTL(p)         ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
  55 #define PLL_TEST_CTL_U(p)       ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
  56 #define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
  57 #define PLL_STATUS(p)           ((p)->offset + (p)->regs[PLL_OFF_STATUS])
  58 #define PLL_OPMODE(p)           ((p)->offset + (p)->regs[PLL_OFF_OPMODE])
  59 #define PLL_FRAC(p)             ((p)->offset + (p)->regs[PLL_OFF_FRAC])
  60
  61 const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
  62         [CLK_ALPHA_PLL_TYPE_DEFAULT] =  {
  63                 [PLL_OFF_L_VAL] = 0x04,
  64                 [PLL_OFF_ALPHA_VAL] = 0x08,
  65                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  66                 [PLL_OFF_USER_CTL] = 0x10,
  67                 [PLL_OFF_USER_CTL_U] = 0x14,
  68                 [PLL_OFF_CONFIG_CTL] = 0x18,
  69                 [PLL_OFF_TEST_CTL] = 0x1c,
  70                 [PLL_OFF_TEST_CTL_U] = 0x20,
  71                 [PLL_OFF_STATUS] = 0x24,
  72         },
  73         [CLK_ALPHA_PLL_TYPE_HUAYRA] =  {
  74                 [PLL_OFF_L_VAL] = 0x04,
  75                 [PLL_OFF_ALPHA_VAL] = 0x08,
  76                 [PLL_OFF_USER_CTL] = 0x10,
  77                 [PLL_OFF_CONFIG_CTL] = 0x14,
  78                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  79                 [PLL_OFF_TEST_CTL] = 0x1c,
  80                 [PLL_OFF_TEST_CTL_U] = 0x20,
  81                 [PLL_OFF_STATUS] = 0x24,
  82         },
  83         [CLK_ALPHA_PLL_TYPE_BRAMMO] =  {
  84                 [PLL_OFF_L_VAL] = 0x04,
  85                 [PLL_OFF_ALPHA_VAL] = 0x08,
  86                 [PLL_OFF_ALPHA_VAL_U] = 0x0c,
  87                 [PLL_OFF_USER_CTL] = 0x10,
  88                 [PLL_OFF_CONFIG_CTL] = 0x18,
  89                 [PLL_OFF_TEST_CTL] = 0x1c,
  90                 [PLL_OFF_STATUS] = 0x24,
  91         },
  92         [CLK_ALPHA_PLL_TYPE_FABIA] =  {
  93                 [PLL_OFF_L_VAL] = 0x04,
  94                 [PLL_OFF_USER_CTL] = 0x0c,
  95                 [PLL_OFF_USER_CTL_U] = 0x10,
  96                 [PLL_OFF_CONFIG_CTL] = 0x14,
  97                 [PLL_OFF_CONFIG_CTL_U] = 0x18,
  98                 [PLL_OFF_TEST_CTL] = 0x1c,
  99                 [PLL_OFF_TEST_CTL_U] = 0x20,
 100                 [PLL_OFF_STATUS] = 0x24,
 101                 [PLL_OFF_OPMODE] = 0x2c,
 102                 [PLL_OFF_FRAC] = 0x38,
 103         },
 104         [CLK_ALPHA_PLL_TYPE_TRION] = {
 105                 [PLL_OFF_L_VAL] = 0x04,
 106                 [PLL_OFF_CAL_L_VAL] = 0x08,
 107                 [PLL_OFF_USER_CTL] = 0x0c,
 108                 [PLL_OFF_USER_CTL_U] = 0x10,
 109                 [PLL_OFF_USER_CTL_U1] = 0x14,
 110                 [PLL_OFF_CONFIG_CTL] = 0x18,
 111                 [PLL_OFF_CONFIG_CTL_U] = 0x1c,
 112                 [PLL_OFF_CONFIG_CTL_U1] = 0x20,
 113                 [PLL_OFF_TEST_CTL] = 0x24,
 114                 [PLL_OFF_TEST_CTL_U] = 0x28,
 115                 [PLL_OFF_TEST_CTL_U1] = 0x2c,
 116                 [PLL_OFF_STATUS] = 0x30,
 117                 [PLL_OFF_OPMODE] = 0x38,
 118                 [PLL_OFF_ALPHA_VAL] = 0x40,
 119         },
 120         [CLK_ALPHA_PLL_TYPE_AGERA] =  {
 121                 [PLL_OFF_L_VAL] = 0x04,
 122                 [PLL_OFF_ALPHA_VAL] = 0x08,
 123                 [PLL_OFF_USER_CTL] = 0x0c,
 124                 [PLL_OFF_CONFIG_CTL] = 0x10,
 125                 [PLL_OFF_CONFIG_CTL_U] = 0x14,
 126                 [PLL_OFF_TEST_CTL] = 0x18,
 127                 [PLL_OFF_TEST_CTL_U] = 0x1c,
 128                 [PLL_OFF_STATUS] = 0x2c,
 129         },
 130         [CLK_ALPHA_PLL_TYPE_ZONDA] =  {
 131                 [PLL_OFF_L_VAL] = 0x04,
 132                 [PLL_OFF_ALPHA_VAL] = 0x08,
 133                 [PLL_OFF_USER_CTL] = 0x0c,
 134                 [PLL_OFF_CONFIG_CTL] = 0x10,
 135                 [PLL_OFF_CONFIG_CTL_U] = 0x14,
 136                 [PLL_OFF_CONFIG_CTL_U1] = 0x18,
 137                 [PLL_OFF_TEST_CTL] = 0x1c,
 138                 [PLL_OFF_TEST_CTL_U] = 0x20,
 139                 [PLL_OFF_TEST_CTL_U1] = 0x24,
 140                 [PLL_OFF_OPMODE] = 0x28,
 141                 [PLL_OFF_STATUS] = 0x38,
 142         },
 143         [CLK_ALPHA_PLL_TYPE_LUCID_EVO] = {
 144                 [PLL_OFF_OPMODE] = 0x04,
 145                 [PLL_OFF_STATUS] = 0x0c,
 146                 [PLL_OFF_L_VAL] = 0x10,
 147                 [PLL_OFF_ALPHA_VAL] = 0x14,
 148                 [PLL_OFF_USER_CTL] = 0x18,
 149                 [PLL_OFF_USER_CTL_U] = 0x1c,
 150                 [PLL_OFF_CONFIG_CTL] = 0x20,
 151                 [PLL_OFF_CONFIG_CTL_U] = 0x24,
 152                 [PLL_OFF_CONFIG_CTL_U1] = 0x28,
 153                 [PLL_OFF_TEST_CTL] = 0x2c,
 154                 [PLL_OFF_TEST_CTL_U] = 0x30,
 155                 [PLL_OFF_TEST_CTL_U1] = 0x34,
 156         },
 157 };
 158 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 159
 160 /*
 161  * Even though 40 bits are present, use only 32 for ease of calculation.
 162  */
 163 #define ALPHA_REG_BITWIDTH      40
 164 #define ALPHA_REG_16BIT_WIDTH   16
 165 #define ALPHA_BITWIDTH          32U
 166 #define ALPHA_SHIFT(w)          min(w, ALPHA_BITWIDTH)
 167
 168 #define PLL_HUAYRA_M_WIDTH              8
 169 #define PLL_HUAYRA_M_SHIFT              8
 170 #define PLL_HUAYRA_M_MASK               0xff
 171 #define PLL_HUAYRA_N_SHIFT              0
 172 #define PLL_HUAYRA_N_MASK               0xff
 173 #define PLL_HUAYRA_ALPHA_WIDTH          16
 174
 175 #define PLL_STANDBY             0x0
 176 #define PLL_RUN                 0x1
 177 #define PLL_OUT_MASK            0x7
 178 #define PLL_RATE_MARGIN         500
 179
 180 /* TRION PLL specific settings and offsets */
 181 #define TRION_PLL_CAL_VAL       0x44
 182 #define TRION_PCAL_DONE         BIT(26)
 183
 184 /* LUCID PLL specific settings and offsets */
 185 #define LUCID_PCAL_DONE         BIT(27)
 186
 187 /* LUCID 5LPE PLL specific settings and offsets */
 188 #define LUCID_5LPE_PCAL_DONE            BIT(11)
 189 #define LUCID_5LPE_ALPHA_PLL_ACK_LATCH  BIT(13)
 190 #define LUCID_5LPE_PLL_LATCH_INPUT      BIT(14)
 191 #define LUCID_5LPE_ENABLE_VOTE_RUN      BIT(21)
 192
 193 /* LUCID EVO PLL specific settings and offsets */
 194 #define LUCID_EVO_ENABLE_VOTE_RUN       BIT(25)
 195 #define LUCID_EVO_PLL_L_VAL_MASK        GENMASK(15, 0)
 196
 197 /* ZONDA PLL specific */
 198 #define ZONDA_PLL_OUT_MASK      0xf
 199 #define ZONDA_STAY_IN_CFA       BIT(16)
 200 #define ZONDA_PLL_FREQ_LOCK_DET BIT(29)
 201
 202 #define pll_alpha_width(p)                                      \
 203                 ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
 204                                  ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
 205
 206 #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4)
 207
 208 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
 209                                            struct clk_alpha_pll, clkr)
 210
 211 #define to_clk_alpha_pll_postdiv(_hw) container_of(to_clk_regmap(_hw), \
 212                                            struct clk_alpha_pll_postdiv, clkr)
 213
 214 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 215                         const char *action)
 216 {
 217         u32 val;
 218         int count;
 219         int ret;
 220         const char *name = clk_hw_get_name(&pll->clkr.hw);
 221
 222         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 223         if (ret)
 224                 return ret;
 225
 226         for (count = 200; count > 0; count--) {
 227                 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 228                 if (ret)
 229                         return ret;
 230                 if (inverse && !(val & mask))
 231                         return 0;
 232                 else if ((val & mask) == mask)
 233                         return 0;
 234
 235                 udelay(1);
 236         }
 237
 238         WARN(1, "%s failed to %s!\n", name, action);
 239         return -ETIMEDOUT;
 240 }
 241
 242 #define wait_for_pll_enable_active(pll) \
 243         wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
 244
 245 #define wait_for_pll_enable_lock(pll) \
 246         wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")
 247
 248 #define wait_for_zonda_pll_freq_lock(pll) \
 249         wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")
 250
 251 #define wait_for_pll_disable(pll) \
 252         wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")
 253
 254 #define wait_for_pll_offline(pll) \
 255         wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 256
 257 #define wait_for_pll_update(pll) \
 258         wait_for_pll(pll, PLL_UPDATE, 1, "update")
 259
 260 #define wait_for_pll_update_ack_set(pll) \
 261         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 0, "update_ack_set")
 262
 263 #define wait_for_pll_update_ack_clear(pll) \
 264         wait_for_pll(pll, ALPHA_PLL_ACK_LATCH, 1, "update_ack_clear")
 265
 266 static void clk_alpha_pll_write_config(struct regmap *regmap, unsigned int reg,
 267                                         unsigned int val)
 268 {
 269         if (val)
 270                 regmap_write(regmap, reg, val);
 271 }
 272
 273 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 274                              const struct alpha_pll_config *config)
 275 {
 276         u32 val, mask;
 277
 278         regmap_write(regmap, PLL_L_VAL(pll), config->l);
 279         regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
 280         regmap_write(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
 281
 282         if (pll_has_64bit_config(pll))
 283                 regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
 284                              config->config_ctl_hi_val);
 285
 286         if (pll_alpha_width(pll) > 32)
 287                 regmap_write(regmap, PLL_ALPHA_VAL_U(pll), config->alpha_hi);
 288
 289         val = config->main_output_mask;
 290         val |= config->aux_output_mask;
 291         val |= config->aux2_output_mask;
 292         val |= config->early_output_mask;
 293         val |= config->pre_div_val;
 294         val |= config->post_div_val;
 295         val |= config->vco_val;
 296         val |= config->alpha_en_mask;
 297         val |= config->alpha_mode_mask;
 298
 299         mask = config->main_output_mask;
 300         mask |= config->aux_output_mask;
 301         mask |= config->aux2_output_mask;
 302         mask |= config->early_output_mask;
 303         mask |= config->pre_div_mask;
 304         mask |= config->post_div_mask;
 305         mask |= config->vco_mask;
 306
 307         regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
 308
 309         if (pll->flags & SUPPORTS_FSM_MODE)
 310                 qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
 311 }
 312 EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
 313
 314 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 315 {
 316         int ret;
 317         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 318         u32 val;
 319
 320         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 321         if (ret)
 322                 return ret;
 323
 324         val |= PLL_FSM_ENA;
 325
 326         if (pll->flags & SUPPORTS_OFFLINE_REQ)
 327                 val &= ~PLL_OFFLINE_REQ;
 328
 329         ret = regmap_write(pll->clkr.regmap, PLL_MODE(pll), val);
 330         if (ret)
 331                 return ret;
 332
 333         /* Make sure enable request goes through before waiting for update */
 334         mb();
 335
 336         return wait_for_pll_enable_active(pll);
 337 }
 338
 339 static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
 340 {
 341         int ret;
 342         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 343         u32 val;
 344
 345         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 346         if (ret)
 347                 return;
 348
 349         if (pll->flags & SUPPORTS_OFFLINE_REQ) {
 350                 ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 351                                          PLL_OFFLINE_REQ, PLL_OFFLINE_REQ);
 352                 if (ret)
 353                         return;
 354
 355                 ret = wait_for_pll_offline(pll);
 356                 if (ret)
 357                         return;
 358         }
 359
 360         /* Disable hwfsm */
 361         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 362                                  PLL_FSM_ENA, 0);
 363         if (ret)
 364                 return;
 365
 366         wait_for_pll_disable(pll);
 367 }
 368
 369 static int pll_is_enabled(struct clk_hw *hw, u32 mask)
 370 {
 371         int ret;
 372         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 373         u32 val;
 374
 375         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 376         if (ret)
 377                 return ret;
 378
 379         return !!(val & mask);
 380 }
 381
 382 static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
 383 {
 384         return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
 385 }
 386
 387 static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
 388 {
 389         return pll_is_enabled(hw, PLL_LOCK_DET);
 390 }
 391
 392 static int clk_alpha_pll_enable(struct clk_hw *hw)
 393 {
 394         int ret;
 395         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 396         u32 val, mask;
 397
 398         mask = PLL_OUTCTRL | PLL_RESET_N | PLL_BYPASSNL;
 399         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 400         if (ret)
 401                 return ret;
 402
 403         /* If in FSM mode, just vote for it */
 404         if (val & PLL_VOTE_FSM_ENA) {
 405                 ret = clk_enable_regmap(hw);
 406                 if (ret)
 407                         return ret;
 408                 return wait_for_pll_enable_active(pll);
 409         }
 410
 411         /* Skip if already enabled */
 412         if ((val & mask) == mask)
 413                 return 0;
 414
 415         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 416                                  PLL_BYPASSNL, PLL_BYPASSNL);
 417         if (ret)
 418                 return ret;
 419
 420         /*
 421          * H/W requires a 5us delay between disabling the bypass and
 422          * de-asserting the reset.
 423          */
 424         mb();
 425         udelay(5);
 426
 427         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 428                                  PLL_RESET_N, PLL_RESET_N);
 429         if (ret)
 430                 return ret;
 431
 432         ret = wait_for_pll_enable_lock(pll);
 433         if (ret)
 434                 return ret;
 435
 436         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
 437                                  PLL_OUTCTRL, PLL_OUTCTRL);
 438
 439         /* Ensure that the write above goes through before returning. */
 440         mb();
 441         return ret;
 442 }
 443
 444 static void clk_alpha_pll_disable(struct clk_hw *hw)
 445 {
 446         int ret;
 447         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 448         u32 val, mask;
 449
 450         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
 451         if (ret)
 452                 return;
 453
 454         /* If in FSM mode, just unvote it */
 455         if (val & PLL_VOTE_FSM_ENA) {
 456                 clk_disable_regmap(hw);
 457                 return;
 458         }
 459
 460         mask = PLL_OUTCTRL;
 461         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 462
 463         /* Delay of 2 output clock ticks required until output is disabled */
 464         mb();
 465         udelay(1);
 466
 467         mask = PLL_RESET_N | PLL_BYPASSNL;
 468         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), mask, 0);
 469 }
 470
 471 static unsigned long
 472 alpha_pll_calc_rate(u64 prate, u32 l, u32 a, u32 alpha_width)
 473 {
 474         return (prate * l) + ((prate * a) >> ALPHA_SHIFT(alpha_width));
 475 }
 476
 477 static unsigned long
 478 alpha_pll_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a,
 479                      u32 alpha_width)
 480 {
 481         u64 remainder;
 482         u64 quotient;
 483
 484         quotient = rate;
 485         remainder = do_div(quotient, prate);
 486         *l = quotient;
 487
 488         if (!remainder) {
 489                 *a = 0;
 490                 return rate;
 491         }
 492
 493         /* Upper ALPHA_BITWIDTH bits of Alpha */
 494         quotient = remainder << ALPHA_SHIFT(alpha_width);
 495
 496         remainder = do_div(quotient, prate);
 497
 498         if (remainder)
 499                 quotient++;
 500
 501         *a = quotient;
 502         return alpha_pll_calc_rate(prate, *l, *a, alpha_width);
 503 }
 504
 505 static const struct pll_vco *
 506 alpha_pll_find_vco(const struct clk_alpha_pll *pll, unsigned long rate)
 507 {
 508         const struct pll_vco *v = pll->vco_table;
 509         const struct pll_vco *end = v + pll->num_vco;
 510
 511         for (; v < end; v++)
 512                 if (rate >= v->min_freq && rate <= v->max_freq)
 513                         return v;
 514
 515         return NULL;
 516 }
 517
 518 static unsigned long
 519 clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 520 {
 521         u32 l, low, high, ctl;
 522         u64 a = 0, prate = parent_rate;
 523         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 524         u32 alpha_width = pll_alpha_width(pll);
 525
 526         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 527
 528         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 529         if (ctl & PLL_ALPHA_EN) {
 530                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
 531                 if (alpha_width > 32) {
 532                         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
 533                                     &high);
 534                         a = (u64)high << 32 | low;
 535                 } else {
 536                         a = low & GENMASK(alpha_width - 1, 0);
 537                 }
 538
 539                 if (alpha_width > ALPHA_BITWIDTH)
 540                         a >>= alpha_width - ALPHA_BITWIDTH;
 541         }
 542
 543         return alpha_pll_calc_rate(prate, l, a, alpha_width);
 544 }
 545
 546
 547 static int __clk_alpha_pll_update_latch(struct clk_alpha_pll *pll)
 548 {
 549         int ret;
 550         u32 mode;
 551
 552         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &mode);
 553
 554         /* Latch the input to the PLL */
 555         regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
 556                            PLL_UPDATE);
 557
 558         /* Wait for 2 reference cycle before checking ACK bit */
 559         udelay(1);
 560
 561         /*
 562          * PLL will latch the new L, Alpha and freq control word.
 563          * PLL will respond by raising PLL_ACK_LATCH output when new programming
 564          * has been latched in and PLL is being updated. When
 565          * UPDATE_LOGIC_BYPASS bit is not set, PLL_UPDATE will be cleared
 566          * automatically by hardware when PLL_ACK_LATCH is asserted by PLL.
 567          */
 568         if (mode & PLL_UPDATE_BYPASS) {
 569                 ret = wait_for_pll_update_ack_set(pll);
 570                 if (ret)
 571                         return ret;
 572
 573                 regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, 0);
 574         } else {
 575                 ret = wait_for_pll_update(pll);
 576                 if (ret)
 577                         return ret;
 578         }
 579
 580         ret = wait_for_pll_update_ack_clear(pll);
 581         if (ret)
 582                 return ret;
 583
 584         /* Wait for PLL output to stabilize */
 585         udelay(10);
 586
 587         return 0;
 588 }
 589
 590 static int clk_alpha_pll_update_latch(struct clk_alpha_pll *pll,
 591                                       int (*is_enabled)(struct clk_hw *))
 592 {
 593         if (!is_enabled(&pll->clkr.hw) ||
 594             !(pll->flags & SUPPORTS_DYNAMIC_UPDATE))
 595                 return 0;
 596
 597         return __clk_alpha_pll_update_latch(pll);
 598 }
 599
 600 static int __clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 601                                     unsigned long prate,
 602                                     int (*is_enabled)(struct clk_hw *))
 603 {
 604         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 605         const struct pll_vco *vco;
 606         u32 l, alpha_width = pll_alpha_width(pll);
 607         u64 a;
 608
 609         rate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 610         vco = alpha_pll_find_vco(pll, rate);
 611         if (pll->vco_table && !vco) {
 612                 pr_err("%s: alpha pll not in a valid vco range\n",
 613                        clk_hw_get_name(hw));
 614                 return -EINVAL;
 615         }
 616
 617         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 618
 619         if (alpha_width > ALPHA_BITWIDTH)
 620                 a <<= alpha_width - ALPHA_BITWIDTH;
 621
 622         if (alpha_width > 32)
 623                 regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), a >> 32);
 624
 625         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 626
 627         if (vco) {
 628                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 629                                    PLL_VCO_MASK << PLL_VCO_SHIFT,
 630                                    vco->val << PLL_VCO_SHIFT);
 631         }
 632
 633         regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 634                            PLL_ALPHA_EN, PLL_ALPHA_EN);
 635
 636         return clk_alpha_pll_update_latch(pll, is_enabled);
 637 }
 638
 639 static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 640                                   unsigned long prate)
 641 {
 642         return __clk_alpha_pll_set_rate(hw, rate, prate,
 643                                         clk_alpha_pll_is_enabled);
 644 }
 645
 646 static int clk_alpha_pll_hwfsm_set_rate(struct clk_hw *hw, unsigned long rate,
 647                                         unsigned long prate)
 648 {
 649         return __clk_alpha_pll_set_rate(hw, rate, prate,
 650                                         clk_alpha_pll_hwfsm_is_enabled);
 651 }
 652
 653 static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 654                                      unsigned long *prate)
 655 {
 656         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 657         u32 l, alpha_width = pll_alpha_width(pll);
 658         u64 a;
 659         unsigned long min_freq, max_freq;
 660
 661         rate = alpha_pll_round_rate(rate, *prate, &l, &a, alpha_width);
 662         if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
 663                 return rate;
 664
 665         min_freq = pll->vco_table[0].min_freq;
 666         max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
 667
 668         return clamp(rate, min_freq, max_freq);
 669 }
 670
 671 static unsigned long
 672 alpha_huayra_pll_calc_rate(u64 prate, u32 l, u32 a)
 673 {
 674         /*
 675          * a contains 16 bit alpha_val in two’s complement number in the range
 676          * of [-0.5, 0.5).
 677          */
 678         if (a >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 679                 l -= 1;
 680
 681         return (prate * l) + (prate * a >> PLL_HUAYRA_ALPHA_WIDTH);
 682 }
 683
 684 static unsigned long
 685 alpha_huayra_pll_round_rate(unsigned long rate, unsigned long prate,
 686                             u32 *l, u32 *a)
 687 {
 688         u64 remainder;
 689         u64 quotient;
 690
 691         quotient = rate;
 692         remainder = do_div(quotient, prate);
 693         *l = quotient;
 694
 695         if (!remainder) {
 696                 *a = 0;
 697                 return rate;
 698         }
 699
 700         quotient = remainder << PLL_HUAYRA_ALPHA_WIDTH;
 701         remainder = do_div(quotient, prate);
 702
 703         if (remainder)
 704                 quotient++;
 705
 706         /*
 707          * alpha_val should be in two’s complement number in the range
 708          * of [-0.5, 0.5) so if quotient >= 0.5 then increment the l value
 709          * since alpha value will be subtracted in this case.
 710          */
 711         if (quotient >= BIT(PLL_HUAYRA_ALPHA_WIDTH - 1))
 712                 *l += 1;
 713
 714         *a = quotient;
 715         return alpha_huayra_pll_calc_rate(prate, *l, *a);
 716 }
 717
 718 static unsigned long
 719 alpha_pll_huayra_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 720 {
 721         u64 rate = parent_rate, tmp;
 722         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 723         u32 l, alpha = 0, ctl, alpha_m, alpha_n;
 724
 725         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 726         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 727
 728         if (ctl & PLL_ALPHA_EN) {
 729                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &alpha);
 730                 /*
 731                  * Depending upon alpha_mode, it can be treated as M/N value or
 732                  * as a two’s complement number. When alpha_mode=1,
 733                  * pll_alpha_val<15:8>=M and pll_apla_val<7:0>=N
 734                  *
 735                  *              Fout=FIN*(L+(M/N))
 736                  *
 737                  * M is a signed number (-128 to 127) and N is unsigned
 738                  * (0 to 255). M/N has to be within +/-0.5.
 739                  *
 740                  * When alpha_mode=0, it is a two’s complement number in the
 741                  * range [-0.5, 0.5).
 742                  *
 743                  *              Fout=FIN*(L+(alpha_val)/2^16)
 744                  *
 745                  * where alpha_val is two’s complement number.
 746                  */
 747                 if (!(ctl & PLL_ALPHA_MODE))
 748                         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 749
 750                 alpha_m = alpha >> PLL_HUAYRA_M_SHIFT & PLL_HUAYRA_M_MASK;
 751                 alpha_n = alpha >> PLL_HUAYRA_N_SHIFT & PLL_HUAYRA_N_MASK;
 752
 753                 rate *= l;
 754                 tmp = parent_rate;
 755                 if (alpha_m >= BIT(PLL_HUAYRA_M_WIDTH - 1)) {
 756                         alpha_m = BIT(PLL_HUAYRA_M_WIDTH) - alpha_m;
 757                         tmp *= alpha_m;
 758                         do_div(tmp, alpha_n);
 759                         rate -= tmp;
 760                 } else {
 761                         tmp *= alpha_m;
 762                         do_div(tmp, alpha_n);
 763                         rate += tmp;
 764                 }
 765
 766                 return rate;
 767         }
 768
 769         return alpha_huayra_pll_calc_rate(rate, l, alpha);
 770 }
 771
 772 static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 773                                      unsigned long prate)
 774 {
 775         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 776         u32 l, a, ctl, cur_alpha = 0;
 777
 778         rate = alpha_huayra_pll_round_rate(rate, prate, &l, &a);
 779
 780         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 781
 782         if (ctl & PLL_ALPHA_EN)
 783                 regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &cur_alpha);
 784
 785         /*
 786          * Huayra PLL supports PLL dynamic programming. User can change L_VAL,
 787          * without having to go through the power on sequence.
 788          */
 789         if (clk_alpha_pll_is_enabled(hw)) {
 790                 if (cur_alpha != a) {
 791                         pr_err("%s: clock needs to be gated\n",
 792                                clk_hw_get_name(hw));
 793                         return -EBUSY;
 794                 }
 795
 796                 regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 797                 /* Ensure that the write above goes to detect L val change. */
 798                 mb();
 799                 return wait_for_pll_enable_lock(pll);
 800         }
 801
 802         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
 803         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
 804
 805         if (a == 0)
 806                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 807                                    PLL_ALPHA_EN, 0x0);
 808         else
 809                 regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
 810                                    PLL_ALPHA_EN | PLL_ALPHA_MODE, PLL_ALPHA_EN);
 811
 812         return 0;
 813 }
 814
 815 static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
 816                                         unsigned long *prate)
 817 {
 818         u32 l, a;
 819
 820         return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
 821 }
 822
 823 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
 824                                 struct regmap *regmap)
 825 {
 826         u32 mode_val, opmode_val;
 827         int ret;
 828
 829         ret = regmap_read(regmap, PLL_MODE(pll), &mode_val);
 830         ret |= regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
 831         if (ret)
 832                 return 0;
 833
 834         return ((opmode_val & PLL_RUN) && (mode_val & PLL_OUTCTRL));
 835 }
 836
 837 static int clk_trion_pll_is_enabled(struct clk_hw *hw)
 838 {
 839         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 840
 841         return trion_pll_is_enabled(pll, pll->clkr.regmap);
 842 }
 843
 844 static int clk_trion_pll_enable(struct clk_hw *hw)
 845 {
 846         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 847         struct regmap *regmap = pll->clkr.regmap;
 848         u32 val;
 849         int ret;
 850
 851         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 852         if (ret)
 853                 return ret;
 854
 855         /* If in FSM mode, just vote for it */
 856         if (val & PLL_VOTE_FSM_ENA) {
 857                 ret = clk_enable_regmap(hw);
 858                 if (ret)
 859                         return ret;
 860                 return wait_for_pll_enable_active(pll);
 861         }
 862
 863         /* Set operation mode to RUN */
 864         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 865
 866         ret = wait_for_pll_enable_lock(pll);
 867         if (ret)
 868                 return ret;
 869
 870         /* Enable the PLL outputs */
 871         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 872                                  PLL_OUT_MASK, PLL_OUT_MASK);
 873         if (ret)
 874                 return ret;
 875
 876         /* Enable the global PLL outputs */
 877         return regmap_update_bits(regmap, PLL_MODE(pll),
 878                                  PLL_OUTCTRL, PLL_OUTCTRL);
 879 }
 880
 881 static void clk_trion_pll_disable(struct clk_hw *hw)
 882 {
 883         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 884         struct regmap *regmap = pll->clkr.regmap;
 885         u32 val;
 886         int ret;
 887
 888         ret = regmap_read(regmap, PLL_MODE(pll), &val);
 889         if (ret)
 890                 return;
 891
 892         /* If in FSM mode, just unvote it */
 893         if (val & PLL_VOTE_FSM_ENA) {
 894                 clk_disable_regmap(hw);
 895                 return;
 896         }
 897
 898         /* Disable the global PLL output */
 899         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
 900         if (ret)
 901                 return;
 902
 903         /* Disable the PLL outputs */
 904         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
 905                                  PLL_OUT_MASK, 0);
 906         if (ret)
 907                 return;
 908
 909         /* Place the PLL mode in STANDBY */
 910         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 911         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 912 }
 913
 914 static unsigned long
 915 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 916 {
 917         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 918         u32 l, frac, alpha_width = pll_alpha_width(pll);
 919
 920         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
 921         regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
 922
 923         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
 924 }
 925
 926 const struct clk_ops clk_alpha_pll_fixed_ops = {
 927         .enable = clk_alpha_pll_enable,
 928         .disable = clk_alpha_pll_disable,
 929         .is_enabled = clk_alpha_pll_is_enabled,
 930         .recalc_rate = clk_alpha_pll_recalc_rate,
 931 };
 932 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_ops);
 933
 934 const struct clk_ops clk_alpha_pll_ops = {
 935         .enable = clk_alpha_pll_enable,
 936         .disable = clk_alpha_pll_disable,
 937         .is_enabled = clk_alpha_pll_is_enabled,
 938         .recalc_rate = clk_alpha_pll_recalc_rate,
 939         .round_rate = clk_alpha_pll_round_rate,
 940         .set_rate = clk_alpha_pll_set_rate,
 941 };
 942 EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 943
 944 const struct clk_ops clk_alpha_pll_huayra_ops = {
 945         .enable = clk_alpha_pll_enable,
 946         .disable = clk_alpha_pll_disable,
 947         .is_enabled = clk_alpha_pll_is_enabled,
 948         .recalc_rate = alpha_pll_huayra_recalc_rate,
 949         .round_rate = alpha_pll_huayra_round_rate,
 950         .set_rate = alpha_pll_huayra_set_rate,
 951 };
 952 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
 953
 954 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
 955         .enable = clk_alpha_pll_hwfsm_enable,
 956         .disable = clk_alpha_pll_hwfsm_disable,
 957         .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
 958         .recalc_rate = clk_alpha_pll_recalc_rate,
 959         .round_rate = clk_alpha_pll_round_rate,
 960         .set_rate = clk_alpha_pll_hwfsm_set_rate,
 961 };
 962 EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
 963
 964 const struct clk_ops clk_alpha_pll_fixed_trion_ops = {
 965         .enable = clk_trion_pll_enable,
 966         .disable = clk_trion_pll_disable,
 967         .is_enabled = clk_trion_pll_is_enabled,
 968         .recalc_rate = clk_trion_pll_recalc_rate,
 969         .round_rate = clk_alpha_pll_round_rate,
 970 };
 971 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_trion_ops);
 972
 973 static unsigned long
 974 clk_alpha_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 975 {
 976         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
 977         u32 ctl;
 978
 979         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
 980
 981         ctl >>= PLL_POST_DIV_SHIFT;
 982         ctl &= PLL_POST_DIV_MASK(pll);
 983
 984         return parent_rate >> fls(ctl);
 985 }
 986
 987 static const struct clk_div_table clk_alpha_div_table[] = {
 988         { 0x0, 1 },
 989         { 0x1, 2 },
 990         { 0x3, 4 },
 991         { 0x7, 8 },
 992         { 0xf, 16 },
 993         { }
 994 };
 995
 996 static const struct clk_div_table clk_alpha_2bit_div_table[] = {
 997         { 0x0, 1 },
 998         { 0x1, 2 },
 999         { 0x3, 4 },
1000         { }
1001 };
1002
1003 static long
1004 clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1005                                  unsigned long *prate)
1006 {
1007         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1008         const struct clk_div_table *table;
1009
1010         if (pll->width == 2)
1011                 table = clk_alpha_2bit_div_table;
1012         else
1013                 table = clk_alpha_div_table;
1014
1015         return divider_round_rate(hw, rate, prate, table,
1016                                   pll->width, CLK_DIVIDER_POWER_OF_TWO);
1017 }
1018
1019 static long
1020 clk_alpha_pll_postdiv_round_ro_rate(struct clk_hw *hw, unsigned long rate,
1021                                     unsigned long *prate)
1022 {
1023         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1024         u32 ctl, div;
1025
1026         regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
1027
1028         ctl >>= PLL_POST_DIV_SHIFT;
1029         ctl &= BIT(pll->width) - 1;
1030         div = 1 << fls(ctl);
1031
1032         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)
1033                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), div * rate);
1034
1035         return DIV_ROUND_UP_ULL((u64)*prate, div);
1036 }
1037
1038 static int clk_alpha_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1039                                           unsigned long parent_rate)
1040 {
1041         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1042         int div;
1043
1044         /* 16 -> 0xf, 8 -> 0x7, 4 -> 0x3, 2 -> 0x1, 1 -> 0x0 */
1045         div = DIV_ROUND_UP_ULL(parent_rate, rate) - 1;
1046
1047         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1048                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1049                                   div << PLL_POST_DIV_SHIFT);
1050 }
1051
1052 const struct clk_ops clk_alpha_pll_postdiv_ops = {
1053         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1054         .round_rate = clk_alpha_pll_postdiv_round_rate,
1055         .set_rate = clk_alpha_pll_postdiv_set_rate,
1056 };
1057 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ops);
1058
1059 const struct clk_ops clk_alpha_pll_postdiv_ro_ops = {
1060         .round_rate = clk_alpha_pll_postdiv_round_ro_rate,
1061         .recalc_rate = clk_alpha_pll_postdiv_recalc_rate,
1062 };
1063 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);
1064
1065 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1066                              const struct alpha_pll_config *config)
1067 {
1068         u32 val, mask;
1069
1070         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1071         clk_alpha_pll_write_config(regmap, PLL_FRAC(pll), config->alpha);
1072         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1073                                                 config->config_ctl_val);
1074         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1075                                                 config->config_ctl_hi_val);
1076         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1077                                                 config->user_ctl_val);
1078         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1079                                                 config->user_ctl_hi_val);
1080         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1081                                                 config->test_ctl_val);
1082         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1083                                                 config->test_ctl_hi_val);
1084
1085         if (config->post_div_mask) {
1086                 mask = config->post_div_mask;
1087                 val = config->post_div_val;
1088                 regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
1089         }
1090
1091         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1092                                                         PLL_UPDATE_BYPASS);
1093
1094         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1095 }
1096 EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
1097
1098 static int alpha_pll_fabia_enable(struct clk_hw *hw)
1099 {
1100         int ret;
1101         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1102         u32 val, opmode_val;
1103         struct regmap *regmap = pll->clkr.regmap;
1104
1105         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1106         if (ret)
1107                 return ret;
1108
1109         /* If in FSM mode, just vote for it */
1110         if (val & PLL_VOTE_FSM_ENA) {
1111                 ret = clk_enable_regmap(hw);
1112                 if (ret)
1113                         return ret;
1114                 return wait_for_pll_enable_active(pll);
1115         }
1116
1117         ret = regmap_read(regmap, PLL_OPMODE(pll), &opmode_val);
1118         if (ret)
1119                 return ret;
1120
1121         /* Skip If PLL is already running */
1122         if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
1123                 return 0;
1124
1125         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1126         if (ret)
1127                 return ret;
1128
1129         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1130         if (ret)
1131                 return ret;
1132
1133         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N,
1134                                  PLL_RESET_N);
1135         if (ret)
1136                 return ret;
1137
1138         ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1139         if (ret)
1140                 return ret;
1141
1142         ret = wait_for_pll_enable_lock(pll);
1143         if (ret)
1144                 return ret;
1145
1146         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
1147                                  PLL_OUT_MASK, PLL_OUT_MASK);
1148         if (ret)
1149                 return ret;
1150
1151         return regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL,
1152                                  PLL_OUTCTRL);
1153 }
1154
1155 static void alpha_pll_fabia_disable(struct clk_hw *hw)
1156 {
1157         int ret;
1158         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1159         u32 val;
1160         struct regmap *regmap = pll->clkr.regmap;
1161
1162         ret = regmap_read(regmap, PLL_MODE(pll), &val);
1163         if (ret)
1164                 return;
1165
1166         /* If in FSM mode, just unvote it */
1167         if (val & PLL_FSM_ENA) {
1168                 clk_disable_regmap(hw);
1169                 return;
1170         }
1171
1172         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1173         if (ret)
1174                 return;
1175
1176         /* Disable main outputs */
1177         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1178         if (ret)
1179                 return;
1180
1181         /* Place the PLL in STANDBY */
1182         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1183 }
1184
1185 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,
1186                                                 unsigned long parent_rate)
1187 {
1188         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1189         u32 l, frac, alpha_width = pll_alpha_width(pll);
1190
1191         regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
1192         regmap_read(pll->clkr.regmap, PLL_FRAC(pll), &frac);
1193
1194         return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
1195 }
1196
1197 /*
1198  * Due to limited number of bits for fractional rate programming, the
1199  * rounded up rate could be marginally higher than the requested rate.
1200  */
1201 static int alpha_pll_check_rate_margin(struct clk_hw *hw,
1202                         unsigned long rrate, unsigned long rate)
1203 {
1204         unsigned long rate_margin = rate + PLL_RATE_MARGIN;
1205
1206         if (rrate > rate_margin || rrate < rate) {
1207                 pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
1208                        clk_hw_get_name(hw), rrate, rate, rate_margin);
1209                 return -EINVAL;
1210         }
1211
1212         return 0;
1213 }
1214
1215 static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
1216                                                 unsigned long prate)
1217 {
1218         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1219         u32 l, alpha_width = pll_alpha_width(pll);
1220         unsigned long rrate;
1221         int ret;
1222         u64 a;
1223
1224         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1225
1226         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1227         if (ret < 0)
1228                 return ret;
1229
1230         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1231         regmap_write(pll->clkr.regmap, PLL_FRAC(pll), a);
1232
1233         return __clk_alpha_pll_update_latch(pll);
1234 }
1235
1236 static int alpha_pll_fabia_prepare(struct clk_hw *hw)
1237 {
1238         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1239         const struct pll_vco *vco;
1240         struct clk_hw *parent_hw;
1241         unsigned long cal_freq, rrate;
1242         u32 cal_l, val, alpha_width = pll_alpha_width(pll);
1243         const char *name = clk_hw_get_name(hw);
1244         u64 a;
1245         int ret;
1246
1247         /* Check if calibration needs to be done i.e. PLL is in reset */
1248         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1249         if (ret)
1250                 return ret;
1251
1252         /* Return early if calibration is not needed. */
1253         if (val & PLL_RESET_N)
1254                 return 0;
1255
1256         vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));
1257         if (!vco) {
1258                 pr_err("%s: alpha pll not in a valid vco range\n", name);
1259                 return -EINVAL;
1260         }
1261
1262         cal_freq = DIV_ROUND_CLOSEST((pll->vco_table[0].min_freq +
1263                                 pll->vco_table[0].max_freq) * 54, 100);
1264
1265         parent_hw = clk_hw_get_parent(hw);
1266         if (!parent_hw)
1267                 return -EINVAL;
1268
1269         rrate = alpha_pll_round_rate(cal_freq, clk_hw_get_rate(parent_hw),
1270                                         &cal_l, &a, alpha_width);
1271
1272         ret = alpha_pll_check_rate_margin(hw, rrate, cal_freq);
1273         if (ret < 0)
1274                 return ret;
1275
1276         /* Setup PLL for calibration frequency */
1277         regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), cal_l);
1278
1279         /* Bringup the PLL at calibration frequency */
1280         ret = clk_alpha_pll_enable(hw);
1281         if (ret) {
1282                 pr_err("%s: alpha pll calibration failed\n", name);
1283                 return ret;
1284         }
1285
1286         clk_alpha_pll_disable(hw);
1287
1288         return 0;
1289 }
1290
1291 const struct clk_ops clk_alpha_pll_fabia_ops = {
1292         .prepare = alpha_pll_fabia_prepare,
1293         .enable = alpha_pll_fabia_enable,
1294         .disable = alpha_pll_fabia_disable,
1295         .is_enabled = clk_alpha_pll_is_enabled,
1296         .set_rate = alpha_pll_fabia_set_rate,
1297         .recalc_rate = alpha_pll_fabia_recalc_rate,
1298         .round_rate = clk_alpha_pll_round_rate,
1299 };
1300 EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
1301
1302 const struct clk_ops clk_alpha_pll_fixed_fabia_ops = {
1303         .enable = alpha_pll_fabia_enable,
1304         .disable = alpha_pll_fabia_disable,
1305         .is_enabled = clk_alpha_pll_is_enabled,
1306         .recalc_rate = alpha_pll_fabia_recalc_rate,
1307         .round_rate = clk_alpha_pll_round_rate,
1308 };
1309 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);
1310
1311 static unsigned long clk_alpha_pll_postdiv_fabia_recalc_rate(struct clk_hw *hw,
1312                                         unsigned long parent_rate)
1313 {
1314         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1315         u32 i, div = 1, val;
1316         int ret;
1317
1318         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1319         if (ret)
1320                 return ret;
1321
1322         val >>= pll->post_div_shift;
1323         val &= BIT(pll->width) - 1;
1324
1325         for (i = 0; i < pll->num_post_div; i++) {
1326                 if (pll->post_div_table[i].val == val) {
1327                         div = pll->post_div_table[i].div;
1328                         break;
1329                 }
1330         }
1331
1332         return (parent_rate / div);
1333 }
1334
1335 static unsigned long
1336 clk_trion_pll_postdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1337 {
1338         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1339         struct regmap *regmap = pll->clkr.regmap;
1340         u32 i, div = 1, val;
1341
1342         regmap_read(regmap, PLL_USER_CTL(pll), &val);
1343
1344         val >>= pll->post_div_shift;
1345         val &= PLL_POST_DIV_MASK(pll);
1346
1347         for (i = 0; i < pll->num_post_div; i++) {
1348                 if (pll->post_div_table[i].val == val) {
1349                         div = pll->post_div_table[i].div;
1350                         break;
1351                 }
1352         }
1353
1354         return (parent_rate / div);
1355 }
1356
1357 static long
1358 clk_trion_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
1359                                  unsigned long *prate)
1360 {
1361         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1362
1363         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1364                                   pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1365 };
1366
1367 static int
1368 clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1369                                unsigned long parent_rate)
1370 {
1371         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1372         struct regmap *regmap = pll->clkr.regmap;
1373         int i, val = 0, div;
1374
1375         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1376         for (i = 0; i < pll->num_post_div; i++) {
1377                 if (pll->post_div_table[i].div == div) {
1378                         val = pll->post_div_table[i].val;
1379                         break;
1380                 }
1381         }
1382
1383         return regmap_update_bits(regmap, PLL_USER_CTL(pll),
1384                                   PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
1385                                   val << PLL_POST_DIV_SHIFT);
1386 }
1387
1388 const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
1389         .recalc_rate = clk_trion_pll_postdiv_recalc_rate,
1390         .round_rate = clk_trion_pll_postdiv_round_rate,
1391         .set_rate = clk_trion_pll_postdiv_set_rate,
1392 };
1393 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_trion_ops);
1394
1395 static long clk_alpha_pll_postdiv_fabia_round_rate(struct clk_hw *hw,
1396                                 unsigned long rate, unsigned long *prate)
1397 {
1398         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1399
1400         return divider_round_rate(hw, rate, prate, pll->post_div_table,
1401                                 pll->width, CLK_DIVIDER_ROUND_CLOSEST);
1402 }
1403
1404 static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
1405                                 unsigned long rate, unsigned long parent_rate)
1406 {
1407         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1408         int i, val = 0, div, ret;
1409
1410         /*
1411          * If the PLL is in FSM mode, then treat set_rate callback as a
1412          * no-operation.
1413          */
1414         ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1415         if (ret)
1416                 return ret;
1417
1418         if (val & PLL_VOTE_FSM_ENA)
1419                 return 0;
1420
1421         div = DIV_ROUND_UP_ULL(parent_rate, rate);
1422         for (i = 0; i < pll->num_post_div; i++) {
1423                 if (pll->post_div_table[i].div == div) {
1424                         val = pll->post_div_table[i].val;
1425                         break;
1426                 }
1427         }
1428
1429         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1430                                 (BIT(pll->width) - 1) << pll->post_div_shift,
1431                                 val << pll->post_div_shift);
1432 }
1433
1434 const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
1435         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1436         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1437         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1438 };
1439 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1440
1441 /**
1442  * clk_lucid_pll_configure - configure the lucid pll
1443  *
1444  * @pll: clk alpha pll
1445  * @regmap: register map
1446  * @config: configuration to apply for pll
1447  */
1448 void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1449                              const struct alpha_pll_config *config)
1450 {
1451         /*
1452          * If the bootloader left the PLL enabled it's likely that there are
1453          * RCGs that will lock up if we disable the PLL below.
1454          */
1455         if (trion_pll_is_enabled(pll, regmap)) {
1456                 pr_debug("Trion PLL is already enabled, skipping configuration\n");
1457                 return;
1458         }
1459
1460         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1461         regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
1462         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1463         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1464                                      config->config_ctl_val);
1465         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1466                                      config->config_ctl_hi_val);
1467         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll),
1468                                      config->config_ctl_hi1_val);
1469         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1470                                         config->user_ctl_val);
1471         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll),
1472                                         config->user_ctl_hi_val);
1473         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll),
1474                                         config->user_ctl_hi1_val);
1475         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1476                                         config->test_ctl_val);
1477         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll),
1478                                         config->test_ctl_hi_val);
1479         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll),
1480                                         config->test_ctl_hi1_val);
1481
1482         regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
1483                            PLL_UPDATE_BYPASS);
1484
1485         /* Disable PLL output */
1486         regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
1487
1488         /* Set operation mode to OFF */
1489         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1490
1491         /* Place the PLL in STANDBY mode */
1492         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1493 }
1494 EXPORT_SYMBOL_GPL(clk_trion_pll_configure);
1495
1496 /*
1497  * The TRION PLL requires a power-on self-calibration which happens when the
1498  * PLL comes out of reset. Calibrate in case it is not completed.
1499  */
1500 static int __alpha_pll_trion_prepare(struct clk_hw *hw, u32 pcal_done)
1501 {
1502         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1503         u32 val;
1504         int ret;
1505
1506         /* Return early if calibration is not needed. */
1507         regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &val);
1508         if (val & pcal_done)
1509                 return 0;
1510
1511         /* On/off to calibrate */
1512         ret = clk_trion_pll_enable(hw);
1513         if (!ret)
1514                 clk_trion_pll_disable(hw);
1515
1516         return ret;
1517 }
1518
1519 static int alpha_pll_trion_prepare(struct clk_hw *hw)
1520 {
1521         return __alpha_pll_trion_prepare(hw, TRION_PCAL_DONE);
1522 }
1523
1524 static int alpha_pll_lucid_prepare(struct clk_hw *hw)
1525 {
1526         return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);
1527 }
1528
1529 static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1530                                       unsigned long prate, u32 latch_bit, u32 latch_ack)
1531 {
1532         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1533         unsigned long rrate;
1534         u32 val, l, alpha_width = pll_alpha_width(pll);
1535         u64 a;
1536         int ret;
1537
1538         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1539
1540         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1541         if (ret < 0)
1542                 return ret;
1543
1544         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1545         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1546
1547         /* Latch the PLL input */
1548         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);
1549         if (ret)
1550                 return ret;
1551
1552         /* Wait for 2 reference cycles before checking the ACK bit. */
1553         udelay(1);
1554         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1555         if (!(val & latch_ack)) {
1556                 pr_err("Lucid PLL latch failed. Output may be unstable!\n");
1557                 return -EINVAL;
1558         }
1559
1560         /* Return the latch input to 0 */
1561         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);
1562         if (ret)
1563                 return ret;
1564
1565         if (clk_hw_is_enabled(hw)) {
1566                 ret = wait_for_pll_enable_lock(pll);
1567                 if (ret)
1568                         return ret;
1569         }
1570
1571         /* Wait for PLL output to stabilize */
1572         udelay(100);
1573         return 0;
1574 }
1575
1576 static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,
1577                                     unsigned long prate)
1578 {
1579         return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);
1580 }
1581
1582 const struct clk_ops clk_alpha_pll_trion_ops = {
1583         .prepare = alpha_pll_trion_prepare,
1584         .enable = clk_trion_pll_enable,
1585         .disable = clk_trion_pll_disable,
1586         .is_enabled = clk_trion_pll_is_enabled,
1587         .recalc_rate = clk_trion_pll_recalc_rate,
1588         .round_rate = clk_alpha_pll_round_rate,
1589         .set_rate = alpha_pll_trion_set_rate,
1590 };
1591 EXPORT_SYMBOL_GPL(clk_alpha_pll_trion_ops);
1592
1593 const struct clk_ops clk_alpha_pll_lucid_ops = {
1594         .prepare = alpha_pll_lucid_prepare,
1595         .enable = clk_trion_pll_enable,
1596         .disable = clk_trion_pll_disable,
1597         .is_enabled = clk_trion_pll_is_enabled,
1598         .recalc_rate = clk_trion_pll_recalc_rate,
1599         .round_rate = clk_alpha_pll_round_rate,
1600         .set_rate = alpha_pll_trion_set_rate,
1601 };
1602 EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
1603
1604 const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
1605         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1606         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1607         .set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
1608 };
1609 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
1610
1611 void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1612                         const struct alpha_pll_config *config)
1613 {
1614         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1615         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1616         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll),
1617                                                         config->user_ctl_val);
1618         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll),
1619                                                 config->config_ctl_val);
1620         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll),
1621                                                 config->config_ctl_hi_val);
1622         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll),
1623                                                 config->test_ctl_val);
1624         clk_alpha_pll_write_config(regmap,  PLL_TEST_CTL_U(pll),
1625                                                 config->test_ctl_hi_val);
1626 }
1627 EXPORT_SYMBOL_GPL(clk_agera_pll_configure);
1628
1629 static int clk_alpha_pll_agera_set_rate(struct clk_hw *hw, unsigned long rate,
1630                                                         unsigned long prate)
1631 {
1632         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1633         u32 l, alpha_width = pll_alpha_width(pll);
1634         int ret;
1635         unsigned long rrate;
1636         u64 a;
1637
1638         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1639         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1640         if (ret < 0)
1641                 return ret;
1642
1643         /* change L_VAL without having to go through the power on sequence */
1644         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1645         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1646
1647         if (clk_hw_is_enabled(hw))
1648                 return wait_for_pll_enable_lock(pll);
1649
1650         return 0;
1651 }
1652
1653 const struct clk_ops clk_alpha_pll_agera_ops = {
1654         .enable = clk_alpha_pll_enable,
1655         .disable = clk_alpha_pll_disable,
1656         .is_enabled = clk_alpha_pll_is_enabled,
1657         .recalc_rate = alpha_pll_fabia_recalc_rate,
1658         .round_rate = clk_alpha_pll_round_rate,
1659         .set_rate = clk_alpha_pll_agera_set_rate,
1660 };
1661 EXPORT_SYMBOL_GPL(clk_alpha_pll_agera_ops);
1662
1663 static int alpha_pll_lucid_5lpe_enable(struct clk_hw *hw)
1664 {
1665         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1666         u32 val;
1667         int ret;
1668
1669         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1670         if (ret)
1671                 return ret;
1672
1673         /* If in FSM mode, just vote for it */
1674         if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1675                 ret = clk_enable_regmap(hw);
1676                 if (ret)
1677                         return ret;
1678                 return wait_for_pll_enable_lock(pll);
1679         }
1680
1681         /* Check if PLL is already enabled, return if enabled */
1682         ret = trion_pll_is_enabled(pll, pll->clkr.regmap);
1683         if (ret < 0)
1684                 return ret;
1685
1686         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1687         if (ret)
1688                 return ret;
1689
1690         regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_RUN);
1691
1692         ret = wait_for_pll_enable_lock(pll);
1693         if (ret)
1694                 return ret;
1695
1696         /* Enable the PLL outputs */
1697         ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
1698         if (ret)
1699                 return ret;
1700
1701         /* Enable the global PLL outputs */
1702         return regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1703 }
1704
1705 static void alpha_pll_lucid_5lpe_disable(struct clk_hw *hw)
1706 {
1707         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1708         u32 val;
1709         int ret;
1710
1711         ret = regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &val);
1712         if (ret)
1713                 return;
1714
1715         /* If in FSM mode, just unvote it */
1716         if (val & LUCID_5LPE_ENABLE_VOTE_RUN) {
1717                 clk_disable_regmap(hw);
1718                 return;
1719         }
1720
1721         /* Disable the global PLL output */
1722         ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1723         if (ret)
1724                 return;
1725
1726         /* Disable the PLL outputs */
1727         ret = regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
1728         if (ret)
1729                 return;
1730
1731         /* Place the PLL mode in STANDBY */
1732         regmap_write(pll->clkr.regmap, PLL_OPMODE(pll), PLL_STANDBY);
1733 }
1734
1735 /*
1736  * The Lucid 5LPE PLL requires a power-on self-calibration which happens
1737  * when the PLL comes out of reset. Calibrate in case it is not completed.
1738  */
1739 static int alpha_pll_lucid_5lpe_prepare(struct clk_hw *hw)
1740 {
1741         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1742         struct clk_hw *p;
1743         u32 val = 0;
1744         int ret;
1745
1746         /* Return early if calibration is not needed. */
1747         regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
1748         if (val & LUCID_5LPE_PCAL_DONE)
1749                 return 0;
1750
1751         p = clk_hw_get_parent(hw);
1752         if (!p)
1753                 return -EINVAL;
1754
1755         ret = alpha_pll_lucid_5lpe_enable(hw);
1756         if (ret)
1757                 return ret;
1758
1759         alpha_pll_lucid_5lpe_disable(hw);
1760
1761         return 0;
1762 }
1763
1764 static int alpha_pll_lucid_5lpe_set_rate(struct clk_hw *hw, unsigned long rate,
1765                                          unsigned long prate)
1766 {
1767         return __alpha_pll_trion_set_rate(hw, rate, prate,
1768                                           LUCID_5LPE_PLL_LATCH_INPUT,
1769                                           LUCID_5LPE_ALPHA_PLL_ACK_LATCH);
1770 }
1771
1772 static int __clk_lucid_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1773                                             unsigned long parent_rate,
1774                                             unsigned long enable_vote_run)
1775 {
1776         struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
1777         struct regmap *regmap = pll->clkr.regmap;
1778         int i, val, div, ret;
1779         u32 mask;
1780
1781         /*
1782          * If the PLL is in FSM mode, then treat set_rate callback as a
1783          * no-operation.
1784          */
1785         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
1786         if (ret)
1787                 return ret;
1788
1789         if (val & enable_vote_run)
1790                 return 0;
1791
1792         if (!pll->post_div_table) {
1793                 pr_err("Missing the post_div_table for the %s PLL\n",
1794                        clk_hw_get_name(&pll->clkr.hw));
1795                 return -EINVAL;
1796         }
1797
1798         div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
1799         for (i = 0; i < pll->num_post_div; i++) {
1800                 if (pll->post_div_table[i].div == div) {
1801                         val = pll->post_div_table[i].val;
1802                         break;
1803                 }
1804         }
1805
1806         mask = GENMASK(pll->width + pll->post_div_shift - 1, pll->post_div_shift);
1807         return regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
1808                                   mask, val << pll->post_div_shift);
1809 }
1810
1811 static int clk_lucid_5lpe_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
1812                                                unsigned long parent_rate)
1813 {
1814         return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_5LPE_ENABLE_VOTE_RUN);
1815 }
1816
1817 const struct clk_ops clk_alpha_pll_lucid_5lpe_ops = {
1818         .prepare = alpha_pll_lucid_5lpe_prepare,
1819         .enable = alpha_pll_lucid_5lpe_enable,
1820         .disable = alpha_pll_lucid_5lpe_disable,
1821         .is_enabled = clk_trion_pll_is_enabled,
1822         .recalc_rate = clk_trion_pll_recalc_rate,
1823         .round_rate = clk_alpha_pll_round_rate,
1824         .set_rate = alpha_pll_lucid_5lpe_set_rate,
1825 };
1826 EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
1827
1828 const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1829         .enable = alpha_pll_lucid_5lpe_enable,
1830         .disable = alpha_pll_lucid_5lpe_disable,
1831         .is_enabled = clk_trion_pll_is_enabled,
1832         .recalc_rate = clk_trion_pll_recalc_rate,
1833         .round_rate = clk_alpha_pll_round_rate,
1834 };
1835 EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1836
1837 const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1838         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1839         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1840         .set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1841 };
1842 EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1843
1844 void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1845                              const struct alpha_pll_config *config)
1846 {
1847         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
1848         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
1849         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
1850         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
1851         clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
1852         clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
1853         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
1854         clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
1855         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
1856         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
1857         clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
1858
1859         regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);
1860
1861         /* Disable PLL output */
1862         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1863
1864         /* Set operation mode to OFF */
1865         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
1866
1867         /* Place the PLL in STANDBY mode */
1868         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1869 }
1870 EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);
1871
1872 static int clk_zonda_pll_enable(struct clk_hw *hw)
1873 {
1874         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1875         struct regmap *regmap = pll->clkr.regmap;
1876         u32 val;
1877         int ret;
1878
1879         regmap_read(regmap, PLL_MODE(pll), &val);
1880
1881         /* If in FSM mode, just vote for it */
1882         if (val & PLL_VOTE_FSM_ENA) {
1883                 ret = clk_enable_regmap(hw);
1884                 if (ret)
1885                         return ret;
1886                 return wait_for_pll_enable_active(pll);
1887         }
1888
1889         /* Get the PLL out of bypass mode */
1890         regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);
1891
1892         /*
1893          * H/W requires a 1us delay between disabling the bypass and
1894          * de-asserting the reset.
1895          */
1896         udelay(1);
1897
1898         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
1899
1900         /* Set operation mode to RUN */
1901         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
1902
1903         regmap_read(regmap, PLL_TEST_CTL(pll), &val);
1904
1905         /* If cfa mode then poll for freq lock */
1906         if (val & ZONDA_STAY_IN_CFA)
1907                 ret = wait_for_zonda_pll_freq_lock(pll);
1908         else
1909                 ret = wait_for_pll_enable_lock(pll);
1910         if (ret)
1911                 return ret;
1912
1913         /* Enable the PLL outputs */
1914         regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);
1915
1916         /* Enable the global PLL outputs */
1917         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
1918
1919         return 0;
1920 }
1921
1922 static void clk_zonda_pll_disable(struct clk_hw *hw)
1923 {
1924         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1925         struct regmap *regmap = pll->clkr.regmap;
1926         u32 val;
1927
1928         regmap_read(regmap, PLL_MODE(pll), &val);
1929
1930         /* If in FSM mode, just unvote it */
1931         if (val & PLL_VOTE_FSM_ENA) {
1932                 clk_disable_regmap(hw);
1933                 return;
1934         }
1935
1936         /* Disable the global PLL output */
1937         regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
1938
1939         /* Disable the PLL outputs */
1940         regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);
1941
1942         /* Put the PLL in bypass and reset */
1943         regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);
1944
1945         /* Place the PLL mode in OFF state */
1946         regmap_write(regmap, PLL_OPMODE(pll), 0x0);
1947 }
1948
1949 static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
1950                                   unsigned long prate)
1951 {
1952         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
1953         unsigned long rrate;
1954         u32 test_ctl_val;
1955         u32 l, alpha_width = pll_alpha_width(pll);
1956         u64 a;
1957         int ret;
1958
1959         rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
1960
1961         ret = alpha_pll_check_rate_margin(hw, rrate, rate);
1962         if (ret < 0)
1963                 return ret;
1964
1965         regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
1966         regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
1967
1968         /* Wait before polling for the frequency latch */
1969         udelay(5);
1970
1971         /* Read stay in cfa mode */
1972         regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);
1973
1974         /* If cfa mode then poll for freq lock */
1975         if (test_ctl_val & ZONDA_STAY_IN_CFA)
1976                 ret = wait_for_zonda_pll_freq_lock(pll);
1977         else
1978                 ret = wait_for_pll_enable_lock(pll);
1979         if (ret)
1980                 return ret;
1981
1982         /* Wait for PLL output to stabilize */
1983         udelay(100);
1984         return 0;
1985 }
1986
1987 const struct clk_ops clk_alpha_pll_zonda_ops = {
1988         .enable = clk_zonda_pll_enable,
1989         .disable = clk_zonda_pll_disable,
1990         .is_enabled = clk_trion_pll_is_enabled,
1991         .recalc_rate = clk_trion_pll_recalc_rate,
1992         .round_rate = clk_alpha_pll_round_rate,
1993         .set_rate = clk_zonda_pll_set_rate,
1994 };
1995 EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
1996
1997 static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
1998 {
1999         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2000         struct regmap *regmap = pll->clkr.regmap;
2001         u32 val;
2002         int ret;
2003
2004         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2005         if (ret)
2006                 return ret;
2007
2008         /* If in FSM mode, just vote for it */
2009         if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2010                 ret = clk_enable_regmap(hw);
2011                 if (ret)
2012                         return ret;
2013                 return wait_for_pll_enable_lock(pll);
2014         }
2015
2016         /* Check if PLL is already enabled */
2017         ret = trion_pll_is_enabled(pll, regmap);
2018         if (ret < 0) {
2019                 return ret;
2020         } else if (ret) {
2021                 pr_warn("%s PLL is already enabled\n", clk_hw_get_name(&pll->clkr.hw));
2022                 return 0;
2023         }
2024
2025         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2026         if (ret)
2027                 return ret;
2028
2029         /* Set operation mode to RUN */
2030         regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
2031
2032         ret = wait_for_pll_enable_lock(pll);
2033         if (ret)
2034                 return ret;
2035
2036         /* Enable the PLL outputs */
2037         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, PLL_OUT_MASK);
2038         if (ret)
2039                 return ret;
2040
2041         /* Enable the global PLL outputs */
2042         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);
2043         if (ret)
2044                 return ret;
2045
2046         /* Ensure that the write above goes through before returning. */
2047         mb();
2048         return ret;
2049 }
2050
2051 static void alpha_pll_lucid_evo_disable(struct clk_hw *hw)
2052 {
2053         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2054         struct regmap *regmap = pll->clkr.regmap;
2055         u32 val;
2056         int ret;
2057
2058         ret = regmap_read(regmap, PLL_USER_CTL(pll), &val);
2059         if (ret)
2060                 return;
2061
2062         /* If in FSM mode, just unvote it */
2063         if (val & LUCID_EVO_ENABLE_VOTE_RUN) {
2064                 clk_disable_regmap(hw);
2065                 return;
2066         }
2067
2068         /* Disable the global PLL output */
2069         ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2070         if (ret)
2071                 return;
2072
2073         /* Disable the PLL outputs */
2074         ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
2075         if (ret)
2076                 return;
2077
2078         /* Place the PLL mode in STANDBY */
2079         regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2080 }
2081
2082 static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2083                                                      unsigned long parent_rate)
2084 {
2085         struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2086         struct regmap *regmap = pll->clkr.regmap;
2087         u32 l, frac;
2088
2089         regmap_read(regmap, PLL_L_VAL(pll), &l);
2090         l &= LUCID_EVO_PLL_L_VAL_MASK;
2091         regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
2092
2093         return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
2094 }
2095
2096 static int clk_lucid_evo_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
2097                                               unsigned long parent_rate)
2098 {
2099         return __clk_lucid_pll_postdiv_set_rate(hw, rate, parent_rate, LUCID_EVO_ENABLE_VOTE_RUN);
2100 }
2101
2102 const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops = {
2103         .enable = alpha_pll_lucid_evo_enable,
2104         .disable = alpha_pll_lucid_evo_disable,
2105         .is_enabled = clk_trion_pll_is_enabled,
2106         .recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2107         .round_rate = clk_alpha_pll_round_rate,
2108 };
2109 EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_evo_ops);
2110
2111 const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops = {
2112         .recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
2113         .round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
2114         .set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2115 };
2116 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);