2 * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
15 #include <linux/of_address.h>
16 #include <linux/regmap.h>
18 #include <dt-bindings/clock/lpc32xx-clock.h>
21 #define pr_fmt(fmt) "%s: " fmt, __func__
23 /* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
24 #define PLL_CTRL_ENABLE BIT(16)
25 #define PLL_CTRL_BYPASS BIT(15)
26 #define PLL_CTRL_DIRECT BIT(14)
27 #define PLL_CTRL_FEEDBACK BIT(13)
28 #define PLL_CTRL_POSTDIV (BIT(12)|BIT(11))
29 #define PLL_CTRL_PREDIV (BIT(10)|BIT(9))
30 #define PLL_CTRL_FEEDDIV (0xFF << 1)
31 #define PLL_CTRL_LOCK BIT(0)
33 /* Clock registers on System Control Block */
34 #define LPC32XX_CLKPWR_DEBUG_CTRL 0x00
35 #define LPC32XX_CLKPWR_USB_DIV 0x1C
36 #define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40
37 #define LPC32XX_CLKPWR_PWR_CTRL 0x44
38 #define LPC32XX_CLKPWR_PLL397_CTRL 0x48
39 #define LPC32XX_CLKPWR_OSC_CTRL 0x4C
40 #define LPC32XX_CLKPWR_SYSCLK_CTRL 0x50
41 #define LPC32XX_CLKPWR_LCDCLK_CTRL 0x54
42 #define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58
43 #define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60
44 #define LPC32XX_CLKPWR_USB_CTRL 0x64
45 #define LPC32XX_CLKPWR_SSP_CTRL 0x78
46 #define LPC32XX_CLKPWR_I2S_CTRL 0x7C
47 #define LPC32XX_CLKPWR_MS_CTRL 0x80
48 #define LPC32XX_CLKPWR_MACCLK_CTRL 0x90
49 #define LPC32XX_CLKPWR_TEST_CLK_CTRL 0xA4
50 #define LPC32XX_CLKPWR_I2CCLK_CTRL 0xAC
51 #define LPC32XX_CLKPWR_KEYCLK_CTRL 0xB0
52 #define LPC32XX_CLKPWR_ADCCLK_CTRL 0xB4
53 #define LPC32XX_CLKPWR_PWMCLK_CTRL 0xB8
54 #define LPC32XX_CLKPWR_TIMCLK_CTRL 0xBC
55 #define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0
56 #define LPC32XX_CLKPWR_SPI_CTRL 0xC4
57 #define LPC32XX_CLKPWR_FLASHCLK_CTRL 0xC8
58 #define LPC32XX_CLKPWR_UART3_CLK_CTRL 0xD0
59 #define LPC32XX_CLKPWR_UART4_CLK_CTRL 0xD4
60 #define LPC32XX_CLKPWR_UART5_CLK_CTRL 0xD8
61 #define LPC32XX_CLKPWR_UART6_CLK_CTRL 0xDC
62 #define LPC32XX_CLKPWR_IRDA_CLK_CTRL 0xE0
63 #define LPC32XX_CLKPWR_UART_CLK_CTRL 0xE4
64 #define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8
66 /* Clock registers on USB controller */
67 #define LPC32XX_USB_CLK_CTRL 0xF4
68 #define LPC32XX_USB_CLK_STS 0xF8
70 static struct regmap_config lpc32xx_scb_regmap_config = {
75 .val_format_endian = REGMAP_ENDIAN_LITTLE,
76 .max_register = 0x114,
80 static struct regmap *clk_regmap;
81 static void __iomem *usb_clk_vbase;
84 LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1,
87 LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1,
91 /* Start from the last defined clock in dt bindings */
92 LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,
97 /* System clocks, PLL 397x and HCLK PLL clocks */
101 LPC32XX_CLK_HCLK_DIV_PERIPH,
102 LPC32XX_CLK_HCLK_DIV,
112 /* Only one control PWR_CTRL[10] for both muxes */
113 LPC32XX_CLK_PERIPH_HCLK_MUX,
114 LPC32XX_CLK_PERIPH_ARM_MUX,
116 /* Only one control PWR_CTRL[2] for all three muxes */
117 LPC32XX_CLK_SYSCLK_PERIPH_MUX,
118 LPC32XX_CLK_SYSCLK_HCLK_MUX,
119 LPC32XX_CLK_SYSCLK_ARM_MUX,
121 /* Two clock sources external to the driver */
122 LPC32XX_CLK_XTAL_32K,
125 /* Renumbered USB clocks, may have a parent from SCB table */
126 LPC32XX_CLK_USB_OFFSET,
127 LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET,
128 LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET,
129 LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET,
130 LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET,
131 LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET,
133 /* Stub for composite clocks */
136 /* Subclocks of composite clocks, clocks above are for CCF */
137 LPC32XX_CLK_PWM1_MUX,
138 LPC32XX_CLK_PWM1_DIV,
139 LPC32XX_CLK_PWM1_GATE,
140 LPC32XX_CLK_PWM2_MUX,
141 LPC32XX_CLK_PWM2_DIV,
142 LPC32XX_CLK_PWM2_GATE,
143 LPC32XX_CLK_UART3_MUX,
144 LPC32XX_CLK_UART3_DIV,
145 LPC32XX_CLK_UART3_GATE,
146 LPC32XX_CLK_UART4_MUX,
147 LPC32XX_CLK_UART4_DIV,
148 LPC32XX_CLK_UART4_GATE,
149 LPC32XX_CLK_UART5_MUX,
150 LPC32XX_CLK_UART5_DIV,
151 LPC32XX_CLK_UART5_GATE,
152 LPC32XX_CLK_UART6_MUX,
153 LPC32XX_CLK_UART6_DIV,
154 LPC32XX_CLK_UART6_GATE,
155 LPC32XX_CLK_TEST1_MUX,
156 LPC32XX_CLK_TEST1_GATE,
157 LPC32XX_CLK_TEST2_MUX,
158 LPC32XX_CLK_TEST2_GATE,
159 LPC32XX_CLK_USB_DIV_DIV,
160 LPC32XX_CLK_USB_DIV_GATE,
164 LPC32XX_CLK_LCD_GATE,
167 LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1,
168 LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1,
171 static struct clk *clk[LPC32XX_CLK_MAX];
172 static struct clk_onecell_data clk_data = {
174 .clk_num = LPC32XX_CLK_MAX,
177 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
178 static struct clk_onecell_data usb_clk_data = {
180 .clk_num = LPC32XX_USB_CLK_MAX,
183 #define LPC32XX_CLK_PARENTS_MAX 5
187 const u8 parents[LPC32XX_CLK_PARENTS_MAX];
192 #define CLK_PREFIX(LITERAL) LPC32XX_CLK_ ## LITERAL
193 #define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int))
195 #define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \
196 [CLK_PREFIX(_idx)] = { \
199 .parents = { __VA_ARGS__ }, \
200 .num_parents = NUMARGS(__VA_ARGS__), \
203 static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = {
204 LPC32XX_CLK_DEFINE(XTAL, "xtal", 0x0),
205 LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k", 0x0),
207 LPC32XX_CLK_DEFINE(RTC, "rtc", 0x0, LPC32XX_CLK_XTAL_32K),
208 LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
209 LPC32XX_CLK_DEFINE(SYS, "sys", CLK_IGNORE_UNUSED,
210 LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
211 LPC32XX_CLK_DEFINE(PLL397X, "pll_397x", CLK_IGNORE_UNUSED,
213 LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll", CLK_IGNORE_UNUSED,
215 LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph",
216 CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL),
217 LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div", CLK_IGNORE_UNUSED,
218 LPC32XX_CLK_HCLK_PLL),
219 LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
220 LPC32XX_CLK_PERIPH_HCLK_MUX),
221 LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED,
222 LPC32XX_CLK_SYSCLK_PERIPH_MUX),
223 LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED,
224 LPC32XX_CLK_PERIPH_ARM_MUX),
226 LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux",
228 LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
229 LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux", CLK_IGNORE_UNUSED,
230 LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
231 LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux",
233 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH),
234 LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux",
236 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV),
237 LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux", CLK_IGNORE_UNUSED,
238 LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL),
240 LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9", CLK_IGNORE_UNUSED,
242 LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll",
243 CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV),
244 LPC32XX_CLK_DEFINE(USB_DIV, "usb_div", 0x0, LPC32XX_CLK_OSC),
245 LPC32XX_CLK_DEFINE(USB, "usb", 0x0, LPC32XX_CLK_USB_PLL),
246 LPC32XX_CLK_DEFINE(DMA, "dma", 0x0, LPC32XX_CLK_HCLK),
247 LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK),
248 LPC32XX_CLK_DEFINE(SLC, "slc", 0x0, LPC32XX_CLK_HCLK),
249 LPC32XX_CLK_DEFINE(LCD, "lcd", 0x0, LPC32XX_CLK_HCLK),
250 LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
251 LPC32XX_CLK_DEFINE(SD, "sd", 0x0, LPC32XX_CLK_ARM),
252 LPC32XX_CLK_DEFINE(DDRAM, "ddram", CLK_GET_RATE_NOCACHE,
253 LPC32XX_CLK_SYSCLK_ARM_MUX),
254 LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK),
255 LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK),
258 * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its
259 * divider register does not contain information about selected rate.
261 LPC32XX_CLK_DEFINE(UART3, "uart3", CLK_GET_RATE_NOCACHE,
262 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
263 LPC32XX_CLK_DEFINE(UART4, "uart4", CLK_GET_RATE_NOCACHE,
264 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
265 LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE,
266 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
267 LPC32XX_CLK_DEFINE(UART6, "uart6", CLK_GET_RATE_NOCACHE,
268 LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
269 LPC32XX_CLK_DEFINE(IRDA, "irda", 0x0, LPC32XX_CLK_PERIPH),
270 LPC32XX_CLK_DEFINE(I2C1, "i2c1", 0x0, LPC32XX_CLK_HCLK),
271 LPC32XX_CLK_DEFINE(I2C2, "i2c2", 0x0, LPC32XX_CLK_HCLK),
272 LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH),
273 LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH),
274 LPC32XX_CLK_DEFINE(TIMER2, "timer2", 0x0, LPC32XX_CLK_PERIPH),
275 LPC32XX_CLK_DEFINE(TIMER3, "timer3", 0x0, LPC32XX_CLK_PERIPH),
276 LPC32XX_CLK_DEFINE(TIMER4, "timer4", 0x0, LPC32XX_CLK_PERIPH),
277 LPC32XX_CLK_DEFINE(TIMER5, "timer5", 0x0, LPC32XX_CLK_PERIPH),
278 LPC32XX_CLK_DEFINE(WDOG, "watchdog", 0x0, LPC32XX_CLK_PERIPH),
279 LPC32XX_CLK_DEFINE(I2S0, "i2s0", 0x0, LPC32XX_CLK_HCLK),
280 LPC32XX_CLK_DEFINE(I2S1, "i2s1", 0x0, LPC32XX_CLK_HCLK),
281 LPC32XX_CLK_DEFINE(SPI1, "spi1", 0x0, LPC32XX_CLK_HCLK),
282 LPC32XX_CLK_DEFINE(SPI2, "spi2", 0x0, LPC32XX_CLK_HCLK),
283 LPC32XX_CLK_DEFINE(MCPWM, "mcpwm", 0x0, LPC32XX_CLK_HCLK),
284 LPC32XX_CLK_DEFINE(HSTIMER, "hstimer", 0x0, LPC32XX_CLK_PERIPH),
285 LPC32XX_CLK_DEFINE(KEY, "key", 0x0, LPC32XX_CLK_RTC),
286 LPC32XX_CLK_DEFINE(PWM1, "pwm1", 0x0,
287 LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
288 LPC32XX_CLK_DEFINE(PWM2, "pwm2", 0x0,
289 LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
290 LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
291 LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV),
292 LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div", 0x0, LPC32XX_CLK_PERIPH),
293 LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc", 0x0, LPC32XX_CLK_RTC),
294 LPC32XX_CLK_DEFINE(TEST1, "test1", 0x0,
295 LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC),
296 LPC32XX_CLK_DEFINE(TEST2, "test2", 0x0,
297 LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB,
298 LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
300 /* USB controller clocks */
301 LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb", 0x0, LPC32XX_CLK_USB),
302 LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg", 0x0, LPC32XX_CLK_USB_AHB),
303 LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c", 0x0, LPC32XX_CLK_USB_AHB),
304 LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev", 0x0, LPC32XX_CLK_USB_OTG),
305 LPC32XX_CLK_DEFINE(USB_HOST, "usb_host", 0x0, LPC32XX_CLK_USB_OTG),
328 struct lpc32xx_pll_clk {
335 enum clk_pll_mode mode;
338 struct lpc32xx_usb_clk {
347 struct lpc32xx_clk_mux {
356 struct lpc32xx_clk_div {
361 const struct clk_div_table *table;
365 struct lpc32xx_clk_gate {
372 #define to_lpc32xx_clk(_hw) container_of(_hw, struct lpc32xx_clk, hw)
373 #define to_lpc32xx_pll_clk(_hw) container_of(_hw, struct lpc32xx_pll_clk, hw)
374 #define to_lpc32xx_usb_clk(_hw) container_of(_hw, struct lpc32xx_usb_clk, hw)
375 #define to_lpc32xx_mux(_hw) container_of(_hw, struct lpc32xx_clk_mux, hw)
376 #define to_lpc32xx_div(_hw) container_of(_hw, struct lpc32xx_clk_div, hw)
377 #define to_lpc32xx_gate(_hw) container_of(_hw, struct lpc32xx_clk_gate, hw)
379 static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max)
381 return (val0 >= (val1 * min) && val0 <= (val1 * max));
384 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk)
386 return readl(usb_clk_vbase + LPC32XX_USB_CLK_STS);
389 static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
391 writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
394 static int clk_mask_enable(struct clk_hw *hw)
396 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
399 regmap_read(clk_regmap, clk->reg, &val);
401 if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
404 return regmap_update_bits(clk_regmap, clk->reg,
405 clk->enable_mask, clk->enable);
408 static void clk_mask_disable(struct clk_hw *hw)
410 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
412 regmap_update_bits(clk_regmap, clk->reg,
413 clk->disable_mask, clk->disable);
416 static int clk_mask_is_enabled(struct clk_hw *hw)
418 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
421 regmap_read(clk_regmap, clk->reg, &val);
423 return ((val & clk->enable_mask) == clk->enable);
426 static const struct clk_ops clk_mask_ops = {
427 .enable = clk_mask_enable,
428 .disable = clk_mask_disable,
429 .is_enabled = clk_mask_is_enabled,
432 static int clk_pll_enable(struct clk_hw *hw)
434 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
437 regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable);
439 for (count = 0; count < 1000; count++) {
440 regmap_read(clk_regmap, clk->reg, &val);
441 if (val & PLL_CTRL_LOCK)
445 if (val & PLL_CTRL_LOCK)
451 static void clk_pll_disable(struct clk_hw *hw)
453 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
455 regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0);
458 static int clk_pll_is_enabled(struct clk_hw *hw)
460 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
463 regmap_read(clk_regmap, clk->reg, &val);
465 val &= clk->enable | PLL_CTRL_LOCK;
466 if (val == (clk->enable | PLL_CTRL_LOCK))
472 static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw,
473 unsigned long parent_rate)
475 return parent_rate * 397;
478 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
479 unsigned long parent_rate)
481 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
482 bool is_direct, is_bypass, is_feedback;
483 unsigned long rate, cco_rate, ref_rate;
486 regmap_read(clk_regmap, clk->reg, &val);
487 is_direct = val & PLL_CTRL_DIRECT;
488 is_bypass = val & PLL_CTRL_BYPASS;
489 is_feedback = val & PLL_CTRL_FEEDBACK;
491 clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
492 clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
493 clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
495 if (is_direct && is_bypass) {
497 clk->mode = PLL_DIRECT_BYPASS;
501 clk->mode = PLL_BYPASS;
502 return parent_rate / (1 << clk->p_div);
506 clk->mode = PLL_DIRECT;
509 ref_rate = parent_rate / clk->n_div;
510 rate = cco_rate = ref_rate * clk->m_div;
514 cco_rate *= (1 << clk->p_div);
515 clk->mode = PLL_INTEGER;
517 rate /= (1 << clk->p_div);
518 clk->mode = PLL_NON_INTEGER;
522 pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n",
524 parent_rate, val, is_direct, is_bypass, is_feedback,
525 clk->n_div, clk->m_div, (1 << clk->p_div), rate);
527 if (clk_pll_is_enabled(hw) &&
528 !(pll_is_valid(parent_rate, 1, 1000000, 20000000)
529 && pll_is_valid(cco_rate, 1, 156000000, 320000000)
530 && pll_is_valid(ref_rate, 1, 1000000, 27000000)))
531 pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
533 parent_rate, cco_rate, ref_rate);
538 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
539 unsigned long parent_rate)
541 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
543 unsigned long new_rate;
545 /* Validate PLL clock parameters computed on round rate stage */
548 val = PLL_CTRL_DIRECT;
549 val |= (clk->m_div - 1) << 1;
550 val |= (clk->n_div - 1) << 9;
551 new_rate = (parent_rate * clk->m_div) / clk->n_div;
554 val = PLL_CTRL_BYPASS;
555 val |= (clk->p_div - 1) << 11;
556 new_rate = parent_rate / (1 << (clk->p_div));
558 case PLL_DIRECT_BYPASS:
559 val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS;
560 new_rate = parent_rate;
563 val = PLL_CTRL_FEEDBACK;
564 val |= (clk->m_div - 1) << 1;
565 val |= (clk->n_div - 1) << 9;
566 val |= (clk->p_div - 1) << 11;
567 new_rate = (parent_rate * clk->m_div) / clk->n_div;
569 case PLL_NON_INTEGER:
571 val |= (clk->m_div - 1) << 1;
572 val |= (clk->n_div - 1) << 9;
573 val |= (clk->p_div - 1) << 11;
574 new_rate = (parent_rate * clk->m_div) /
575 (clk->n_div * (1 << clk->p_div));
581 /* Sanity check that round rate is equal to the requested one */
582 if (new_rate != rate)
585 return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
588 static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
589 unsigned long *parent_rate)
591 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
592 u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6;
593 u64 m = 0, n = 0, p = 0;
596 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
598 if (rate > 266500000)
601 /* Have to check all 20 possibilities to find the minimal M */
602 for (p_i = 4; p_i >= 0; p_i--) {
603 for (n_i = 4; n_i > 0; n_i--) {
604 m_i = div64_u64(o * n_i * (1 << p_i), i);
606 /* Check for valid PLL parameter constraints */
607 if (!(m_i && m_i <= 256
608 && pll_is_valid(i, n_i, 1000000, 27000000)
609 && pll_is_valid(i * m_i * (1 << p_i), n_i,
610 156000000, 320000000)))
613 /* Store some intermediate valid parameters */
614 if (o * n_i * (1 << p_i) - i * m_i <= d) {
618 d = o * n_i * (1 << p_i) - i * m_i;
623 if (d == (u64)rate << 6) {
624 pr_err("%s: %lu: no valid PLL parameters are found\n",
625 clk_hw_get_name(hw), rate);
633 /* Set only direct or non-integer mode of PLL */
635 clk->mode = PLL_DIRECT;
637 clk->mode = PLL_NON_INTEGER;
639 o = div64_u64(i * m, n * (1 << p));
642 pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n",
643 clk_hw_get_name(hw), rate, m, n, p);
645 pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n",
646 clk_hw_get_name(hw), rate, m, n, p, o);
651 static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate,
652 unsigned long *parent_rate)
654 struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
655 struct clk_hw *usb_div_hw, *osc_hw;
658 pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), *parent_rate, rate);
661 * The only supported USB clock is 48MHz, with PLL internal constraints
662 * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz
663 * and post-divider must be 4, this slightly simplifies calculation of
664 * USB divider, USB PLL N and M parameters.
666 if (rate != 48000000)
669 /* USB divider clock */
670 usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
674 /* Main oscillator clock */
675 osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
678 o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */
680 /* Check if valid USB divider and USB PLL parameters exists */
681 for (d_i = 16; d_i >= 1; d_i--) {
682 for (n_i = 1; n_i <= 4; n_i++) {
683 m = div64_u64(192000000 * d_i * n_i, o);
685 && m * o == 192000000 * d_i * n_i
686 && pll_is_valid(o, d_i, 1000000, 20000000)
687 && pll_is_valid(o, d_i * n_i, 1000000, 27000000)))
693 clk->mode = PLL_NON_INTEGER;
694 *parent_rate = div64_u64(o, d_i);
703 #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr) \
704 static const struct clk_ops clk_ ##_name ## _ops = { \
705 .enable = clk_pll_enable, \
706 .disable = clk_pll_disable, \
707 .is_enabled = clk_pll_is_enabled, \
708 .recalc_rate = _rc, \
713 LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL);
714 LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate,
715 clk_pll_set_rate, clk_hclk_pll_round_rate);
716 LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate,
717 clk_pll_set_rate, clk_usb_pll_round_rate);
719 static int clk_ddram_is_enabled(struct clk_hw *hw)
721 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
724 regmap_read(clk_regmap, clk->reg, &val);
725 val &= clk->enable_mask | clk->busy_mask;
727 return (val == (BIT(7) | BIT(0)) ||
728 val == (BIT(8) | BIT(1)));
731 static int clk_ddram_enable(struct clk_hw *hw)
733 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
736 regmap_read(clk_regmap, clk->reg, &val);
737 hclk_div = val & clk->busy_mask;
740 * DDRAM clock must be 2 times higher than HCLK,
741 * this implies DDRAM clock can not be enabled,
742 * if HCLK clock rate is equal to ARM clock rate
744 if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0)))
747 return regmap_update_bits(clk_regmap, clk->reg,
748 clk->enable_mask, hclk_div << 7);
751 static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw,
752 unsigned long parent_rate)
754 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
757 if (!clk_ddram_is_enabled(hw))
760 regmap_read(clk_regmap, clk->reg, &val);
761 val &= clk->enable_mask;
763 return parent_rate / (val >> 7);
766 static const struct clk_ops clk_ddram_ops = {
767 .enable = clk_ddram_enable,
768 .disable = clk_mask_disable,
769 .is_enabled = clk_ddram_is_enabled,
770 .recalc_rate = clk_ddram_recalc_rate,
773 static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw,
774 unsigned long parent_rate)
776 struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
779 regmap_read(clk_regmap, clk->reg, &val);
780 x = (val & 0xFF00) >> 8;
784 return (parent_rate * x) / y;
789 static const struct clk_ops lpc32xx_uart_div_ops = {
790 .recalc_rate = lpc32xx_clk_uart_recalc_rate,
793 static const struct clk_div_table clk_hclk_div_table[] = {
794 { .val = 0, .div = 1 },
795 { .val = 1, .div = 2 },
796 { .val = 2, .div = 4 },
800 static u32 test1_mux_table[] = { 0, 1, 2, };
801 static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, };
803 static int clk_usb_enable(struct clk_hw *hw)
805 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
806 u32 val, ctrl_val, count;
808 pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable);
810 if (clk->ctrl_mask) {
811 regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
812 regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
813 clk->ctrl_mask, clk->ctrl_enable);
816 val = lpc32xx_usb_clk_read(clk);
817 if (clk->busy && (val & clk->busy) == clk->busy) {
819 regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
825 lpc32xx_usb_clk_write(clk, val);
827 for (count = 0; count < 1000; count++) {
828 val = lpc32xx_usb_clk_read(clk);
829 if ((val & clk->enable) == clk->enable)
833 if ((val & clk->enable) == clk->enable)
837 regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, ctrl_val);
842 static void clk_usb_disable(struct clk_hw *hw)
844 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
845 u32 val = lpc32xx_usb_clk_read(clk);
848 lpc32xx_usb_clk_write(clk, val);
851 regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
852 clk->ctrl_mask, clk->ctrl_disable);
855 static int clk_usb_is_enabled(struct clk_hw *hw)
857 struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
860 if (clk->ctrl_mask) {
861 regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
862 if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable)
866 val = lpc32xx_usb_clk_read(clk);
868 return ((val & clk->enable) == clk->enable);
871 static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw,
872 unsigned long parent_rate)
874 return clk_get_rate(clk[LPC32XX_CLK_PERIPH]);
877 static const struct clk_ops clk_usb_ops = {
878 .enable = clk_usb_enable,
879 .disable = clk_usb_disable,
880 .is_enabled = clk_usb_is_enabled,
883 static const struct clk_ops clk_usb_i2c_ops = {
884 .enable = clk_usb_enable,
885 .disable = clk_usb_disable,
886 .is_enabled = clk_usb_is_enabled,
887 .recalc_rate = clk_usb_i2c_recalc_rate,
890 static int lpc32xx_clk_gate_enable(struct clk_hw *hw)
892 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
893 u32 mask = BIT(clk->bit_idx);
894 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
896 return regmap_update_bits(clk_regmap, clk->reg, mask, val);
899 static void lpc32xx_clk_gate_disable(struct clk_hw *hw)
901 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
902 u32 mask = BIT(clk->bit_idx);
903 u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
905 regmap_update_bits(clk_regmap, clk->reg, mask, val);
908 static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw)
910 struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
914 regmap_read(clk_regmap, clk->reg, &val);
915 is_set = val & BIT(clk->bit_idx);
917 return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set);
920 static const struct clk_ops lpc32xx_clk_gate_ops = {
921 .enable = lpc32xx_clk_gate_enable,
922 .disable = lpc32xx_clk_gate_disable,
923 .is_enabled = lpc32xx_clk_gate_is_enabled,
926 #define div_mask(width) ((1 << (width)) - 1)
928 static unsigned int _get_table_div(const struct clk_div_table *table,
931 const struct clk_div_table *clkt;
933 for (clkt = table; clkt->div; clkt++)
934 if (clkt->val == val)
939 static unsigned int _get_div(const struct clk_div_table *table,
940 unsigned int val, unsigned long flags, u8 width)
942 if (flags & CLK_DIVIDER_ONE_BASED)
945 return _get_table_div(table, val);
949 static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
950 unsigned long parent_rate)
952 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
955 regmap_read(clk_regmap, divider->reg, &val);
957 val >>= divider->shift;
958 val &= div_mask(divider->width);
960 return divider_recalc_rate(hw, parent_rate, val, divider->table,
961 divider->flags, divider->width);
964 static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
965 unsigned long *prate)
967 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
968 unsigned int bestdiv;
970 /* if read only, just return current value */
971 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
972 regmap_read(clk_regmap, divider->reg, &bestdiv);
973 bestdiv >>= divider->shift;
974 bestdiv &= div_mask(divider->width);
975 bestdiv = _get_div(divider->table, bestdiv, divider->flags,
977 return DIV_ROUND_UP(*prate, bestdiv);
980 return divider_round_rate(hw, rate, prate, divider->table,
981 divider->width, divider->flags);
984 static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
985 unsigned long parent_rate)
987 struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
990 value = divider_get_val(rate, parent_rate, divider->table,
991 divider->width, divider->flags);
993 return regmap_update_bits(clk_regmap, divider->reg,
994 div_mask(divider->width) << divider->shift,
995 value << divider->shift);
998 static const struct clk_ops lpc32xx_clk_divider_ops = {
999 .recalc_rate = clk_divider_recalc_rate,
1000 .round_rate = clk_divider_round_rate,
1001 .set_rate = clk_divider_set_rate,
1004 static u8 clk_mux_get_parent(struct clk_hw *hw)
1006 struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
1007 u32 num_parents = clk_hw_get_num_parents(hw);
1010 regmap_read(clk_regmap, mux->reg, &val);
1017 for (i = 0; i < num_parents; i++)
1018 if (mux->table[i] == val)
1023 if (val >= num_parents)
1029 static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
1031 struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
1034 index = mux->table[index];
1036 return regmap_update_bits(clk_regmap, mux->reg,
1037 mux->mask << mux->shift, index << mux->shift);
1040 static const struct clk_ops lpc32xx_clk_mux_ro_ops = {
1041 .get_parent = clk_mux_get_parent,
1044 static const struct clk_ops lpc32xx_clk_mux_ops = {
1045 .get_parent = clk_mux_get_parent,
1046 .set_parent = clk_mux_set_parent,
1047 .determine_rate = __clk_mux_determine_rate,
1050 enum lpc32xx_clk_type {
1061 struct clk_hw_proto0 {
1062 const struct clk_ops *ops;
1064 struct lpc32xx_pll_clk pll;
1065 struct lpc32xx_clk clk;
1066 struct lpc32xx_usb_clk usb_clk;
1067 struct lpc32xx_clk_mux mux;
1068 struct lpc32xx_clk_div div;
1069 struct lpc32xx_clk_gate gate;
1073 struct clk_hw_proto1 {
1074 struct clk_hw_proto0 *mux;
1075 struct clk_hw_proto0 *div;
1076 struct clk_hw_proto0 *gate;
1079 struct clk_hw_proto {
1080 enum lpc32xx_clk_type type;
1083 struct clk_fixed_rate f;
1084 struct clk_hw_proto0 hw0;
1085 struct clk_hw_proto1 hw1;
1089 #define LPC32XX_DEFINE_FIXED(_idx, _rate) \
1090 [CLK_PREFIX(_idx)] = { \
1091 .type = CLK_FIXED, \
1094 .fixed_rate = (_rate), \
1099 #define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \
1100 [CLK_PREFIX(_idx)] = { \
1101 .type = CLK_LPC32XX_PLL, \
1104 .ops = &clk_ ##_name ## _ops, \
1107 .reg = LPC32XX_CLKPWR_ ## _reg, \
1108 .enable = (_enable), \
1115 #define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \
1116 [CLK_PREFIX(_idx)] = { \
1120 .ops = (_flags & CLK_MUX_READ_ONLY ? \
1121 &lpc32xx_clk_mux_ro_ops : \
1122 &lpc32xx_clk_mux_ops), \
1125 .reg = LPC32XX_CLKPWR_ ## _reg, \
1127 .shift = (_shift), \
1128 .table = (_table), \
1129 .flags = (_flags), \
1136 #define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \
1137 [CLK_PREFIX(_idx)] = { \
1141 .ops = &lpc32xx_clk_divider_ops, \
1144 .reg = LPC32XX_CLKPWR_ ## _reg, \
1145 .shift = (_shift), \
1146 .width = (_width), \
1147 .table = (_table), \
1148 .flags = (_flags), \
1155 #define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \
1156 [CLK_PREFIX(_idx)] = { \
1160 .ops = &lpc32xx_clk_gate_ops, \
1163 .reg = LPC32XX_CLKPWR_ ## _reg, \
1164 .bit_idx = (_bit), \
1165 .flags = (_flags), \
1172 #define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \
1173 [CLK_PREFIX(_idx)] = { \
1174 .type = CLK_LPC32XX, \
1180 .reg = LPC32XX_CLKPWR_ ## _reg, \
1182 .enable_mask = (_em), \
1184 .disable_mask = (_dm), \
1186 .busy_mask = (_bm), \
1193 #define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \
1194 [CLK_PREFIX(_idx)] = { \
1195 .type = CLK_LPC32XX_USB, \
1201 .ctrl_enable = (_ce), \
1202 .ctrl_disable = (_cd), \
1203 .ctrl_mask = (_cm), \
1212 #define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \
1213 [CLK_PREFIX(_idx)] = { \
1214 .type = CLK_COMPOSITE, \
1217 .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \
1218 &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \
1219 .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \
1220 &clk_hw_proto[CLK_PREFIX(_div)].hw0), \
1221 .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
1222 &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
1227 static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
1228 LPC32XX_DEFINE_FIXED(RTC, 32768),
1229 LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
1230 LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
1231 LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
1232 LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1233 LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0),
1235 LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL,
1236 CLK_DIVIDER_READ_ONLY),
1237 LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table,
1238 CLK_DIVIDER_READ_ONLY),
1240 /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
1241 LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
1243 LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
1245 LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
1247 /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
1248 LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
1250 LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
1253 /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
1254 LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1255 LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1256 LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
1258 LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0),
1259 LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0),
1260 LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7),
1261 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops),
1263 LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
1264 LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
1265 LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0),
1266 LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0),
1267 LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0),
1268 LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0),
1270 LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),
1271 LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
1272 LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0),
1273 LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0),
1274 LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0),
1275 LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0),
1276 LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0),
1277 LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0),
1278 LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0),
1279 LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0),
1281 LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0),
1282 LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0),
1284 LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
1285 LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
1286 CLK_DIVIDER_ONE_BASED),
1287 LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
1288 LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
1290 LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
1291 LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
1292 CLK_DIVIDER_ONE_BASED),
1293 LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
1294 LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
1296 LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0),
1297 LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL,
1298 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1299 LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
1300 LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
1302 LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0),
1303 LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL,
1304 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1305 LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0),
1306 LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE),
1308 LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0),
1309 LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL,
1310 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1311 LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0),
1312 LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
1314 LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0),
1315 LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL,
1316 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1317 LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0),
1318 LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE),
1320 LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL,
1321 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
1323 LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3,
1324 test1_mux_table, 0),
1325 LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0),
1326 LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE),
1328 LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7,
1329 test2_mux_table, 0),
1330 LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0),
1331 LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE),
1333 LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
1335 LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0),
1336 LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0),
1337 LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
1339 LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
1340 LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
1341 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
1342 LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
1344 LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0),
1345 LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0),
1346 LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE),
1348 LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL,
1349 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
1350 BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
1351 0x0, 0x0, clk_mask_ops),
1352 LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL,
1353 BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0,
1354 BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops),
1355 LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
1356 BIT(1), BIT(2) | BIT(1), 0x0, BIT(1),
1357 BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops),
1359 * ADC/TS clock unfortunately cannot be registered as a composite one
1360 * due to a different connection of gate, div and mux, e.g. gating it
1361 * won't mean that the clock is off, if peripheral clock is its parent:
1363 * rtc-->[gate]-->| |
1365 * pclk-->[div]-->| |
1368 * ADC --- resulting clock must be <= 4.5 MHz
1369 * TS --- resulting clock must be <= 400 KHz
1371 LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0),
1372 LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0),
1373 LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
1375 /* USB controller clocks */
1376 LPC32XX_DEFINE_USB(USB_AHB,
1377 BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops),
1378 LPC32XX_DEFINE_USB(USB_OTG,
1379 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops),
1380 LPC32XX_DEFINE_USB(USB_I2C,
1381 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops),
1382 LPC32XX_DEFINE_USB(USB_DEV,
1383 BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops),
1384 LPC32XX_DEFINE_USB(USB_HOST,
1385 BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops),
1388 static struct clk * __init lpc32xx_clk_register(u32 id)
1390 const struct clk_proto_t *lpc32xx_clk = &clk_proto[id];
1391 struct clk_hw_proto *clk_hw = &clk_hw_proto[id];
1392 const char *parents[LPC32XX_CLK_PARENTS_MAX];
1396 for (i = 0; i < lpc32xx_clk->num_parents; i++)
1397 parents[i] = clk_proto[lpc32xx_clk->parents[i]].name;
1399 pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name,
1400 parents[0], clk_hw->type);
1402 switch (clk_hw->type) {
1404 case CLK_LPC32XX_PLL:
1405 case CLK_LPC32XX_USB:
1410 struct clk_init_data clk_init = {
1411 .name = lpc32xx_clk->name,
1412 .parent_names = parents,
1413 .num_parents = lpc32xx_clk->num_parents,
1414 .flags = lpc32xx_clk->flags,
1415 .ops = clk_hw->hw0.ops,
1419 if (clk_hw->type == CLK_LPC32XX)
1420 hw = &clk_hw->hw0.clk.hw;
1421 else if (clk_hw->type == CLK_LPC32XX_PLL)
1422 hw = &clk_hw->hw0.pll.hw;
1423 else if (clk_hw->type == CLK_LPC32XX_USB)
1424 hw = &clk_hw->hw0.usb_clk.hw;
1425 else if (clk_hw->type == CLK_MUX)
1426 hw = &clk_hw->hw0.mux.hw;
1427 else if (clk_hw->type == CLK_DIV)
1428 hw = &clk_hw->hw0.div.hw;
1429 else if (clk_hw->type == CLK_GATE)
1430 hw = &clk_hw->hw0.gate.hw;
1432 return ERR_PTR(-EINVAL);
1434 hw->init = &clk_init;
1435 clk = clk_register(NULL, hw);
1440 struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
1441 const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL;
1442 struct clk_hw_proto0 *mux0, *div0, *gate0;
1444 mux0 = clk_hw->hw1.mux;
1445 div0 = clk_hw->hw1.div;
1446 gate0 = clk_hw->hw1.gate;
1449 mux_hw = &mux0->clk.hw;
1453 div_hw = &div0->clk.hw;
1457 gate_hw = &gate0->clk.hw;
1460 clk = clk_register_composite(NULL, lpc32xx_clk->name,
1461 parents, lpc32xx_clk->num_parents,
1462 mux_hw, mops, div_hw, dops,
1463 gate_hw, gops, lpc32xx_clk->flags);
1468 struct clk_fixed_rate *fixed = &clk_hw->f;
1470 clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
1471 parents[0], 0, fixed->fixed_rate);
1475 clk = ERR_PTR(-EINVAL);
1481 static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
1485 regmap_read(clk_regmap, reg, &val);
1487 if (!(val & div_mask)) {
1489 val |= BIT(__ffs(div_mask));
1492 regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
1495 static void __init lpc32xx_clk_init(struct device_node *np)
1498 struct clk *clk_osc, *clk_32k;
1499 void __iomem *base = NULL;
1501 /* Ensure that parent clocks are available and valid */
1502 clk_32k = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL_32K].name);
1503 if (IS_ERR(clk_32k)) {
1504 pr_err("failed to find external 32KHz clock: %ld\n",
1508 if (clk_get_rate(clk_32k) != 32768) {
1509 pr_err("invalid clock rate of external 32KHz oscillator\n");
1513 clk_osc = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL].name);
1514 if (IS_ERR(clk_osc)) {
1515 pr_err("failed to find external main oscillator clock: %ld\n",
1520 base = of_iomap(np, 0);
1522 pr_err("failed to map system control block registers\n");
1526 clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config);
1527 if (IS_ERR(clk_regmap)) {
1528 pr_err("failed to regmap system control block: %ld\n",
1529 PTR_ERR(clk_regmap));
1535 * Divider part of PWM and MS clocks requires a quirk to avoid
1536 * a misinterpretation of formally valid zero value in register
1537 * bitfield, which indicates another clock gate. Instead of
1538 * adding complexity to a gate clock ensure that zero value in
1539 * divider clock is never met in runtime.
1541 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0));
1542 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2));
1543 lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9));
1545 for (i = 1; i < LPC32XX_CLK_MAX; i++) {
1546 clk[i] = lpc32xx_clk_register(i);
1547 if (IS_ERR(clk[i])) {
1548 pr_err("failed to register %s clock: %ld\n",
1549 clk_proto[i].name, PTR_ERR(clk[i]));
1554 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
1556 /* Set 48MHz rate of USB PLL clock */
1557 clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
1559 /* These two clocks must be always on independently on consumers */
1560 clk_prepare_enable(clk[LPC32XX_CLK_ARM]);
1561 clk_prepare_enable(clk[LPC32XX_CLK_HCLK]);
1563 /* Enable ARM VFP by default */
1564 clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]);
1566 /* Disable enabled by default clocks for NAND MLC and SLC */
1567 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw);
1568 clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw);
1570 CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
1572 static void __init lpc32xx_usb_clk_init(struct device_node *np)
1576 usb_clk_vbase = of_iomap(np, 0);
1577 if (!usb_clk_vbase) {
1578 pr_err("failed to map address range\n");
1582 for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) {
1583 usb_clk[i] = lpc32xx_clk_register(i + LPC32XX_CLK_USB_OFFSET);
1584 if (IS_ERR(usb_clk[i])) {
1585 pr_err("failed to register %s clock: %ld\n",
1586 clk_proto[i].name, PTR_ERR(usb_clk[i]));
1591 of_clk_add_provider(np, of_clk_src_onecell_get, &usb_clk_data);
1593 CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);