drivers/clk/mvebu/armada-37xx-periph.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell Armada 37xx SoC Peripheral clocks
   4  *
   5  * Copyright (C) 2016 Marvell
   6  *
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  *
   9  * Most of the peripheral clocks can be modelled like this:
  10  *             _____    _______    _______
  11  * TBG-A-P  --|     |  |       |  |       |   ______
  12  * TBG-B-P  --| Mux |--| /div1 |--| /div2 |--| Gate |--> perip_clk
  13  * TBG-A-S  --|     |  |       |  |       |  |______|
  14  * TBG-B-S  --|_____|  |_______|  |_______|
  15  *
  16  * However some clocks may use only one or two block or and use the
  17  * xtal clock as parent.
  18  */
  19
  20 #include <linux/clk-provider.h>
  21 #include <linux/mfd/syscon.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/regmap.h>
  26 #include <linux/slab.h>
  27
  28 #define TBG_SEL         0x0
  29 #define DIV_SEL0        0x4
  30 #define DIV_SEL1        0x8
  31 #define DIV_SEL2        0xC
  32 #define CLK_SEL         0x10
  33 #define CLK_DIS         0x14
  34
  35 #define  ARMADA_37XX_DVFS_LOAD_1 1
  36 #define LOAD_LEVEL_NR   4
  37
  38 #define ARMADA_37XX_NB_L0L1     0x18
  39 #define ARMADA_37XX_NB_L2L3     0x1C
  40 #define         ARMADA_37XX_NB_TBG_DIV_OFF      13
  41 #define         ARMADA_37XX_NB_TBG_DIV_MASK     0x7
  42 #define         ARMADA_37XX_NB_CLK_SEL_OFF      11
  43 #define         ARMADA_37XX_NB_CLK_SEL_MASK     0x1
  44 #define         ARMADA_37XX_NB_TBG_SEL_OFF      9
  45 #define         ARMADA_37XX_NB_TBG_SEL_MASK     0x3
  46 #define         ARMADA_37XX_NB_CONFIG_SHIFT     16
  47 #define ARMADA_37XX_NB_DYN_MOD  0x24
  48 #define         ARMADA_37XX_NB_DFS_EN   31
  49 #define ARMADA_37XX_NB_CPU_LOAD 0x30
  50 #define         ARMADA_37XX_NB_CPU_LOAD_MASK    0x3
  51 #define         ARMADA_37XX_DVFS_LOAD_0         0
  52 #define         ARMADA_37XX_DVFS_LOAD_1         1
  53 #define         ARMADA_37XX_DVFS_LOAD_2         2
  54 #define         ARMADA_37XX_DVFS_LOAD_3         3
  55
  56 struct clk_periph_driver_data {
  57         struct clk_hw_onecell_data *hw_data;
  58         spinlock_t lock;
  59         void __iomem *reg;
  60
  61         /* Storage registers for suspend/resume operations */
  62         u32 tbg_sel;
  63         u32 div_sel0;
  64         u32 div_sel1;
  65         u32 div_sel2;
  66         u32 clk_sel;
  67         u32 clk_dis;
  68 };
  69
  70 struct clk_double_div {
  71         struct clk_hw hw;
  72         void __iomem *reg1;
  73         u8 shift1;
  74         void __iomem *reg2;
  75         u8 shift2;
  76 };
  77
  78 struct clk_pm_cpu {
  79         struct clk_hw hw;
  80         void __iomem *reg_mux;
  81         u8 shift_mux;
  82         u32 mask_mux;
  83         void __iomem *reg_div;
  84         u8 shift_div;
  85         struct regmap *nb_pm_base;
  86 };
  87
  88 #define to_clk_double_div(_hw) container_of(_hw, struct clk_double_div, hw)
  89 #define to_clk_pm_cpu(_hw) container_of(_hw, struct clk_pm_cpu, hw)
  90
  91 struct clk_periph_data {
  92         const char *name;
  93         const char * const *parent_names;
  94         int num_parents;
  95         struct clk_hw *mux_hw;
  96         struct clk_hw *rate_hw;
  97         struct clk_hw *gate_hw;
  98         struct clk_hw *muxrate_hw;
  99         bool is_double_div;
 100 };
 101
 102 static const struct clk_div_table clk_table6[] = {
 103         { .val = 1, .div = 1, },
 104         { .val = 2, .div = 2, },
 105         { .val = 3, .div = 3, },
 106         { .val = 4, .div = 4, },
 107         { .val = 5, .div = 5, },
 108         { .val = 6, .div = 6, },
 109         { .val = 0, .div = 0, }, /* last entry */
 110 };
 111
 112 static const struct clk_div_table clk_table1[] = {
 113         { .val = 0, .div = 1, },
 114         { .val = 1, .div = 2, },
 115         { .val = 0, .div = 0, }, /* last entry */
 116 };
 117
 118 static const struct clk_div_table clk_table2[] = {
 119         { .val = 0, .div = 2, },
 120         { .val = 1, .div = 4, },
 121         { .val = 0, .div = 0, }, /* last entry */
 122 };
 123
 124 static const struct clk_ops clk_double_div_ops;
 125 static const struct clk_ops clk_pm_cpu_ops;
 126
 127 #define PERIPH_GATE(_name, _bit)                \
 128 struct clk_gate gate_##_name = {                \
 129         .reg = (void *)CLK_DIS,                 \
 130         .bit_idx = _bit,                        \
 131         .hw.init = &(struct clk_init_data){     \
 132                 .ops =  &clk_gate_ops,          \
 133         }                                       \
 134 };
 135
 136 #define PERIPH_MUX(_name, _shift)               \
 137 struct clk_mux mux_##_name = {                  \
 138         .reg = (void *)TBG_SEL,                 \
 139         .shift = _shift,                        \
 140         .mask = 3,                              \
 141         .hw.init = &(struct clk_init_data){     \
 142                 .ops =  &clk_mux_ro_ops,        \
 143         }                                       \
 144 };
 145
 146 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \
 147 struct clk_double_div rate_##_name = {          \
 148         .reg1 = (void *)_reg1,                  \
 149         .reg2 = (void *)_reg2,                  \
 150         .shift1 = _shift1,                      \
 151         .shift2 = _shift2,                      \
 152         .hw.init = &(struct clk_init_data){     \
 153                 .ops =  &clk_double_div_ops,    \
 154         }                                       \
 155 };
 156
 157 #define PERIPH_DIV(_name, _reg, _shift, _table) \
 158 struct clk_divider rate_##_name = {             \
 159         .reg = (void *)_reg,                    \
 160         .table = _table,                        \
 161         .shift = _shift,                        \
 162         .hw.init = &(struct clk_init_data){     \
 163                 .ops =  &clk_divider_ro_ops,    \
 164         }                                       \
 165 };
 166
 167 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2)    \
 168 struct clk_pm_cpu muxrate_##_name = {           \
 169         .reg_mux = (void *)TBG_SEL,             \
 170         .mask_mux = 3,                          \
 171         .shift_mux = _shift1,                   \
 172         .reg_div = (void *)_reg,                \
 173         .shift_div = _shift2,                   \
 174         .hw.init = &(struct clk_init_data){     \
 175                 .ops =  &clk_pm_cpu_ops,        \
 176         }                                       \
 177 };
 178
 179 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\
 180 static PERIPH_GATE(_name, _bit);                            \
 181 static PERIPH_MUX(_name, _shift);                           \
 182 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
 183
 184 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table)     \
 185 static PERIPH_GATE(_name, _bit);                            \
 186 static PERIPH_MUX(_name, _shift);                           \
 187 static PERIPH_DIV(_name, _reg, _shift1, _table);
 188
 189 #define PERIPH_CLK_GATE_DIV(_name, _bit,  _reg, _shift, _table) \
 190 static PERIPH_GATE(_name, _bit);                        \
 191 static PERIPH_DIV(_name, _reg, _shift, _table);
 192
 193 #define PERIPH_CLK_MUX_DD(_name, _shift, _reg1, _reg2, _shift1, _shift2)\
 194 static PERIPH_MUX(_name, _shift);                           \
 195 static PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2);
 196
 197 #define REF_CLK_FULL(_name)                             \
 198         { .name = #_name,                               \
 199           .parent_names = (const char *[]){ "TBG-A-P",  \
 200               "TBG-B-P", "TBG-A-S", "TBG-B-S"},         \
 201           .num_parents = 4,                             \
 202           .mux_hw = &mux_##_name.hw,                    \
 203           .gate_hw = &gate_##_name.hw,                  \
 204           .rate_hw = &rate_##_name.hw,                  \
 205         }
 206
 207 #define REF_CLK_FULL_DD(_name)                          \
 208         { .name = #_name,                               \
 209           .parent_names = (const char *[]){ "TBG-A-P",  \
 210               "TBG-B-P", "TBG-A-S", "TBG-B-S"},         \
 211           .num_parents = 4,                             \
 212           .mux_hw = &mux_##_name.hw,                    \
 213           .gate_hw = &gate_##_name.hw,                  \
 214           .rate_hw = &rate_##_name.hw,                  \
 215           .is_double_div = true,                        \
 216         }
 217
 218 #define REF_CLK_GATE(_name, _parent_name)                       \
 219         { .name = #_name,                                       \
 220           .parent_names = (const char *[]){ _parent_name},      \
 221           .num_parents = 1,                                     \
 222           .gate_hw = &gate_##_name.hw,                          \
 223         }
 224
 225 #define REF_CLK_GATE_DIV(_name, _parent_name)                   \
 226         { .name = #_name,                                       \
 227           .parent_names = (const char *[]){ _parent_name},      \
 228           .num_parents = 1,                                     \
 229           .gate_hw = &gate_##_name.hw,                          \
 230           .rate_hw = &rate_##_name.hw,                          \
 231         }
 232
 233 #define REF_CLK_PM_CPU(_name)                           \
 234         { .name = #_name,                               \
 235           .parent_names = (const char *[]){ "TBG-A-P",  \
 236               "TBG-B-P", "TBG-A-S", "TBG-B-S"},         \
 237           .num_parents = 4,                             \
 238           .muxrate_hw = &muxrate_##_name.hw,            \
 239         }
 240
 241 #define REF_CLK_MUX_DD(_name)                           \
 242         { .name = #_name,                               \
 243           .parent_names = (const char *[]){ "TBG-A-P",  \
 244               "TBG-B-P", "TBG-A-S", "TBG-B-S"},         \
 245           .num_parents = 4,                             \
 246           .mux_hw = &mux_##_name.hw,                    \
 247           .rate_hw = &rate_##_name.hw,                  \
 248           .is_double_div = true,                        \
 249         }
 250
 251 /* NB periph clocks */
 252 PERIPH_CLK_FULL_DD(mmc, 2, 0, DIV_SEL2, DIV_SEL2, 16, 13);
 253 PERIPH_CLK_FULL_DD(sata_host, 3, 2, DIV_SEL2, DIV_SEL2, 10, 7);
 254 PERIPH_CLK_FULL_DD(sec_at, 6, 4, DIV_SEL1, DIV_SEL1, 3, 0);
 255 PERIPH_CLK_FULL_DD(sec_dap, 7, 6, DIV_SEL1, DIV_SEL1, 9, 6);
 256 PERIPH_CLK_FULL_DD(tscem, 8, 8, DIV_SEL1, DIV_SEL1, 15, 12);
 257 PERIPH_CLK_FULL(tscem_tmx, 10, 10, DIV_SEL1, 18, clk_table6);
 258 static PERIPH_GATE(avs, 11);
 259 PERIPH_CLK_FULL_DD(pwm, 13, 14, DIV_SEL0, DIV_SEL0, 3, 0);
 260 PERIPH_CLK_FULL_DD(sqf, 12, 12, DIV_SEL1, DIV_SEL1, 27, 24);
 261 static PERIPH_GATE(i2c_2, 16);
 262 static PERIPH_GATE(i2c_1, 17);
 263 PERIPH_CLK_GATE_DIV(ddr_phy, 19, DIV_SEL0, 18, clk_table2);
 264 PERIPH_CLK_FULL_DD(ddr_fclk, 21, 16, DIV_SEL0, DIV_SEL0, 15, 12);
 265 PERIPH_CLK_FULL(trace, 22, 18, DIV_SEL0, 20, clk_table6);
 266 PERIPH_CLK_FULL(counter, 23, 20, DIV_SEL0, 23, clk_table6);
 267 PERIPH_CLK_FULL_DD(eip97, 24, 24, DIV_SEL2, DIV_SEL2, 22, 19);
 268 static PERIPH_PM_CPU(cpu, 22, DIV_SEL0, 28);
 269
 270 static struct clk_periph_data data_nb[] = {
 271         REF_CLK_FULL_DD(mmc),
 272         REF_CLK_FULL_DD(sata_host),
 273         REF_CLK_FULL_DD(sec_at),
 274         REF_CLK_FULL_DD(sec_dap),
 275         REF_CLK_FULL_DD(tscem),
 276         REF_CLK_FULL(tscem_tmx),
 277         REF_CLK_GATE(avs, "xtal"),
 278         REF_CLK_FULL_DD(sqf),
 279         REF_CLK_FULL_DD(pwm),
 280         REF_CLK_GATE(i2c_2, "xtal"),
 281         REF_CLK_GATE(i2c_1, "xtal"),
 282         REF_CLK_GATE_DIV(ddr_phy, "TBG-A-S"),
 283         REF_CLK_FULL_DD(ddr_fclk),
 284         REF_CLK_FULL(trace),
 285         REF_CLK_FULL(counter),
 286         REF_CLK_FULL_DD(eip97),
 287         REF_CLK_PM_CPU(cpu),
 288         { },
 289 };
 290
 291 /* SB periph clocks */
 292 PERIPH_CLK_MUX_DD(gbe_50, 6, DIV_SEL2, DIV_SEL2, 6, 9);
 293 PERIPH_CLK_MUX_DD(gbe_core, 8, DIV_SEL1, DIV_SEL1, 18, 21);
 294 PERIPH_CLK_MUX_DD(gbe_125, 10, DIV_SEL1, DIV_SEL1, 6, 9);
 295 static PERIPH_GATE(gbe1_50, 0);
 296 static PERIPH_GATE(gbe0_50, 1);
 297 static PERIPH_GATE(gbe1_125, 2);
 298 static PERIPH_GATE(gbe0_125, 3);
 299 PERIPH_CLK_GATE_DIV(gbe1_core, 4, DIV_SEL1, 13, clk_table1);
 300 PERIPH_CLK_GATE_DIV(gbe0_core, 5, DIV_SEL1, 14, clk_table1);
 301 PERIPH_CLK_GATE_DIV(gbe_bm, 12, DIV_SEL1, 0, clk_table1);
 302 PERIPH_CLK_FULL_DD(sdio, 11, 14, DIV_SEL0, DIV_SEL0, 3, 6);
 303 PERIPH_CLK_FULL_DD(usb32_usb2_sys, 16, 16, DIV_SEL0, DIV_SEL0, 9, 12);
 304 PERIPH_CLK_FULL_DD(usb32_ss_sys, 17, 18, DIV_SEL0, DIV_SEL0, 15, 18);
 305
 306 static struct clk_periph_data data_sb[] = {
 307         REF_CLK_MUX_DD(gbe_50),
 308         REF_CLK_MUX_DD(gbe_core),
 309         REF_CLK_MUX_DD(gbe_125),
 310         REF_CLK_GATE(gbe1_50, "gbe_50"),
 311         REF_CLK_GATE(gbe0_50, "gbe_50"),
 312         REF_CLK_GATE(gbe1_125, "gbe_125"),
 313         REF_CLK_GATE(gbe0_125, "gbe_125"),
 314         REF_CLK_GATE_DIV(gbe1_core, "gbe_core"),
 315         REF_CLK_GATE_DIV(gbe0_core, "gbe_core"),
 316         REF_CLK_GATE_DIV(gbe_bm, "gbe_core"),
 317         REF_CLK_FULL_DD(sdio),
 318         REF_CLK_FULL_DD(usb32_usb2_sys),
 319         REF_CLK_FULL_DD(usb32_ss_sys),
 320         { },
 321 };
 322
 323 static unsigned int get_div(void __iomem *reg, int shift)
 324 {
 325         u32 val;
 326
 327         val = (readl(reg) >> shift) & 0x7;
 328         if (val > 6)
 329                 return 0;
 330         return val;
 331 }
 332
 333 static unsigned long clk_double_div_recalc_rate(struct clk_hw *hw,
 334                                                 unsigned long parent_rate)
 335 {
 336         struct clk_double_div *double_div = to_clk_double_div(hw);
 337         unsigned int div;
 338
 339         div = get_div(double_div->reg1, double_div->shift1);
 340         div *= get_div(double_div->reg2, double_div->shift2);
 341
 342         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
 343 }
 344
 345 static const struct clk_ops clk_double_div_ops = {
 346         .recalc_rate = clk_double_div_recalc_rate,
 347 };
 348
 349 static void armada_3700_pm_dvfs_update_regs(unsigned int load_level,
 350                                             unsigned int *reg,
 351                                             unsigned int *offset)
 352 {
 353         if (load_level <= ARMADA_37XX_DVFS_LOAD_1)
 354                 *reg = ARMADA_37XX_NB_L0L1;
 355         else
 356                 *reg = ARMADA_37XX_NB_L2L3;
 357
 358         if (load_level == ARMADA_37XX_DVFS_LOAD_0 ||
 359             load_level ==  ARMADA_37XX_DVFS_LOAD_2)
 360                 *offset += ARMADA_37XX_NB_CONFIG_SHIFT;
 361 }
 362
 363 static bool armada_3700_pm_dvfs_is_enabled(struct regmap *base)
 364 {
 365         unsigned int val, reg = ARMADA_37XX_NB_DYN_MOD;
 366
 367         if (IS_ERR(base))
 368                 return false;
 369
 370         regmap_read(base, reg, &val);
 371
 372         return !!(val & BIT(ARMADA_37XX_NB_DFS_EN));
 373 }
 374
 375 static unsigned int armada_3700_pm_dvfs_get_cpu_div(struct regmap *base)
 376 {
 377         unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
 378         unsigned int offset = ARMADA_37XX_NB_TBG_DIV_OFF;
 379         unsigned int load_level, div;
 380
 381         /*
 382          * This function is always called after the function
 383          * armada_3700_pm_dvfs_is_enabled, so no need to check again
 384          * if the base is valid.
 385          */
 386         regmap_read(base, reg, &load_level);
 387
 388         /*
 389          * The register and the offset inside this register accessed to
 390          * read the current divider depend on the load level
 391          */
 392         load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
 393         armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 394
 395         regmap_read(base, reg, &div);
 396
 397         return (div >> offset) & ARMADA_37XX_NB_TBG_DIV_MASK;
 398 }
 399
 400 static unsigned int armada_3700_pm_dvfs_get_cpu_parent(struct regmap *base)
 401 {
 402         unsigned int reg = ARMADA_37XX_NB_CPU_LOAD;
 403         unsigned int offset = ARMADA_37XX_NB_TBG_SEL_OFF;
 404         unsigned int load_level, sel;
 405
 406         /*
 407          * This function is always called after the function
 408          * armada_3700_pm_dvfs_is_enabled, so no need to check again
 409          * if the base is valid
 410          */
 411         regmap_read(base, reg, &load_level);
 412
 413         /*
 414          * The register and the offset inside this register accessed to
 415          * read the current divider depend on the load level
 416          */
 417         load_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
 418         armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 419
 420         regmap_read(base, reg, &sel);
 421
 422         return (sel >> offset) & ARMADA_37XX_NB_TBG_SEL_MASK;
 423 }
 424
 425 static u8 clk_pm_cpu_get_parent(struct clk_hw *hw)
 426 {
 427         struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
 428         u32 val;
 429
 430         if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base)) {
 431                 val = armada_3700_pm_dvfs_get_cpu_parent(pm_cpu->nb_pm_base);
 432         } else {
 433                 val = readl(pm_cpu->reg_mux) >> pm_cpu->shift_mux;
 434                 val &= pm_cpu->mask_mux;
 435         }
 436
 437         return val;
 438 }
 439
 440 static int clk_pm_cpu_set_parent(struct clk_hw *hw, u8 index)
 441 {
 442         struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
 443         struct regmap *base = pm_cpu->nb_pm_base;
 444         int load_level;
 445
 446         /*
 447          * We set the clock parent only if the DVFS is available but
 448          * not enabled.
 449          */
 450         if (IS_ERR(base) || armada_3700_pm_dvfs_is_enabled(base))
 451                 return -EINVAL;
 452
 453         /* Set the parent clock for all the load level */
 454         for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
 455                 unsigned int reg, mask,  val,
 456                         offset = ARMADA_37XX_NB_TBG_SEL_OFF;
 457
 458                 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 459
 460                 val = index << offset;
 461                 mask = ARMADA_37XX_NB_TBG_SEL_MASK << offset;
 462                 regmap_update_bits(base, reg, mask, val);
 463         }
 464         return 0;
 465 }
 466
 467 static unsigned long clk_pm_cpu_recalc_rate(struct clk_hw *hw,
 468                                             unsigned long parent_rate)
 469 {
 470         struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
 471         unsigned int div;
 472
 473         if (armada_3700_pm_dvfs_is_enabled(pm_cpu->nb_pm_base))
 474                 div = armada_3700_pm_dvfs_get_cpu_div(pm_cpu->nb_pm_base);
 475         else
 476                 div = get_div(pm_cpu->reg_div, pm_cpu->shift_div);
 477         return DIV_ROUND_UP_ULL((u64)parent_rate, div);
 478 }
 479
 480 static long clk_pm_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
 481                                   unsigned long *parent_rate)
 482 {
 483         struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
 484         struct regmap *base = pm_cpu->nb_pm_base;
 485         unsigned int div = *parent_rate / rate;
 486         unsigned int load_level;
 487         /* only available when DVFS is enabled */
 488         if (!armada_3700_pm_dvfs_is_enabled(base))
 489                 return -EINVAL;
 490
 491         for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
 492                 unsigned int reg, val, offset = ARMADA_37XX_NB_TBG_DIV_OFF;
 493
 494                 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 495
 496                 regmap_read(base, reg, &val);
 497
 498                 val >>= offset;
 499                 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
 500                 if (val == div)
 501                         /*
 502                          * We found a load level matching the target
 503                          * divider, switch to this load level and
 504                          * return.
 505                          */
 506                         return *parent_rate / div;
 507         }
 508
 509         /* We didn't find any valid divider */
 510         return -EINVAL;
 511 }
 512
 513 /*
 514  * Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
 515  * respectively) to L0 frequency (1.2 Ghz) requires a significant
 516  * amount of time to let VDD stabilize to the appropriate
 517  * voltage. This amount of time is large enough that it cannot be
 518  * covered by the hardware countdown register. Due to this, the CPU
 519  * might start operating at L0 before the voltage is stabilized,
 520  * leading to CPU stalls.
 521  *
 522  * To work around this problem, we prevent switching directly from the
 523  * L2/L3 frequencies to the L0 frequency, and instead switch to the L1
 524  * frequency in-between. The sequence therefore becomes:
 525  * 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
 526  * 2. Sleep 20ms for stabling VDD voltage
 527  * 3. Then switch from L1(600MHZ) to L0(1200Mhz).
 528  */
 529 static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
 530 {
 531         unsigned int cur_level;
 532
 533         if (rate != 1200 * 1000 * 1000)
 534                 return;
 535
 536         regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
 537         cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
 538         if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
 539                 return;
 540
 541         regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
 542                            ARMADA_37XX_NB_CPU_LOAD_MASK,
 543                            ARMADA_37XX_DVFS_LOAD_1);
 544         msleep(20);
 545 }
 546
 547 static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
 548                                unsigned long parent_rate)
 549 {
 550         struct clk_pm_cpu *pm_cpu = to_clk_pm_cpu(hw);
 551         struct regmap *base = pm_cpu->nb_pm_base;
 552         unsigned int div = parent_rate / rate;
 553         unsigned int load_level;
 554
 555         /* only available when DVFS is enabled */
 556         if (!armada_3700_pm_dvfs_is_enabled(base))
 557                 return -EINVAL;
 558
 559         for (load_level = 0; load_level < LOAD_LEVEL_NR; load_level++) {
 560                 unsigned int reg, mask, val,
 561                         offset = ARMADA_37XX_NB_TBG_DIV_OFF;
 562
 563                 armada_3700_pm_dvfs_update_regs(load_level, &reg, &offset);
 564
 565                 regmap_read(base, reg, &val);
 566                 val >>= offset;
 567                 val &= ARMADA_37XX_NB_TBG_DIV_MASK;
 568
 569                 if (val == div) {
 570                         /*
 571                          * We found a load level matching the target
 572                          * divider, switch to this load level and
 573                          * return.
 574                          */
 575                         reg = ARMADA_37XX_NB_CPU_LOAD;
 576                         mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
 577
 578                         clk_pm_cpu_set_rate_wa(rate, base);
 579
 580                         regmap_update_bits(base, reg, mask, load_level);
 581
 582                         return rate;
 583                 }
 584         }
 585
 586         /* We didn't find any valid divider */
 587         return -EINVAL;
 588 }
 589
 590 static const struct clk_ops clk_pm_cpu_ops = {
 591         .get_parent = clk_pm_cpu_get_parent,
 592         .set_parent = clk_pm_cpu_set_parent,
 593         .round_rate = clk_pm_cpu_round_rate,
 594         .set_rate = clk_pm_cpu_set_rate,
 595         .recalc_rate = clk_pm_cpu_recalc_rate,
 596 };
 597
 598 static const struct of_device_id armada_3700_periph_clock_of_match[] = {
 599         { .compatible = "marvell,armada-3700-periph-clock-nb",
 600           .data = data_nb, },
 601         { .compatible = "marvell,armada-3700-periph-clock-sb",
 602         .data = data_sb, },
 603         { }
 604 };
 605
 606 static int armada_3700_add_composite_clk(const struct clk_periph_data *data,
 607                                          void __iomem *reg, spinlock_t *lock,
 608                                          struct device *dev, struct clk_hw **hw)
 609 {
 610         const struct clk_ops *mux_ops = NULL, *gate_ops = NULL,
 611                 *rate_ops = NULL;
 612         struct clk_hw *mux_hw = NULL, *gate_hw = NULL, *rate_hw = NULL;
 613
 614         if (data->mux_hw) {
 615                 struct clk_mux *mux;
 616
 617                 mux_hw = data->mux_hw;
 618                 mux = to_clk_mux(mux_hw);
 619                 mux->lock = lock;
 620                 mux_ops = mux_hw->init->ops;
 621                 mux->reg = reg + (u64)mux->reg;
 622         }
 623
 624         if (data->gate_hw) {
 625                 struct clk_gate *gate;
 626
 627                 gate_hw = data->gate_hw;
 628                 gate = to_clk_gate(gate_hw);
 629                 gate->lock = lock;
 630                 gate_ops = gate_hw->init->ops;
 631                 gate->reg = reg + (u64)gate->reg;
 632                 gate->flags = CLK_GATE_SET_TO_DISABLE;
 633         }
 634
 635         if (data->rate_hw) {
 636                 rate_hw = data->rate_hw;
 637                 rate_ops = rate_hw->init->ops;
 638                 if (data->is_double_div) {
 639                         struct clk_double_div *rate;
 640
 641                         rate =  to_clk_double_div(rate_hw);
 642                         rate->reg1 = reg + (u64)rate->reg1;
 643                         rate->reg2 = reg + (u64)rate->reg2;
 644                 } else {
 645                         struct clk_divider *rate = to_clk_divider(rate_hw);
 646                         const struct clk_div_table *clkt;
 647                         int table_size = 0;
 648
 649                         rate->reg = reg + (u64)rate->reg;
 650                         for (clkt = rate->table; clkt->div; clkt++)
 651                                 table_size++;
 652                         rate->width = order_base_2(table_size);
 653                         rate->lock = lock;
 654                 }
 655         }
 656
 657         if (data->muxrate_hw) {
 658                 struct clk_pm_cpu *pmcpu_clk;
 659                 struct clk_hw *muxrate_hw = data->muxrate_hw;
 660                 struct regmap *map;
 661
 662                 pmcpu_clk =  to_clk_pm_cpu(muxrate_hw);
 663                 pmcpu_clk->reg_mux = reg + (u64)pmcpu_clk->reg_mux;
 664                 pmcpu_clk->reg_div = reg + (u64)pmcpu_clk->reg_div;
 665
 666                 mux_hw = muxrate_hw;
 667                 rate_hw = muxrate_hw;
 668                 mux_ops = muxrate_hw->init->ops;
 669                 rate_ops = muxrate_hw->init->ops;
 670
 671                 map = syscon_regmap_lookup_by_compatible(
 672                                 "marvell,armada-3700-nb-pm");
 673                 pmcpu_clk->nb_pm_base = map;
 674         }
 675
 676         *hw = clk_hw_register_composite(dev, data->name, data->parent_names,
 677                                         data->num_parents, mux_hw,
 678                                         mux_ops, rate_hw, rate_ops,
 679                                         gate_hw, gate_ops, CLK_IGNORE_UNUSED);
 680
 681         return PTR_ERR_OR_ZERO(*hw);
 682 }
 683
 684 static int __maybe_unused armada_3700_periph_clock_suspend(struct device *dev)
 685 {
 686         struct clk_periph_driver_data *data = dev_get_drvdata(dev);
 687
 688         data->tbg_sel = readl(data->reg + TBG_SEL);
 689         data->div_sel0 = readl(data->reg + DIV_SEL0);
 690         data->div_sel1 = readl(data->reg + DIV_SEL1);
 691         data->div_sel2 = readl(data->reg + DIV_SEL2);
 692         data->clk_sel = readl(data->reg + CLK_SEL);
 693         data->clk_dis = readl(data->reg + CLK_DIS);
 694
 695         return 0;
 696 }
 697
 698 static int __maybe_unused armada_3700_periph_clock_resume(struct device *dev)
 699 {
 700         struct clk_periph_driver_data *data = dev_get_drvdata(dev);
 701
 702         /* Follow the same order than what the Cortex-M3 does (ATF code) */
 703         writel(data->clk_dis, data->reg + CLK_DIS);
 704         writel(data->div_sel0, data->reg + DIV_SEL0);
 705         writel(data->div_sel1, data->reg + DIV_SEL1);
 706         writel(data->div_sel2, data->reg + DIV_SEL2);
 707         writel(data->tbg_sel, data->reg + TBG_SEL);
 708         writel(data->clk_sel, data->reg + CLK_SEL);
 709
 710         return 0;
 711 }
 712
 713 static const struct dev_pm_ops armada_3700_periph_clock_pm_ops = {
 714         SET_SYSTEM_SLEEP_PM_OPS(armada_3700_periph_clock_suspend,
 715                                 armada_3700_periph_clock_resume)
 716 };
 717
 718 static int armada_3700_periph_clock_probe(struct platform_device *pdev)
 719 {
 720         struct clk_periph_driver_data *driver_data;
 721         struct device_node *np = pdev->dev.of_node;
 722         const struct clk_periph_data *data;
 723         struct device *dev = &pdev->dev;
 724         int num_periph = 0, i, ret;
 725         struct resource *res;
 726
 727         data = of_device_get_match_data(dev);
 728         if (!data)
 729                 return -ENODEV;
 730
 731         while (data[num_periph].name)
 732                 num_periph++;
 733
 734         driver_data = devm_kzalloc(dev, sizeof(*driver_data), GFP_KERNEL);
 735         if (!driver_data)
 736                 return -ENOMEM;
 737
 738         driver_data->hw_data = devm_kzalloc(dev,
 739                                             struct_size(driver_data->hw_data,
 740                                                         hws, num_periph),
 741                                             GFP_KERNEL);
 742         if (!driver_data->hw_data)
 743                 return -ENOMEM;
 744         driver_data->hw_data->num = num_periph;
 745
 746         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 747         driver_data->reg = devm_ioremap_resource(dev, res);
 748         if (IS_ERR(driver_data->reg))
 749                 return PTR_ERR(driver_data->reg);
 750
 751         spin_lock_init(&driver_data->lock);
 752
 753         for (i = 0; i < num_periph; i++) {
 754                 struct clk_hw **hw = &driver_data->hw_data->hws[i];
 755                 if (armada_3700_add_composite_clk(&data[i], driver_data->reg,
 756                                                   &driver_data->lock, dev, hw))
 757                         dev_err(dev, "Can't register periph clock %s\n",
 758                                 data[i].name);
 759         }
 760
 761         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
 762                                      driver_data->hw_data);
 763         if (ret) {
 764                 for (i = 0; i < num_periph; i++)
 765                         clk_hw_unregister(driver_data->hw_data->hws[i]);
 766                 return ret;
 767         }
 768
 769         platform_set_drvdata(pdev, driver_data);
 770         return 0;
 771 }
 772
 773 static int armada_3700_periph_clock_remove(struct platform_device *pdev)
 774 {
 775         struct clk_periph_driver_data *data = platform_get_drvdata(pdev);
 776         struct clk_hw_onecell_data *hw_data = data->hw_data;
 777         int i;
 778
 779         of_clk_del_provider(pdev->dev.of_node);
 780
 781         for (i = 0; i < hw_data->num; i++)
 782                 clk_hw_unregister(hw_data->hws[i]);
 783
 784         return 0;
 785 }
 786
 787 static struct platform_driver armada_3700_periph_clock_driver = {
 788         .probe = armada_3700_periph_clock_probe,
 789         .remove = armada_3700_periph_clock_remove,
 790         .driver         = {
 791                 .name   = "marvell-armada-3700-periph-clock",
 792                 .of_match_table = armada_3700_periph_clock_of_match,
 793                 .pm     = &armada_3700_periph_clock_pm_ops,
 794         },
 795 };
 796
 797 builtin_platform_driver(armada_3700_periph_clock_driver);