drivers/clk/mvebu/ap-cpu-clk.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Marvell Armada AP CPU Clock Controller
   4  *
   5  * Copyright (C) 2018 Marvell
   6  *
   7  * Omri Itach <omrii@marvell.com>
   8  * Gregory Clement <gregory.clement@bootlin.com>
   9  */
  10
  11 #define pr_fmt(fmt) "ap-cpu-clk: " fmt
  12
  13 #include <linux/clk-provider.h>
  14 #include <linux/clk.h>
  15 #include <linux/mfd/syscon.h>
  16 #include <linux/of.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/regmap.h>
  21 #include "armada_ap_cp_helper.h"
  22
  23 #define AP806_CPU_CLUSTER0              0
  24 #define AP806_CPU_CLUSTER1              1
  25 #define AP806_CPUS_PER_CLUSTER          2
  26 #define APN806_CPU1_MASK                0x1
  27
  28 #define APN806_CLUSTER_NUM_OFFSET       8
  29 #define APN806_CLUSTER_NUM_MASK         BIT(APN806_CLUSTER_NUM_OFFSET)
  30
  31 #define APN806_MAX_DIVIDER              32
  32
  33 /**
  34  * struct cpu_dfs_regs: CPU DFS register mapping
  35  * @divider_reg: full integer ratio from PLL frequency to CPU clock frequency
  36  * @force_reg: request to force new ratio regardless of relation to other clocks
  37  * @ratio_reg: central request to switch ratios
  38  */
  39 struct cpu_dfs_regs {
  40         unsigned int divider_reg;
  41         unsigned int force_reg;
  42         unsigned int ratio_reg;
  43         unsigned int ratio_state_reg;
  44         unsigned int divider_mask;
  45         unsigned int cluster_offset;
  46         unsigned int force_mask;
  47         int divider_offset;
  48         int ratio_offset;
  49         int ratio_state_offset;
  50         int ratio_state_cluster_offset;
  51 };
  52
  53 /* AP806 CPU DFS register mapping*/
  54 #define AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET             0x278
  55 #define AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET             0x280
  56 #define AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET             0x284
  57 #define AP806_CA72MP2_0_PLL_SR_REG_OFFSET               0xC94
  58
  59 #define AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET           0x14
  60 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET         0
  61 #define AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK \
  62                         (0x3f << AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET)
  63 #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET      24
  64 #define AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK \
  65                         (0x1 << AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_OFFSET)
  66 #define AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET      16
  67 #define AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET 0
  68 #define AP806_CA72MP2_0_PLL_RATIO_STATE                 11
  69
  70 #define STATUS_POLL_PERIOD_US           1
  71 #define STATUS_POLL_TIMEOUT_US          1000000
  72
  73 #define to_ap_cpu_clk(_hw) container_of(_hw, struct ap_cpu_clk, hw)
  74
  75 static const struct cpu_dfs_regs ap806_dfs_regs = {
  76         .divider_reg = AP806_CA72MP2_0_PLL_CR_0_REG_OFFSET,
  77         .force_reg = AP806_CA72MP2_0_PLL_CR_1_REG_OFFSET,
  78         .ratio_reg = AP806_CA72MP2_0_PLL_CR_2_REG_OFFSET,
  79         .ratio_state_reg = AP806_CA72MP2_0_PLL_SR_REG_OFFSET,
  80         .divider_mask = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_MASK,
  81         .cluster_offset = AP806_CA72MP2_0_PLL_CR_CLUSTER_OFFSET,
  82         .force_mask = AP806_PLL_CR_0_CPU_CLK_RELOAD_FORCE_MASK,
  83         .divider_offset = AP806_PLL_CR_0_CPU_CLK_DIV_RATIO_OFFSET,
  84         .ratio_offset = AP806_PLL_CR_0_CPU_CLK_RELOAD_RATIO_OFFSET,
  85         .ratio_state_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
  86         .ratio_state_cluster_offset = AP806_CA72MP2_0_PLL_RATIO_STABLE_OFFSET,
  87 };
  88
  89 /*
  90  * struct ap806_clk: CPU cluster clock controller instance
  91  * @cluster: Cluster clock controller index
  92  * @clk_name: Cluster clock controller name
  93  * @dev : Cluster clock device
  94  * @hw: HW specific structure of Cluster clock controller
  95  * @pll_cr_base: CA72MP2 Register base (Device Sample at Reset register)
  96  */
  97 struct ap_cpu_clk {
  98         unsigned int cluster;
  99         const char *clk_name;
 100         struct device *dev;
 101         struct clk_hw hw;
 102         struct regmap *pll_cr_base;
 103         const struct cpu_dfs_regs *pll_regs;
 104 };
 105
 106 static unsigned long ap_cpu_clk_recalc_rate(struct clk_hw *hw,
 107                                             unsigned long parent_rate)
 108 {
 109         struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
 110         unsigned int cpu_clkdiv_reg;
 111         int cpu_clkdiv_ratio;
 112
 113         cpu_clkdiv_reg = clk->pll_regs->divider_reg +
 114                 (clk->cluster * clk->pll_regs->cluster_offset);
 115         regmap_read(clk->pll_cr_base, cpu_clkdiv_reg, &cpu_clkdiv_ratio);
 116         cpu_clkdiv_ratio &= clk->pll_regs->divider_mask;
 117         cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset;
 118
 119         return parent_rate / cpu_clkdiv_ratio;
 120 }
 121
 122 static int ap_cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 123                                unsigned long parent_rate)
 124 {
 125         struct ap_cpu_clk *clk = to_ap_cpu_clk(hw);
 126         int ret, reg, divider = parent_rate / rate;
 127         unsigned int cpu_clkdiv_reg, cpu_force_reg, cpu_ratio_reg, stable_bit;
 128
 129         cpu_clkdiv_reg = clk->pll_regs->divider_reg +
 130                 (clk->cluster * clk->pll_regs->cluster_offset);
 131         cpu_force_reg = clk->pll_regs->force_reg +
 132                 (clk->cluster * clk->pll_regs->cluster_offset);
 133         cpu_ratio_reg = clk->pll_regs->ratio_reg +
 134                 (clk->cluster * clk->pll_regs->cluster_offset);
 135
 136         regmap_update_bits(clk->pll_cr_base, cpu_clkdiv_reg,
 137                            clk->pll_regs->divider_mask, divider);
 138
 139         regmap_update_bits(clk->pll_cr_base, cpu_force_reg,
 140                            clk->pll_regs->force_mask,
 141                            clk->pll_regs->force_mask);
 142
 143         regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
 144                            BIT(clk->pll_regs->ratio_offset),
 145                            BIT(clk->pll_regs->ratio_offset));
 146
 147         stable_bit = BIT(clk->pll_regs->ratio_state_offset +
 148                          clk->cluster *
 149                          clk->pll_regs->ratio_state_cluster_offset),
 150         ret = regmap_read_poll_timeout(clk->pll_cr_base,
 151                                        clk->pll_regs->ratio_state_reg, reg,
 152                                        reg & stable_bit, STATUS_POLL_PERIOD_US,
 153                                        STATUS_POLL_TIMEOUT_US);
 154         if (ret)
 155                 return ret;
 156
 157         regmap_update_bits(clk->pll_cr_base, cpu_ratio_reg,
 158                            BIT(clk->pll_regs->ratio_offset), 0);
 159
 160         return 0;
 161 }
 162
 163 static long ap_cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 164                                   unsigned long *parent_rate)
 165 {
 166         int divider = *parent_rate / rate;
 167
 168         divider = min(divider, APN806_MAX_DIVIDER);
 169
 170         return *parent_rate / divider;
 171 }
 172
 173 static const struct clk_ops ap_cpu_clk_ops = {
 174         .recalc_rate    = ap_cpu_clk_recalc_rate,
 175         .round_rate     = ap_cpu_clk_round_rate,
 176         .set_rate       = ap_cpu_clk_set_rate,
 177 };
 178
 179 static int ap_cpu_clock_probe(struct platform_device *pdev)
 180 {
 181         int ret, nclusters = 0, cluster_index = 0;
 182         struct device *dev = &pdev->dev;
 183         struct device_node *dn, *np = dev->of_node;
 184         struct clk_hw_onecell_data *ap_cpu_data;
 185         struct ap_cpu_clk *ap_cpu_clk;
 186         struct regmap *regmap;
 187
 188         regmap = syscon_node_to_regmap(np->parent);
 189         if (IS_ERR(regmap)) {
 190                 pr_err("cannot get pll_cr_base regmap\n");
 191                 return PTR_ERR(regmap);
 192         }
 193
 194         /*
 195          * AP806 has 4 cpus and DFS for AP806 is controlled per
 196          * cluster (2 CPUs per cluster), cpu0 and cpu1 are fixed to
 197          * cluster0 while cpu2 and cpu3 are fixed to cluster1 whether
 198          * they are enabled or not.  Since cpu0 is the boot cpu, then
 199          * cluster0 must exist.  If cpu2 or cpu3 is enabled, cluster1
 200          * will exist and the cluster number is 2; otherwise the
 201          * cluster number is 1.
 202          */
 203         nclusters = 1;
 204         for_each_of_cpu_node(dn) {
 205                 int cpu, err;
 206
 207                 err = of_property_read_u32(dn, "reg", &cpu);
 208                 if (WARN_ON(err))
 209                         return err;
 210
 211                 /* If cpu2 or cpu3 is enabled */
 212                 if (cpu & APN806_CLUSTER_NUM_MASK) {
 213                         nclusters = 2;
 214                         break;
 215                 }
 216         }
 217         /*
 218          * DFS for AP806 is controlled per cluster (2 CPUs per cluster),
 219          * so allocate structs per cluster
 220          */
 221         ap_cpu_clk = devm_kcalloc(dev, nclusters, sizeof(*ap_cpu_clk),
 222                                   GFP_KERNEL);
 223         if (!ap_cpu_clk)
 224                 return -ENOMEM;
 225
 226         ap_cpu_data = devm_kzalloc(dev, sizeof(*ap_cpu_data) +
 227                                 sizeof(struct clk_hw *) * nclusters,
 228                                 GFP_KERNEL);
 229         if (!ap_cpu_data)
 230                 return -ENOMEM;
 231
 232         for_each_of_cpu_node(dn) {
 233                 char *clk_name = "cpu-cluster-0";
 234                 struct clk_init_data init;
 235                 const char *parent_name;
 236                 struct clk *parent;
 237                 int cpu, err;
 238
 239                 err = of_property_read_u32(dn, "reg", &cpu);
 240                 if (WARN_ON(err))
 241                         return err;
 242
 243                 cluster_index = cpu & APN806_CLUSTER_NUM_MASK;
 244                 cluster_index >>= APN806_CLUSTER_NUM_OFFSET;
 245
 246                 /* Initialize once for one cluster */
 247                 if (ap_cpu_data->hws[cluster_index])
 248                         continue;
 249
 250                 parent = of_clk_get(np, cluster_index);
 251                 if (IS_ERR(parent)) {
 252                         dev_err(dev, "Could not get the clock parent\n");
 253                         return -EINVAL;
 254                 }
 255                 parent_name =  __clk_get_name(parent);
 256                 clk_name[12] += cluster_index;
 257                 ap_cpu_clk[cluster_index].clk_name =
 258                         ap_cp_unique_name(dev, np->parent, clk_name);
 259                 ap_cpu_clk[cluster_index].cluster = cluster_index;
 260                 ap_cpu_clk[cluster_index].pll_cr_base = regmap;
 261                 ap_cpu_clk[cluster_index].hw.init = &init;
 262                 ap_cpu_clk[cluster_index].dev = dev;
 263                 ap_cpu_clk[cluster_index].pll_regs = of_device_get_match_data(&pdev->dev);
 264
 265                 init.name = ap_cpu_clk[cluster_index].clk_name;
 266                 init.ops = &ap_cpu_clk_ops;
 267                 init.num_parents = 1;
 268                 init.parent_names = &parent_name;
 269
 270                 ret = devm_clk_hw_register(dev, &ap_cpu_clk[cluster_index].hw);
 271                 if (ret)
 272                         return ret;
 273                 ap_cpu_data->hws[cluster_index] = &ap_cpu_clk[cluster_index].hw;
 274         }
 275
 276         ap_cpu_data->num = cluster_index + 1;
 277
 278         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, ap_cpu_data);
 279         if (ret)
 280                 dev_err(dev, "failed to register OF clock provider\n");
 281
 282         return ret;
 283 }
 284
 285 static const struct of_device_id ap_cpu_clock_of_match[] = {
 286         {
 287                 .compatible = "marvell,ap806-cpu-clock",
 288                 .data = &ap806_dfs_regs,
 289         },
 290         { }
 291 };
 292
 293 static struct platform_driver ap_cpu_clock_driver = {
 294         .probe = ap_cpu_clock_probe,
 295         .driver         = {
 296                 .name   = "marvell-ap-cpu-clock",
 297                 .of_match_table = ap_cpu_clock_of_match,
 298                 .suppress_bind_attrs = true,
 299         },
 300 };
 301 builtin_platform_driver(ap_cpu_clock_driver);