1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_MMP_CLK_H
3 #define __MACH_MMP_CLK_H
5 #include <linux/clk-provider.h>
6 #include <linux/clkdev.h>
8 #define APBC_NO_BUS_CTRL BIT(0)
9 #define APBC_POWER_CTRL BIT(1)
12 /* Clock type "factor" */
13 struct mmp_clk_factor_masks {
15 unsigned int num_mask;
16 unsigned int den_mask;
17 unsigned int num_shift;
18 unsigned int den_shift;
21 struct mmp_clk_factor_tbl {
26 struct mmp_clk_factor {
29 struct mmp_clk_factor_masks *masks;
30 struct mmp_clk_factor_tbl *ftbl;
31 unsigned int ftbl_cnt;
35 extern struct clk *mmp_clk_register_factor(const char *name,
36 const char *parent_name, unsigned long flags,
37 void __iomem *base, struct mmp_clk_factor_masks *masks,
38 struct mmp_clk_factor_tbl *ftbl, unsigned int ftbl_cnt,
41 /* Clock type "mix" */
42 #define MMP_CLK_BITS_MASK(width, shift) \
43 (((1 << (width)) - 1) << (shift))
44 #define MMP_CLK_BITS_GET_VAL(data, width, shift) \
45 ((data & MMP_CLK_BITS_MASK(width, shift)) >> (shift))
46 #define MMP_CLK_BITS_SET_VAL(val, width, shift) \
47 (((val) << (shift)) & MMP_CLK_BITS_MASK(width, shift))
55 /* The register layout */
56 struct mmp_clk_mix_reg_info {
57 void __iomem *reg_clk_ctrl;
58 void __iomem *reg_clk_sel;
66 /* The suggested clock table from user. */
67 struct mmp_clk_mix_clk_table {
74 struct mmp_clk_mix_config {
75 struct mmp_clk_mix_reg_info reg_info;
76 struct mmp_clk_mix_clk_table *table;
77 unsigned int table_size;
79 struct clk_div_table *div_table;
86 struct mmp_clk_mix_reg_info reg_info;
87 struct mmp_clk_mix_clk_table *table;
89 struct clk_div_table *div_table;
90 unsigned int table_size;
97 extern const struct clk_ops mmp_clk_mix_ops;
98 extern struct clk *mmp_clk_register_mix(struct device *dev,
100 const char * const *parent_names,
103 struct mmp_clk_mix_config *config,
107 /* Clock type "gate". MMP private gate */
108 #define MMP_CLK_GATE_NEED_DELAY BIT(0)
110 struct mmp_clk_gate {
120 extern const struct clk_ops mmp_clk_gate_ops;
121 extern struct clk *mmp_clk_register_gate(struct device *dev, const char *name,
122 const char *parent_name, unsigned long flags,
123 void __iomem *reg, u32 mask, u32 val_enable,
124 u32 val_disable, unsigned int gate_flags,
127 extern struct clk *mmp_clk_register_apbc(const char *name,
128 const char *parent_name, void __iomem *base,
129 unsigned int delay, unsigned int apbc_flags, spinlock_t *lock);
130 extern struct clk *mmp_clk_register_apmu(const char *name,
131 const char *parent_name, void __iomem *base, u32 enable_mask,
134 struct mmp_clk_unit {
135 unsigned int nr_clks;
136 struct clk **clk_table;
137 struct clk_onecell_data clk_data;
140 struct mmp_param_fixed_rate_clk {
143 const char *parent_name;
145 unsigned long fixed_rate;
147 void mmp_register_fixed_rate_clks(struct mmp_clk_unit *unit,
148 struct mmp_param_fixed_rate_clk *clks,
151 struct mmp_param_fixed_factor_clk {
154 const char *parent_name;
159 void mmp_register_fixed_factor_clks(struct mmp_clk_unit *unit,
160 struct mmp_param_fixed_factor_clk *clks,
163 struct mmp_param_general_gate_clk {
166 const char *parent_name;
168 unsigned long offset;
173 void mmp_register_general_gate_clks(struct mmp_clk_unit *unit,
174 struct mmp_param_general_gate_clk *clks,
175 void __iomem *base, int size);
177 struct mmp_param_gate_clk {
180 const char *parent_name;
182 unsigned long offset;
186 unsigned int gate_flags;
189 void mmp_register_gate_clks(struct mmp_clk_unit *unit,
190 struct mmp_param_gate_clk *clks,
191 void __iomem *base, int size);
193 struct mmp_param_mux_clk {
196 const char * const *parent_name;
199 unsigned long offset;
205 void mmp_register_mux_clks(struct mmp_clk_unit *unit,
206 struct mmp_param_mux_clk *clks,
207 void __iomem *base, int size);
209 struct mmp_param_div_clk {
212 const char *parent_name;
214 unsigned long offset;
220 void mmp_register_div_clks(struct mmp_clk_unit *unit,
221 struct mmp_param_div_clk *clks,
222 void __iomem *base, int size);
224 struct mmp_param_pll_clk {
227 unsigned long default_rate;
228 unsigned long enable_offset;
230 unsigned long offset;
233 unsigned long input_rate;
234 unsigned long postdiv_offset;
235 unsigned long postdiv_shift;
237 void mmp_register_pll_clks(struct mmp_clk_unit *unit,
238 struct mmp_param_pll_clk *clks,
239 void __iomem *base, int size);
241 extern struct clk *mmp_clk_register_pll(char *name,
242 unsigned long default_rate,
243 void __iomem *enable_reg, u32 enable,
244 void __iomem *reg, u8 shift,
245 unsigned long input_rate,
246 void __iomem *postdiv_reg, u8 postdiv_shift);
248 #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc) \
250 .width_div = (w_d), \
251 .shift_div = (s_d), \
252 .width_mux = (w_m), \
253 .shift_mux = (s_m), \
257 void mmp_clk_init(struct device_node *np, struct mmp_clk_unit *unit,
259 void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,