drivers/clk/meson/meson8b.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015 Endless Mobile, Inc.
   4  * Author: Carlo Caione <carlo@endlessm.com>
   5  *
   6  * Copyright (c) 2016 BayLibre, Inc.
   7  * Michael Turquette <mturquette@baylibre.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/init.h>
  13 #include <linux/mfd/syscon.h>
  14 #include <linux/of_address.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17 #include <linux/regmap.h>
  18
  19 #include "meson8b.h"
  20 #include "clk-regmap.h"
  21 #include "clk-pll.h"
  22 #include "clk-mpll.h"
  23
  24 static DEFINE_SPINLOCK(meson_clk_lock);
  25
  26 struct meson8b_clk_reset {
  27         struct reset_controller_dev reset;
  28         struct regmap *regmap;
  29 };
  30
  31 static const struct pll_params_table sys_pll_params_table[] = {
  32         PLL_PARAMS(50, 1),
  33         PLL_PARAMS(51, 1),
  34         PLL_PARAMS(52, 1),
  35         PLL_PARAMS(53, 1),
  36         PLL_PARAMS(54, 1),
  37         PLL_PARAMS(55, 1),
  38         PLL_PARAMS(56, 1),
  39         PLL_PARAMS(57, 1),
  40         PLL_PARAMS(58, 1),
  41         PLL_PARAMS(59, 1),
  42         PLL_PARAMS(60, 1),
  43         PLL_PARAMS(61, 1),
  44         PLL_PARAMS(62, 1),
  45         PLL_PARAMS(63, 1),
  46         PLL_PARAMS(64, 1),
  47         PLL_PARAMS(65, 1),
  48         PLL_PARAMS(66, 1),
  49         PLL_PARAMS(67, 1),
  50         PLL_PARAMS(68, 1),
  51         PLL_PARAMS(84, 1),
  52         { /* sentinel */ },
  53 };
  54
  55 static struct clk_regmap meson8b_fixed_pll_dco = {
  56         .data = &(struct meson_clk_pll_data){
  57                 .en = {
  58                         .reg_off = HHI_MPLL_CNTL,
  59                         .shift   = 30,
  60                         .width   = 1,
  61                 },
  62                 .m = {
  63                         .reg_off = HHI_MPLL_CNTL,
  64                         .shift   = 0,
  65                         .width   = 9,
  66                 },
  67                 .n = {
  68                         .reg_off = HHI_MPLL_CNTL,
  69                         .shift   = 9,
  70                         .width   = 5,
  71                 },
  72                 .frac = {
  73                         .reg_off = HHI_MPLL_CNTL2,
  74                         .shift   = 0,
  75                         .width   = 12,
  76                 },
  77                 .l = {
  78                         .reg_off = HHI_MPLL_CNTL,
  79                         .shift   = 31,
  80                         .width   = 1,
  81                 },
  82                 .rst = {
  83                         .reg_off = HHI_MPLL_CNTL,
  84                         .shift   = 29,
  85                         .width   = 1,
  86                 },
  87         },
  88         .hw.init = &(struct clk_init_data){
  89                 .name = "fixed_pll_dco",
  90                 .ops = &meson_clk_pll_ro_ops,
  91                 .parent_data = &(const struct clk_parent_data) {
  92                         .fw_name = "xtal",
  93                         .name = "xtal",
  94                         .index = -1,
  95                 },
  96                 .num_parents = 1,
  97         },
  98 };
  99
 100 static struct clk_regmap meson8b_fixed_pll = {
 101         .data = &(struct clk_regmap_div_data){
 102                 .offset = HHI_MPLL_CNTL,
 103                 .shift = 16,
 104                 .width = 2,
 105                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 106         },
 107         .hw.init = &(struct clk_init_data){
 108                 .name = "fixed_pll",
 109                 .ops = &clk_regmap_divider_ro_ops,
 110                 .parent_hws = (const struct clk_hw *[]) {
 111                         &meson8b_fixed_pll_dco.hw
 112                 },
 113                 .num_parents = 1,
 114                 /*
 115                  * This clock won't ever change at runtime so
 116                  * CLK_SET_RATE_PARENT is not required
 117                  */
 118         },
 119 };
 120
 121 static struct clk_regmap meson8b_hdmi_pll_dco = {
 122         .data = &(struct meson_clk_pll_data){
 123                 .en = {
 124                         .reg_off = HHI_VID_PLL_CNTL,
 125                         .shift   = 30,
 126                         .width   = 1,
 127                 },
 128                 .m = {
 129                         .reg_off = HHI_VID_PLL_CNTL,
 130                         .shift   = 0,
 131                         .width   = 9,
 132                 },
 133                 .n = {
 134                         .reg_off = HHI_VID_PLL_CNTL,
 135                         .shift   = 10,
 136                         .width   = 5,
 137                 },
 138                 .frac = {
 139                         .reg_off = HHI_VID_PLL_CNTL2,
 140                         .shift   = 0,
 141                         .width   = 12,
 142                 },
 143                 .l = {
 144                         .reg_off = HHI_VID_PLL_CNTL,
 145                         .shift   = 31,
 146                         .width   = 1,
 147                 },
 148                 .rst = {
 149                         .reg_off = HHI_VID_PLL_CNTL,
 150                         .shift   = 29,
 151                         .width   = 1,
 152                 },
 153         },
 154         .hw.init = &(struct clk_init_data){
 155                 /* sometimes also called "HPLL" or "HPLL PLL" */
 156                 .name = "hdmi_pll_dco",
 157                 .ops = &meson_clk_pll_ro_ops,
 158                 .parent_data = &(const struct clk_parent_data) {
 159                         .fw_name = "xtal",
 160                         .name = "xtal",
 161                         .index = -1,
 162                 },
 163                 .num_parents = 1,
 164         },
 165 };
 166
 167 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
 168         .data = &(struct clk_regmap_div_data){
 169                 .offset = HHI_VID_PLL_CNTL,
 170                 .shift = 16,
 171                 .width = 2,
 172                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 173         },
 174         .hw.init = &(struct clk_init_data){
 175                 .name = "hdmi_pll_lvds_out",
 176                 .ops = &clk_regmap_divider_ro_ops,
 177                 .parent_hws = (const struct clk_hw *[]) {
 178                         &meson8b_hdmi_pll_dco.hw
 179                 },
 180                 .num_parents = 1,
 181                 .flags = CLK_SET_RATE_PARENT,
 182         },
 183 };
 184
 185 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
 186         .data = &(struct clk_regmap_div_data){
 187                 .offset = HHI_VID_PLL_CNTL,
 188                 .shift = 18,
 189                 .width = 2,
 190                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 191         },
 192         .hw.init = &(struct clk_init_data){
 193                 .name = "hdmi_pll_hdmi_out",
 194                 .ops = &clk_regmap_divider_ro_ops,
 195                 .parent_hws = (const struct clk_hw *[]) {
 196                         &meson8b_hdmi_pll_dco.hw
 197                 },
 198                 .num_parents = 1,
 199                 .flags = CLK_SET_RATE_PARENT,
 200         },
 201 };
 202
 203 static struct clk_regmap meson8b_sys_pll_dco = {
 204         .data = &(struct meson_clk_pll_data){
 205                 .en = {
 206                         .reg_off = HHI_SYS_PLL_CNTL,
 207                         .shift   = 30,
 208                         .width   = 1,
 209                 },
 210                 .m = {
 211                         .reg_off = HHI_SYS_PLL_CNTL,
 212                         .shift   = 0,
 213                         .width   = 9,
 214                 },
 215                 .n = {
 216                         .reg_off = HHI_SYS_PLL_CNTL,
 217                         .shift   = 9,
 218                         .width   = 5,
 219                 },
 220                 .l = {
 221                         .reg_off = HHI_SYS_PLL_CNTL,
 222                         .shift   = 31,
 223                         .width   = 1,
 224                 },
 225                 .rst = {
 226                         .reg_off = HHI_SYS_PLL_CNTL,
 227                         .shift   = 29,
 228                         .width   = 1,
 229                 },
 230                 .table = sys_pll_params_table,
 231         },
 232         .hw.init = &(struct clk_init_data){
 233                 .name = "sys_pll_dco",
 234                 .ops = &meson_clk_pll_ops,
 235                 .parent_data = &(const struct clk_parent_data) {
 236                         .fw_name = "xtal",
 237                         .name = "xtal",
 238                         .index = -1,
 239                 },
 240                 .num_parents = 1,
 241         },
 242 };
 243
 244 static struct clk_regmap meson8b_sys_pll = {
 245         .data = &(struct clk_regmap_div_data){
 246                 .offset = HHI_SYS_PLL_CNTL,
 247                 .shift = 16,
 248                 .width = 2,
 249                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 250         },
 251         .hw.init = &(struct clk_init_data){
 252                 .name = "sys_pll",
 253                 .ops = &clk_regmap_divider_ops,
 254                 .parent_hws = (const struct clk_hw *[]) {
 255                         &meson8b_sys_pll_dco.hw
 256                 },
 257                 .num_parents = 1,
 258                 .flags = CLK_SET_RATE_PARENT,
 259         },
 260 };
 261
 262 static struct clk_fixed_factor meson8b_fclk_div2_div = {
 263         .mult = 1,
 264         .div = 2,
 265         .hw.init = &(struct clk_init_data){
 266                 .name = "fclk_div2_div",
 267                 .ops = &clk_fixed_factor_ops,
 268                 .parent_hws = (const struct clk_hw *[]) {
 269                         &meson8b_fixed_pll.hw
 270                 },
 271                 .num_parents = 1,
 272         },
 273 };
 274
 275 static struct clk_regmap meson8b_fclk_div2 = {
 276         .data = &(struct clk_regmap_gate_data){
 277                 .offset = HHI_MPLL_CNTL6,
 278                 .bit_idx = 27,
 279         },
 280         .hw.init = &(struct clk_init_data){
 281                 .name = "fclk_div2",
 282                 .ops = &clk_regmap_gate_ops,
 283                 .parent_hws = (const struct clk_hw *[]) {
 284                         &meson8b_fclk_div2_div.hw
 285                 },
 286                 .num_parents = 1,
 287         },
 288 };
 289
 290 static struct clk_fixed_factor meson8b_fclk_div3_div = {
 291         .mult = 1,
 292         .div = 3,
 293         .hw.init = &(struct clk_init_data){
 294                 .name = "fclk_div3_div",
 295                 .ops = &clk_fixed_factor_ops,
 296                 .parent_hws = (const struct clk_hw *[]) {
 297                         &meson8b_fixed_pll.hw
 298                 },
 299                 .num_parents = 1,
 300         },
 301 };
 302
 303 static struct clk_regmap meson8b_fclk_div3 = {
 304         .data = &(struct clk_regmap_gate_data){
 305                 .offset = HHI_MPLL_CNTL6,
 306                 .bit_idx = 28,
 307         },
 308         .hw.init = &(struct clk_init_data){
 309                 .name = "fclk_div3",
 310                 .ops = &clk_regmap_gate_ops,
 311                 .parent_hws = (const struct clk_hw *[]) {
 312                         &meson8b_fclk_div3_div.hw
 313                 },
 314                 .num_parents = 1,
 315         },
 316 };
 317
 318 static struct clk_fixed_factor meson8b_fclk_div4_div = {
 319         .mult = 1,
 320         .div = 4,
 321         .hw.init = &(struct clk_init_data){
 322                 .name = "fclk_div4_div",
 323                 .ops = &clk_fixed_factor_ops,
 324                 .parent_hws = (const struct clk_hw *[]) {
 325                         &meson8b_fixed_pll.hw
 326                 },
 327                 .num_parents = 1,
 328         },
 329 };
 330
 331 static struct clk_regmap meson8b_fclk_div4 = {
 332         .data = &(struct clk_regmap_gate_data){
 333                 .offset = HHI_MPLL_CNTL6,
 334                 .bit_idx = 29,
 335         },
 336         .hw.init = &(struct clk_init_data){
 337                 .name = "fclk_div4",
 338                 .ops = &clk_regmap_gate_ops,
 339                 .parent_hws = (const struct clk_hw *[]) {
 340                         &meson8b_fclk_div4_div.hw
 341                 },
 342                 .num_parents = 1,
 343         },
 344 };
 345
 346 static struct clk_fixed_factor meson8b_fclk_div5_div = {
 347         .mult = 1,
 348         .div = 5,
 349         .hw.init = &(struct clk_init_data){
 350                 .name = "fclk_div5_div",
 351                 .ops = &clk_fixed_factor_ops,
 352                 .parent_hws = (const struct clk_hw *[]) {
 353                         &meson8b_fixed_pll.hw
 354                 },
 355                 .num_parents = 1,
 356         },
 357 };
 358
 359 static struct clk_regmap meson8b_fclk_div5 = {
 360         .data = &(struct clk_regmap_gate_data){
 361                 .offset = HHI_MPLL_CNTL6,
 362                 .bit_idx = 30,
 363         },
 364         .hw.init = &(struct clk_init_data){
 365                 .name = "fclk_div5",
 366                 .ops = &clk_regmap_gate_ops,
 367                 .parent_hws = (const struct clk_hw *[]) {
 368                         &meson8b_fclk_div5_div.hw
 369                 },
 370                 .num_parents = 1,
 371         },
 372 };
 373
 374 static struct clk_fixed_factor meson8b_fclk_div7_div = {
 375         .mult = 1,
 376         .div = 7,
 377         .hw.init = &(struct clk_init_data){
 378                 .name = "fclk_div7_div",
 379                 .ops = &clk_fixed_factor_ops,
 380                 .parent_hws = (const struct clk_hw *[]) {
 381                         &meson8b_fixed_pll.hw
 382                 },
 383                 .num_parents = 1,
 384         },
 385 };
 386
 387 static struct clk_regmap meson8b_fclk_div7 = {
 388         .data = &(struct clk_regmap_gate_data){
 389                 .offset = HHI_MPLL_CNTL6,
 390                 .bit_idx = 31,
 391         },
 392         .hw.init = &(struct clk_init_data){
 393                 .name = "fclk_div7",
 394                 .ops = &clk_regmap_gate_ops,
 395                 .parent_hws = (const struct clk_hw *[]) {
 396                         &meson8b_fclk_div7_div.hw
 397                 },
 398                 .num_parents = 1,
 399         },
 400 };
 401
 402 static struct clk_regmap meson8b_mpll_prediv = {
 403         .data = &(struct clk_regmap_div_data){
 404                 .offset = HHI_MPLL_CNTL5,
 405                 .shift = 12,
 406                 .width = 1,
 407         },
 408         .hw.init = &(struct clk_init_data){
 409                 .name = "mpll_prediv",
 410                 .ops = &clk_regmap_divider_ro_ops,
 411                 .parent_hws = (const struct clk_hw *[]) {
 412                         &meson8b_fixed_pll.hw
 413                 },
 414                 .num_parents = 1,
 415         },
 416 };
 417
 418 static struct clk_regmap meson8b_mpll0_div = {
 419         .data = &(struct meson_clk_mpll_data){
 420                 .sdm = {
 421                         .reg_off = HHI_MPLL_CNTL7,
 422                         .shift   = 0,
 423                         .width   = 14,
 424                 },
 425                 .sdm_en = {
 426                         .reg_off = HHI_MPLL_CNTL7,
 427                         .shift   = 15,
 428                         .width   = 1,
 429                 },
 430                 .n2 = {
 431                         .reg_off = HHI_MPLL_CNTL7,
 432                         .shift   = 16,
 433                         .width   = 9,
 434                 },
 435                 .ssen = {
 436                         .reg_off = HHI_MPLL_CNTL,
 437                         .shift   = 25,
 438                         .width   = 1,
 439                 },
 440                 .lock = &meson_clk_lock,
 441         },
 442         .hw.init = &(struct clk_init_data){
 443                 .name = "mpll0_div",
 444                 .ops = &meson_clk_mpll_ops,
 445                 .parent_hws = (const struct clk_hw *[]) {
 446                         &meson8b_mpll_prediv.hw
 447                 },
 448                 .num_parents = 1,
 449         },
 450 };
 451
 452 static struct clk_regmap meson8b_mpll0 = {
 453         .data = &(struct clk_regmap_gate_data){
 454                 .offset = HHI_MPLL_CNTL7,
 455                 .bit_idx = 14,
 456         },
 457         .hw.init = &(struct clk_init_data){
 458                 .name = "mpll0",
 459                 .ops = &clk_regmap_gate_ops,
 460                 .parent_hws = (const struct clk_hw *[]) {
 461                         &meson8b_mpll0_div.hw
 462                 },
 463                 .num_parents = 1,
 464                 .flags = CLK_SET_RATE_PARENT,
 465         },
 466 };
 467
 468 static struct clk_regmap meson8b_mpll1_div = {
 469         .data = &(struct meson_clk_mpll_data){
 470                 .sdm = {
 471                         .reg_off = HHI_MPLL_CNTL8,
 472                         .shift   = 0,
 473                         .width   = 14,
 474                 },
 475                 .sdm_en = {
 476                         .reg_off = HHI_MPLL_CNTL8,
 477                         .shift   = 15,
 478                         .width   = 1,
 479                 },
 480                 .n2 = {
 481                         .reg_off = HHI_MPLL_CNTL8,
 482                         .shift   = 16,
 483                         .width   = 9,
 484                 },
 485                 .lock = &meson_clk_lock,
 486         },
 487         .hw.init = &(struct clk_init_data){
 488                 .name = "mpll1_div",
 489                 .ops = &meson_clk_mpll_ops,
 490                 .parent_hws = (const struct clk_hw *[]) {
 491                         &meson8b_mpll_prediv.hw
 492                 },
 493                 .num_parents = 1,
 494         },
 495 };
 496
 497 static struct clk_regmap meson8b_mpll1 = {
 498         .data = &(struct clk_regmap_gate_data){
 499                 .offset = HHI_MPLL_CNTL8,
 500                 .bit_idx = 14,
 501         },
 502         .hw.init = &(struct clk_init_data){
 503                 .name = "mpll1",
 504                 .ops = &clk_regmap_gate_ops,
 505                 .parent_hws = (const struct clk_hw *[]) {
 506                         &meson8b_mpll1_div.hw
 507                 },
 508                 .num_parents = 1,
 509                 .flags = CLK_SET_RATE_PARENT,
 510         },
 511 };
 512
 513 static struct clk_regmap meson8b_mpll2_div = {
 514         .data = &(struct meson_clk_mpll_data){
 515                 .sdm = {
 516                         .reg_off = HHI_MPLL_CNTL9,
 517                         .shift   = 0,
 518                         .width   = 14,
 519                 },
 520                 .sdm_en = {
 521                         .reg_off = HHI_MPLL_CNTL9,
 522                         .shift   = 15,
 523                         .width   = 1,
 524                 },
 525                 .n2 = {
 526                         .reg_off = HHI_MPLL_CNTL9,
 527                         .shift   = 16,
 528                         .width   = 9,
 529                 },
 530                 .lock = &meson_clk_lock,
 531         },
 532         .hw.init = &(struct clk_init_data){
 533                 .name = "mpll2_div",
 534                 .ops = &meson_clk_mpll_ops,
 535                 .parent_hws = (const struct clk_hw *[]) {
 536                         &meson8b_mpll_prediv.hw
 537                 },
 538                 .num_parents = 1,
 539         },
 540 };
 541
 542 static struct clk_regmap meson8b_mpll2 = {
 543         .data = &(struct clk_regmap_gate_data){
 544                 .offset = HHI_MPLL_CNTL9,
 545                 .bit_idx = 14,
 546         },
 547         .hw.init = &(struct clk_init_data){
 548                 .name = "mpll2",
 549                 .ops = &clk_regmap_gate_ops,
 550                 .parent_hws = (const struct clk_hw *[]) {
 551                         &meson8b_mpll2_div.hw
 552                 },
 553                 .num_parents = 1,
 554                 .flags = CLK_SET_RATE_PARENT,
 555         },
 556 };
 557
 558 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 559 static struct clk_regmap meson8b_mpeg_clk_sel = {
 560         .data = &(struct clk_regmap_mux_data){
 561                 .offset = HHI_MPEG_CLK_CNTL,
 562                 .mask = 0x7,
 563                 .shift = 12,
 564                 .table = mux_table_clk81,
 565         },
 566         .hw.init = &(struct clk_init_data){
 567                 .name = "mpeg_clk_sel",
 568                 .ops = &clk_regmap_mux_ro_ops,
 569                 /*
 570                  * FIXME bits 14:12 selects from 8 possible parents:
 571                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 572                  * fclk_div4, fclk_div3, fclk_div5
 573                  */
 574                 .parent_hws = (const struct clk_hw *[]) {
 575                         &meson8b_fclk_div3.hw,
 576                         &meson8b_fclk_div4.hw,
 577                         &meson8b_fclk_div5.hw,
 578                 },
 579                 .num_parents = 3,
 580         },
 581 };
 582
 583 static struct clk_regmap meson8b_mpeg_clk_div = {
 584         .data = &(struct clk_regmap_div_data){
 585                 .offset = HHI_MPEG_CLK_CNTL,
 586                 .shift = 0,
 587                 .width = 7,
 588         },
 589         .hw.init = &(struct clk_init_data){
 590                 .name = "mpeg_clk_div",
 591                 .ops = &clk_regmap_divider_ro_ops,
 592                 .parent_hws = (const struct clk_hw *[]) {
 593                         &meson8b_mpeg_clk_sel.hw
 594                 },
 595                 .num_parents = 1,
 596         },
 597 };
 598
 599 static struct clk_regmap meson8b_clk81 = {
 600         .data = &(struct clk_regmap_gate_data){
 601                 .offset = HHI_MPEG_CLK_CNTL,
 602                 .bit_idx = 7,
 603         },
 604         .hw.init = &(struct clk_init_data){
 605                 .name = "clk81",
 606                 .ops = &clk_regmap_gate_ops,
 607                 .parent_hws = (const struct clk_hw *[]) {
 608                         &meson8b_mpeg_clk_div.hw
 609                 },
 610                 .num_parents = 1,
 611                 .flags = CLK_IS_CRITICAL,
 612         },
 613 };
 614
 615 static struct clk_regmap meson8b_cpu_in_sel = {
 616         .data = &(struct clk_regmap_mux_data){
 617                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 618                 .mask = 0x1,
 619                 .shift = 0,
 620         },
 621         .hw.init = &(struct clk_init_data){
 622                 .name = "cpu_in_sel",
 623                 .ops = &clk_regmap_mux_ops,
 624                 .parent_data = (const struct clk_parent_data[]) {
 625                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 626                         { .hw = &meson8b_sys_pll.hw, },
 627                 },
 628                 .num_parents = 2,
 629                 .flags = (CLK_SET_RATE_PARENT |
 630                           CLK_SET_RATE_NO_REPARENT),
 631         },
 632 };
 633
 634 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
 635         .mult = 1,
 636         .div = 2,
 637         .hw.init = &(struct clk_init_data){
 638                 .name = "cpu_in_div2",
 639                 .ops = &clk_fixed_factor_ops,
 640                 .parent_hws = (const struct clk_hw *[]) {
 641                         &meson8b_cpu_in_sel.hw
 642                 },
 643                 .num_parents = 1,
 644                 .flags = CLK_SET_RATE_PARENT,
 645         },
 646 };
 647
 648 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
 649         .mult = 1,
 650         .div = 3,
 651         .hw.init = &(struct clk_init_data){
 652                 .name = "cpu_in_div3",
 653                 .ops = &clk_fixed_factor_ops,
 654                 .parent_hws = (const struct clk_hw *[]) {
 655                         &meson8b_cpu_in_sel.hw
 656                 },
 657                 .num_parents = 1,
 658                 .flags = CLK_SET_RATE_PARENT,
 659         },
 660 };
 661
 662 static const struct clk_div_table cpu_scale_table[] = {
 663         { .val = 1, .div = 4 },
 664         { .val = 2, .div = 6 },
 665         { .val = 3, .div = 8 },
 666         { .val = 4, .div = 10 },
 667         { .val = 5, .div = 12 },
 668         { .val = 6, .div = 14 },
 669         { .val = 7, .div = 16 },
 670         { .val = 8, .div = 18 },
 671         { /* sentinel */ },
 672 };
 673
 674 static struct clk_regmap meson8b_cpu_scale_div = {
 675         .data = &(struct clk_regmap_div_data){
 676                 .offset =  HHI_SYS_CPU_CLK_CNTL1,
 677                 .shift = 20,
 678                 .width = 10,
 679                 .table = cpu_scale_table,
 680                 .flags = CLK_DIVIDER_ALLOW_ZERO,
 681         },
 682         .hw.init = &(struct clk_init_data){
 683                 .name = "cpu_scale_div",
 684                 .ops = &clk_regmap_divider_ops,
 685                 .parent_hws = (const struct clk_hw *[]) {
 686                         &meson8b_cpu_in_sel.hw
 687                 },
 688                 .num_parents = 1,
 689                 .flags = CLK_SET_RATE_PARENT,
 690         },
 691 };
 692
 693 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
 694 static struct clk_regmap meson8b_cpu_scale_out_sel = {
 695         .data = &(struct clk_regmap_mux_data){
 696                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 697                 .mask = 0x3,
 698                 .shift = 2,
 699                 .table = mux_table_cpu_scale_out_sel,
 700         },
 701         .hw.init = &(struct clk_init_data){
 702                 .name = "cpu_scale_out_sel",
 703                 .ops = &clk_regmap_mux_ops,
 704                 /*
 705                  * NOTE: We are skipping the parent with value 0x2 (which is
 706                  * meson8b_cpu_in_div3) because it results in a duty cycle of
 707                  * 33% which makes the system unstable and can result in a
 708                  * lockup of the whole system.
 709                  */
 710                 .parent_hws = (const struct clk_hw *[]) {
 711                         &meson8b_cpu_in_sel.hw,
 712                         &meson8b_cpu_in_div2.hw,
 713                         &meson8b_cpu_scale_div.hw,
 714                 },
 715                 .num_parents = 3,
 716                 .flags = CLK_SET_RATE_PARENT,
 717         },
 718 };
 719
 720 static struct clk_regmap meson8b_cpu_clk = {
 721         .data = &(struct clk_regmap_mux_data){
 722                 .offset = HHI_SYS_CPU_CLK_CNTL0,
 723                 .mask = 0x1,
 724                 .shift = 7,
 725         },
 726         .hw.init = &(struct clk_init_data){
 727                 .name = "cpu_clk",
 728                 .ops = &clk_regmap_mux_ops,
 729                 .parent_data = (const struct clk_parent_data[]) {
 730                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 731                         { .hw = &meson8b_cpu_scale_out_sel.hw, },
 732                 },
 733                 .num_parents = 2,
 734                 .flags = (CLK_SET_RATE_PARENT |
 735                           CLK_SET_RATE_NO_REPARENT |
 736                           CLK_IS_CRITICAL),
 737         },
 738 };
 739
 740 static struct clk_regmap meson8b_nand_clk_sel = {
 741         .data = &(struct clk_regmap_mux_data){
 742                 .offset = HHI_NAND_CLK_CNTL,
 743                 .mask = 0x7,
 744                 .shift = 9,
 745                 .flags = CLK_MUX_ROUND_CLOSEST,
 746         },
 747         .hw.init = &(struct clk_init_data){
 748                 .name = "nand_clk_sel",
 749                 .ops = &clk_regmap_mux_ops,
 750                 /* FIXME all other parents are unknown: */
 751                 .parent_data = (const struct clk_parent_data[]) {
 752                         { .hw = &meson8b_fclk_div4.hw, },
 753                         { .hw = &meson8b_fclk_div3.hw, },
 754                         { .hw = &meson8b_fclk_div5.hw, },
 755                         { .hw = &meson8b_fclk_div7.hw, },
 756                         { .fw_name = "xtal", .name = "xtal", .index = -1, },
 757                 },
 758                 .num_parents = 5,
 759                 .flags = CLK_SET_RATE_PARENT,
 760         },
 761 };
 762
 763 static struct clk_regmap meson8b_nand_clk_div = {
 764         .data = &(struct clk_regmap_div_data){
 765                 .offset =  HHI_NAND_CLK_CNTL,
 766                 .shift = 0,
 767                 .width = 7,
 768                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
 769         },
 770         .hw.init = &(struct clk_init_data){
 771                 .name = "nand_clk_div",
 772                 .ops = &clk_regmap_divider_ops,
 773                 .parent_hws = (const struct clk_hw *[]) {
 774                         &meson8b_nand_clk_sel.hw
 775                 },
 776                 .num_parents = 1,
 777                 .flags = CLK_SET_RATE_PARENT,
 778         },
 779 };
 780
 781 static struct clk_regmap meson8b_nand_clk_gate = {
 782         .data = &(struct clk_regmap_gate_data){
 783                 .offset = HHI_NAND_CLK_CNTL,
 784                 .bit_idx = 8,
 785         },
 786         .hw.init = &(struct clk_init_data){
 787                 .name = "nand_clk_gate",
 788                 .ops = &clk_regmap_gate_ops,
 789                 .parent_hws = (const struct clk_hw *[]) {
 790                         &meson8b_nand_clk_div.hw
 791                 },
 792                 .num_parents = 1,
 793                 .flags = CLK_SET_RATE_PARENT,
 794         },
 795 };
 796
 797 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
 798         .mult = 1,
 799         .div = 2,
 800         .hw.init = &(struct clk_init_data){
 801                 .name = "cpu_clk_div2",
 802                 .ops = &clk_fixed_factor_ops,
 803                 .parent_hws = (const struct clk_hw *[]) {
 804                         &meson8b_cpu_clk.hw
 805                 },
 806                 .num_parents = 1,
 807         },
 808 };
 809
 810 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
 811         .mult = 1,
 812         .div = 3,
 813         .hw.init = &(struct clk_init_data){
 814                 .name = "cpu_clk_div3",
 815                 .ops = &clk_fixed_factor_ops,
 816                 .parent_hws = (const struct clk_hw *[]) {
 817                         &meson8b_cpu_clk.hw
 818                 },
 819                 .num_parents = 1,
 820         },
 821 };
 822
 823 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
 824         .mult = 1,
 825         .div = 4,
 826         .hw.init = &(struct clk_init_data){
 827                 .name = "cpu_clk_div4",
 828                 .ops = &clk_fixed_factor_ops,
 829                 .parent_hws = (const struct clk_hw *[]) {
 830                         &meson8b_cpu_clk.hw
 831                 },
 832                 .num_parents = 1,
 833         },
 834 };
 835
 836 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
 837         .mult = 1,
 838         .div = 5,
 839         .hw.init = &(struct clk_init_data){
 840                 .name = "cpu_clk_div5",
 841                 .ops = &clk_fixed_factor_ops,
 842                 .parent_hws = (const struct clk_hw *[]) {
 843                         &meson8b_cpu_clk.hw
 844                 },
 845                 .num_parents = 1,
 846         },
 847 };
 848
 849 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
 850         .mult = 1,
 851         .div = 6,
 852         .hw.init = &(struct clk_init_data){
 853                 .name = "cpu_clk_div6",
 854                 .ops = &clk_fixed_factor_ops,
 855                 .parent_hws = (const struct clk_hw *[]) {
 856                         &meson8b_cpu_clk.hw
 857                 },
 858                 .num_parents = 1,
 859         },
 860 };
 861
 862 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
 863         .mult = 1,
 864         .div = 7,
 865         .hw.init = &(struct clk_init_data){
 866                 .name = "cpu_clk_div7",
 867                 .ops = &clk_fixed_factor_ops,
 868                 .parent_hws = (const struct clk_hw *[]) {
 869                         &meson8b_cpu_clk.hw
 870                 },
 871                 .num_parents = 1,
 872         },
 873 };
 874
 875 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
 876         .mult = 1,
 877         .div = 8,
 878         .hw.init = &(struct clk_init_data){
 879                 .name = "cpu_clk_div8",
 880                 .ops = &clk_fixed_factor_ops,
 881                 .parent_hws = (const struct clk_hw *[]) {
 882                         &meson8b_cpu_clk.hw
 883                 },
 884                 .num_parents = 1,
 885         },
 886 };
 887
 888 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
 889 static struct clk_regmap meson8b_apb_clk_sel = {
 890         .data = &(struct clk_regmap_mux_data){
 891                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 892                 .mask = 0x7,
 893                 .shift = 3,
 894                 .table = mux_table_apb,
 895         },
 896         .hw.init = &(struct clk_init_data){
 897                 .name = "apb_clk_sel",
 898                 .ops = &clk_regmap_mux_ops,
 899                 .parent_hws = (const struct clk_hw *[]) {
 900                         &meson8b_cpu_clk_div2.hw,
 901                         &meson8b_cpu_clk_div3.hw,
 902                         &meson8b_cpu_clk_div4.hw,
 903                         &meson8b_cpu_clk_div5.hw,
 904                         &meson8b_cpu_clk_div6.hw,
 905                         &meson8b_cpu_clk_div7.hw,
 906                         &meson8b_cpu_clk_div8.hw,
 907                 },
 908                 .num_parents = 7,
 909         },
 910 };
 911
 912 static struct clk_regmap meson8b_apb_clk_gate = {
 913         .data = &(struct clk_regmap_gate_data){
 914                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 915                 .bit_idx = 16,
 916                 .flags = CLK_GATE_SET_TO_DISABLE,
 917         },
 918         .hw.init = &(struct clk_init_data){
 919                 .name = "apb_clk_dis",
 920                 .ops = &clk_regmap_gate_ro_ops,
 921                 .parent_hws = (const struct clk_hw *[]) {
 922                         &meson8b_apb_clk_sel.hw
 923                 },
 924                 .num_parents = 1,
 925                 .flags = CLK_SET_RATE_PARENT,
 926         },
 927 };
 928
 929 static struct clk_regmap meson8b_periph_clk_sel = {
 930         .data = &(struct clk_regmap_mux_data){
 931                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 932                 .mask = 0x7,
 933                 .shift = 6,
 934         },
 935         .hw.init = &(struct clk_init_data){
 936                 .name = "periph_clk_sel",
 937                 .ops = &clk_regmap_mux_ops,
 938                 .parent_hws = (const struct clk_hw *[]) {
 939                         &meson8b_cpu_clk_div2.hw,
 940                         &meson8b_cpu_clk_div3.hw,
 941                         &meson8b_cpu_clk_div4.hw,
 942                         &meson8b_cpu_clk_div5.hw,
 943                         &meson8b_cpu_clk_div6.hw,
 944                         &meson8b_cpu_clk_div7.hw,
 945                         &meson8b_cpu_clk_div8.hw,
 946                 },
 947                 .num_parents = 7,
 948         },
 949 };
 950
 951 static struct clk_regmap meson8b_periph_clk_gate = {
 952         .data = &(struct clk_regmap_gate_data){
 953                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 954                 .bit_idx = 17,
 955                 .flags = CLK_GATE_SET_TO_DISABLE,
 956         },
 957         .hw.init = &(struct clk_init_data){
 958                 .name = "periph_clk_dis",
 959                 .ops = &clk_regmap_gate_ro_ops,
 960                 .parent_hws = (const struct clk_hw *[]) {
 961                         &meson8b_periph_clk_sel.hw
 962                 },
 963                 .num_parents = 1,
 964                 .flags = CLK_SET_RATE_PARENT,
 965         },
 966 };
 967
 968 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
 969 static struct clk_regmap meson8b_axi_clk_sel = {
 970         .data = &(struct clk_regmap_mux_data){
 971                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 972                 .mask = 0x7,
 973                 .shift = 9,
 974                 .table = mux_table_axi,
 975         },
 976         .hw.init = &(struct clk_init_data){
 977                 .name = "axi_clk_sel",
 978                 .ops = &clk_regmap_mux_ops,
 979                 .parent_hws = (const struct clk_hw *[]) {
 980                         &meson8b_cpu_clk_div2.hw,
 981                         &meson8b_cpu_clk_div3.hw,
 982                         &meson8b_cpu_clk_div4.hw,
 983                         &meson8b_cpu_clk_div5.hw,
 984                         &meson8b_cpu_clk_div6.hw,
 985                         &meson8b_cpu_clk_div7.hw,
 986                         &meson8b_cpu_clk_div8.hw,
 987                 },
 988                 .num_parents = 7,
 989         },
 990 };
 991
 992 static struct clk_regmap meson8b_axi_clk_gate = {
 993         .data = &(struct clk_regmap_gate_data){
 994                 .offset = HHI_SYS_CPU_CLK_CNTL1,
 995                 .bit_idx = 18,
 996                 .flags = CLK_GATE_SET_TO_DISABLE,
 997         },
 998         .hw.init = &(struct clk_init_data){
 999                 .name = "axi_clk_dis",
1000                 .ops = &clk_regmap_gate_ro_ops,
1001                 .parent_hws = (const struct clk_hw *[]) {
1002                         &meson8b_axi_clk_sel.hw
1003                 },
1004                 .num_parents = 1,
1005                 .flags = CLK_SET_RATE_PARENT,
1006         },
1007 };
1008
1009 static struct clk_regmap meson8b_l2_dram_clk_sel = {
1010         .data = &(struct clk_regmap_mux_data){
1011                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1012                 .mask = 0x7,
1013                 .shift = 12,
1014         },
1015         .hw.init = &(struct clk_init_data){
1016                 .name = "l2_dram_clk_sel",
1017                 .ops = &clk_regmap_mux_ops,
1018                 .parent_hws = (const struct clk_hw *[]) {
1019                         &meson8b_cpu_clk_div2.hw,
1020                         &meson8b_cpu_clk_div3.hw,
1021                         &meson8b_cpu_clk_div4.hw,
1022                         &meson8b_cpu_clk_div5.hw,
1023                         &meson8b_cpu_clk_div6.hw,
1024                         &meson8b_cpu_clk_div7.hw,
1025                         &meson8b_cpu_clk_div8.hw,
1026                 },
1027                 .num_parents = 7,
1028         },
1029 };
1030
1031 static struct clk_regmap meson8b_l2_dram_clk_gate = {
1032         .data = &(struct clk_regmap_gate_data){
1033                 .offset = HHI_SYS_CPU_CLK_CNTL1,
1034                 .bit_idx = 19,
1035                 .flags = CLK_GATE_SET_TO_DISABLE,
1036         },
1037         .hw.init = &(struct clk_init_data){
1038                 .name = "l2_dram_clk_dis",
1039                 .ops = &clk_regmap_gate_ro_ops,
1040                 .parent_hws = (const struct clk_hw *[]) {
1041                         &meson8b_l2_dram_clk_sel.hw
1042                 },
1043                 .num_parents = 1,
1044                 .flags = CLK_SET_RATE_PARENT,
1045         },
1046 };
1047
1048 static struct clk_regmap meson8b_vid_pll_in_sel = {
1049         .data = &(struct clk_regmap_mux_data){
1050                 .offset = HHI_VID_DIVIDER_CNTL,
1051                 .mask = 0x1,
1052                 .shift = 15,
1053         },
1054         .hw.init = &(struct clk_init_data){
1055                 .name = "vid_pll_in_sel",
1056                 .ops = &clk_regmap_mux_ro_ops,
1057                 /*
1058                  * TODO: depending on the SoC there is also a second parent:
1059                  * Meson8: unknown
1060                  * Meson8b: hdmi_pll_dco
1061                  * Meson8m2: vid2_pll
1062                  */
1063                 .parent_hws = (const struct clk_hw *[]) {
1064                         &meson8b_hdmi_pll_lvds_out.hw
1065                 },
1066                 .num_parents = 1,
1067                 .flags = CLK_SET_RATE_PARENT,
1068         },
1069 };
1070
1071 static struct clk_regmap meson8b_vid_pll_in_en = {
1072         .data = &(struct clk_regmap_gate_data){
1073                 .offset = HHI_VID_DIVIDER_CNTL,
1074                 .bit_idx = 16,
1075         },
1076         .hw.init = &(struct clk_init_data){
1077                 .name = "vid_pll_in_en",
1078                 .ops = &clk_regmap_gate_ro_ops,
1079                 .parent_hws = (const struct clk_hw *[]) {
1080                         &meson8b_vid_pll_in_sel.hw
1081                 },
1082                 .num_parents = 1,
1083                 .flags = CLK_SET_RATE_PARENT,
1084         },
1085 };
1086
1087 static struct clk_regmap meson8b_vid_pll_pre_div = {
1088         .data = &(struct clk_regmap_div_data){
1089                 .offset =  HHI_VID_DIVIDER_CNTL,
1090                 .shift = 4,
1091                 .width = 3,
1092         },
1093         .hw.init = &(struct clk_init_data){
1094                 .name = "vid_pll_pre_div",
1095                 .ops = &clk_regmap_divider_ro_ops,
1096                 .parent_hws = (const struct clk_hw *[]) {
1097                         &meson8b_vid_pll_in_en.hw
1098                 },
1099                 .num_parents = 1,
1100                 .flags = CLK_SET_RATE_PARENT,
1101         },
1102 };
1103
1104 static struct clk_regmap meson8b_vid_pll_post_div = {
1105         .data = &(struct clk_regmap_div_data){
1106                 .offset =  HHI_VID_DIVIDER_CNTL,
1107                 .shift = 12,
1108                 .width = 3,
1109         },
1110         .hw.init = &(struct clk_init_data){
1111                 .name = "vid_pll_post_div",
1112                 .ops = &clk_regmap_divider_ro_ops,
1113                 .parent_hws = (const struct clk_hw *[]) {
1114                         &meson8b_vid_pll_pre_div.hw
1115                 },
1116                 .num_parents = 1,
1117                 .flags = CLK_SET_RATE_PARENT,
1118         },
1119 };
1120
1121 static struct clk_regmap meson8b_vid_pll = {
1122         .data = &(struct clk_regmap_mux_data){
1123                 .offset = HHI_VID_DIVIDER_CNTL,
1124                 .mask = 0x3,
1125                 .shift = 8,
1126         },
1127         .hw.init = &(struct clk_init_data){
1128                 .name = "vid_pll",
1129                 .ops = &clk_regmap_mux_ro_ops,
1130                 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1131                 .parent_hws = (const struct clk_hw *[]) {
1132                         &meson8b_vid_pll_pre_div.hw,
1133                         &meson8b_vid_pll_post_div.hw,
1134                 },
1135                 .num_parents = 2,
1136                 .flags = CLK_SET_RATE_PARENT,
1137         },
1138 };
1139
1140 static struct clk_regmap meson8b_vid_pll_final_div = {
1141         .data = &(struct clk_regmap_div_data){
1142                 .offset =  HHI_VID_CLK_DIV,
1143                 .shift = 0,
1144                 .width = 8,
1145         },
1146         .hw.init = &(struct clk_init_data){
1147                 .name = "vid_pll_final_div",
1148                 .ops = &clk_regmap_divider_ro_ops,
1149                 .parent_hws = (const struct clk_hw *[]) {
1150                         &meson8b_vid_pll.hw
1151                 },
1152                 .num_parents = 1,
1153                 .flags = CLK_SET_RATE_PARENT,
1154         },
1155 };
1156
1157 static const struct clk_hw *meson8b_vclk_mux_parent_hws[] = {
1158         &meson8b_vid_pll_final_div.hw,
1159         &meson8b_fclk_div4.hw,
1160         &meson8b_fclk_div3.hw,
1161         &meson8b_fclk_div5.hw,
1162         &meson8b_vid_pll_final_div.hw,
1163         &meson8b_fclk_div7.hw,
1164         &meson8b_mpll1.hw,
1165 };
1166
1167 static struct clk_regmap meson8b_vclk_in_sel = {
1168         .data = &(struct clk_regmap_mux_data){
1169                 .offset = HHI_VID_CLK_CNTL,
1170                 .mask = 0x7,
1171                 .shift = 16,
1172         },
1173         .hw.init = &(struct clk_init_data){
1174                 .name = "vclk_in_sel",
1175                 .ops = &clk_regmap_mux_ro_ops,
1176                 .parent_hws = meson8b_vclk_mux_parent_hws,
1177                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1178                 .flags = CLK_SET_RATE_PARENT,
1179         },
1180 };
1181
1182 static struct clk_regmap meson8b_vclk_in_en = {
1183         .data = &(struct clk_regmap_gate_data){
1184                 .offset = HHI_VID_CLK_DIV,
1185                 .bit_idx = 16,
1186         },
1187         .hw.init = &(struct clk_init_data){
1188                 .name = "vclk_in_en",
1189                 .ops = &clk_regmap_gate_ro_ops,
1190                 .parent_hws = (const struct clk_hw *[]) {
1191                         &meson8b_vclk_in_sel.hw
1192                 },
1193                 .num_parents = 1,
1194                 .flags = CLK_SET_RATE_PARENT,
1195         },
1196 };
1197
1198 static struct clk_regmap meson8b_vclk_en = {
1199         .data = &(struct clk_regmap_gate_data){
1200                 .offset = HHI_VID_CLK_CNTL,
1201                 .bit_idx = 19,
1202         },
1203         .hw.init = &(struct clk_init_data){
1204                 .name = "vclk_en",
1205                 .ops = &clk_regmap_gate_ro_ops,
1206                 .parent_hws = (const struct clk_hw *[]) {
1207                         &meson8b_vclk_in_en.hw
1208                 },
1209                 .num_parents = 1,
1210                 .flags = CLK_SET_RATE_PARENT,
1211         },
1212 };
1213
1214 static struct clk_regmap meson8b_vclk_div1_gate = {
1215         .data = &(struct clk_regmap_gate_data){
1216                 .offset = HHI_VID_CLK_CNTL,
1217                 .bit_idx = 0,
1218         },
1219         .hw.init = &(struct clk_init_data){
1220                 .name = "vclk_div1_en",
1221                 .ops = &clk_regmap_gate_ro_ops,
1222                 .parent_hws = (const struct clk_hw *[]) {
1223                         &meson8b_vclk_en.hw
1224                 },
1225                 .num_parents = 1,
1226                 .flags = CLK_SET_RATE_PARENT,
1227         },
1228 };
1229
1230 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1231         .mult = 1,
1232         .div = 2,
1233         .hw.init = &(struct clk_init_data){
1234                 .name = "vclk_div2",
1235                 .ops = &clk_fixed_factor_ops,
1236                 .parent_hws = (const struct clk_hw *[]) {
1237                         &meson8b_vclk_en.hw
1238                 },
1239                 .num_parents = 1,
1240                 .flags = CLK_SET_RATE_PARENT,
1241         }
1242 };
1243
1244 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1245         .data = &(struct clk_regmap_gate_data){
1246                 .offset = HHI_VID_CLK_CNTL,
1247                 .bit_idx = 1,
1248         },
1249         .hw.init = &(struct clk_init_data){
1250                 .name = "vclk_div2_en",
1251                 .ops = &clk_regmap_gate_ro_ops,
1252                 .parent_hws = (const struct clk_hw *[]) {
1253                         &meson8b_vclk_div2_div.hw
1254                 },
1255                 .num_parents = 1,
1256                 .flags = CLK_SET_RATE_PARENT,
1257         },
1258 };
1259
1260 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1261         .mult = 1,
1262         .div = 4,
1263         .hw.init = &(struct clk_init_data){
1264                 .name = "vclk_div4",
1265                 .ops = &clk_fixed_factor_ops,
1266                 .parent_hws = (const struct clk_hw *[]) {
1267                         &meson8b_vclk_en.hw
1268                 },
1269                 .num_parents = 1,
1270                 .flags = CLK_SET_RATE_PARENT,
1271         }
1272 };
1273
1274 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1275         .data = &(struct clk_regmap_gate_data){
1276                 .offset = HHI_VID_CLK_CNTL,
1277                 .bit_idx = 2,
1278         },
1279         .hw.init = &(struct clk_init_data){
1280                 .name = "vclk_div4_en",
1281                 .ops = &clk_regmap_gate_ro_ops,
1282                 .parent_hws = (const struct clk_hw *[]) {
1283                         &meson8b_vclk_div4_div.hw
1284                 },
1285                 .num_parents = 1,
1286                 .flags = CLK_SET_RATE_PARENT,
1287         },
1288 };
1289
1290 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1291         .mult = 1,
1292         .div = 6,
1293         .hw.init = &(struct clk_init_data){
1294                 .name = "vclk_div6",
1295                 .ops = &clk_fixed_factor_ops,
1296                 .parent_hws = (const struct clk_hw *[]) {
1297                         &meson8b_vclk_en.hw
1298                 },
1299                 .num_parents = 1,
1300                 .flags = CLK_SET_RATE_PARENT,
1301         }
1302 };
1303
1304 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1305         .data = &(struct clk_regmap_gate_data){
1306                 .offset = HHI_VID_CLK_CNTL,
1307                 .bit_idx = 3,
1308         },
1309         .hw.init = &(struct clk_init_data){
1310                 .name = "vclk_div6_en",
1311                 .ops = &clk_regmap_gate_ro_ops,
1312                 .parent_hws = (const struct clk_hw *[]) {
1313                         &meson8b_vclk_div6_div.hw
1314                 },
1315                 .num_parents = 1,
1316                 .flags = CLK_SET_RATE_PARENT,
1317         },
1318 };
1319
1320 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1321         .mult = 1,
1322         .div = 12,
1323         .hw.init = &(struct clk_init_data){
1324                 .name = "vclk_div12",
1325                 .ops = &clk_fixed_factor_ops,
1326                 .parent_hws = (const struct clk_hw *[]) {
1327                         &meson8b_vclk_en.hw
1328                 },
1329                 .num_parents = 1,
1330                 .flags = CLK_SET_RATE_PARENT,
1331         }
1332 };
1333
1334 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1335         .data = &(struct clk_regmap_gate_data){
1336                 .offset = HHI_VID_CLK_CNTL,
1337                 .bit_idx = 4,
1338         },
1339         .hw.init = &(struct clk_init_data){
1340                 .name = "vclk_div12_en",
1341                 .ops = &clk_regmap_gate_ro_ops,
1342                 .parent_hws = (const struct clk_hw *[]) {
1343                         &meson8b_vclk_div12_div.hw
1344                 },
1345                 .num_parents = 1,
1346                 .flags = CLK_SET_RATE_PARENT,
1347         },
1348 };
1349
1350 static struct clk_regmap meson8b_vclk2_in_sel = {
1351         .data = &(struct clk_regmap_mux_data){
1352                 .offset = HHI_VIID_CLK_CNTL,
1353                 .mask = 0x7,
1354                 .shift = 16,
1355         },
1356         .hw.init = &(struct clk_init_data){
1357                 .name = "vclk2_in_sel",
1358                 .ops = &clk_regmap_mux_ro_ops,
1359                 .parent_hws = meson8b_vclk_mux_parent_hws,
1360                 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parent_hws),
1361                 .flags = CLK_SET_RATE_PARENT,
1362         },
1363 };
1364
1365 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1366         .data = &(struct clk_regmap_gate_data){
1367                 .offset = HHI_VIID_CLK_DIV,
1368                 .bit_idx = 16,
1369         },
1370         .hw.init = &(struct clk_init_data){
1371                 .name = "vclk2_in_en",
1372                 .ops = &clk_regmap_gate_ro_ops,
1373                 .parent_hws = (const struct clk_hw *[]) {
1374                         &meson8b_vclk2_in_sel.hw
1375                 },
1376                 .num_parents = 1,
1377                 .flags = CLK_SET_RATE_PARENT,
1378         },
1379 };
1380
1381 static struct clk_regmap meson8b_vclk2_clk_en = {
1382         .data = &(struct clk_regmap_gate_data){
1383                 .offset = HHI_VIID_CLK_DIV,
1384                 .bit_idx = 19,
1385         },
1386         .hw.init = &(struct clk_init_data){
1387                 .name = "vclk2_en",
1388                 .ops = &clk_regmap_gate_ro_ops,
1389                 .parent_hws = (const struct clk_hw *[]) {
1390                         &meson8b_vclk2_clk_in_en.hw
1391                 },
1392                 .num_parents = 1,
1393                 .flags = CLK_SET_RATE_PARENT,
1394         },
1395 };
1396
1397 static struct clk_regmap meson8b_vclk2_div1_gate = {
1398         .data = &(struct clk_regmap_gate_data){
1399                 .offset = HHI_VIID_CLK_DIV,
1400                 .bit_idx = 0,
1401         },
1402         .hw.init = &(struct clk_init_data){
1403                 .name = "vclk2_div1_en",
1404                 .ops = &clk_regmap_gate_ro_ops,
1405                 .parent_hws = (const struct clk_hw *[]) {
1406                         &meson8b_vclk2_clk_en.hw
1407                 },
1408                 .num_parents = 1,
1409                 .flags = CLK_SET_RATE_PARENT,
1410         },
1411 };
1412
1413 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1414         .mult = 1,
1415         .div = 2,
1416         .hw.init = &(struct clk_init_data){
1417                 .name = "vclk2_div2",
1418                 .ops = &clk_fixed_factor_ops,
1419                 .parent_hws = (const struct clk_hw *[]) {
1420                         &meson8b_vclk2_clk_en.hw
1421                 },
1422                 .num_parents = 1,
1423                 .flags = CLK_SET_RATE_PARENT,
1424         }
1425 };
1426
1427 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1428         .data = &(struct clk_regmap_gate_data){
1429                 .offset = HHI_VIID_CLK_DIV,
1430                 .bit_idx = 1,
1431         },
1432         .hw.init = &(struct clk_init_data){
1433                 .name = "vclk2_div2_en",
1434                 .ops = &clk_regmap_gate_ro_ops,
1435                 .parent_hws = (const struct clk_hw *[]) {
1436                         &meson8b_vclk2_div2_div.hw
1437                 },
1438                 .num_parents = 1,
1439                 .flags = CLK_SET_RATE_PARENT,
1440         },
1441 };
1442
1443 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1444         .mult = 1,
1445         .div = 4,
1446         .hw.init = &(struct clk_init_data){
1447                 .name = "vclk2_div4",
1448                 .ops = &clk_fixed_factor_ops,
1449                 .parent_hws = (const struct clk_hw *[]) {
1450                         &meson8b_vclk2_clk_en.hw
1451                 },
1452                 .num_parents = 1,
1453                 .flags = CLK_SET_RATE_PARENT,
1454         }
1455 };
1456
1457 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1458         .data = &(struct clk_regmap_gate_data){
1459                 .offset = HHI_VIID_CLK_DIV,
1460                 .bit_idx = 2,
1461         },
1462         .hw.init = &(struct clk_init_data){
1463                 .name = "vclk2_div4_en",
1464                 .ops = &clk_regmap_gate_ro_ops,
1465                 .parent_hws = (const struct clk_hw *[]) {
1466                         &meson8b_vclk2_div4_div.hw
1467                 },
1468                 .num_parents = 1,
1469                 .flags = CLK_SET_RATE_PARENT,
1470         },
1471 };
1472
1473 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1474         .mult = 1,
1475         .div = 6,
1476         .hw.init = &(struct clk_init_data){
1477                 .name = "vclk2_div6",
1478                 .ops = &clk_fixed_factor_ops,
1479                 .parent_hws = (const struct clk_hw *[]) {
1480                         &meson8b_vclk2_clk_en.hw
1481                 },
1482                 .num_parents = 1,
1483                 .flags = CLK_SET_RATE_PARENT,
1484         }
1485 };
1486
1487 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1488         .data = &(struct clk_regmap_gate_data){
1489                 .offset = HHI_VIID_CLK_DIV,
1490                 .bit_idx = 3,
1491         },
1492         .hw.init = &(struct clk_init_data){
1493                 .name = "vclk2_div6_en",
1494                 .ops = &clk_regmap_gate_ro_ops,
1495                 .parent_hws = (const struct clk_hw *[]) {
1496                         &meson8b_vclk2_div6_div.hw
1497                 },
1498                 .num_parents = 1,
1499                 .flags = CLK_SET_RATE_PARENT,
1500         },
1501 };
1502
1503 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1504         .mult = 1,
1505         .div = 12,
1506         .hw.init = &(struct clk_init_data){
1507                 .name = "vclk2_div12",
1508                 .ops = &clk_fixed_factor_ops,
1509                 .parent_hws = (const struct clk_hw *[]) {
1510                         &meson8b_vclk2_clk_en.hw
1511                 },
1512                 .num_parents = 1,
1513                 .flags = CLK_SET_RATE_PARENT,
1514         }
1515 };
1516
1517 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1518         .data = &(struct clk_regmap_gate_data){
1519                 .offset = HHI_VIID_CLK_DIV,
1520                 .bit_idx = 4,
1521         },
1522         .hw.init = &(struct clk_init_data){
1523                 .name = "vclk2_div12_en",
1524                 .ops = &clk_regmap_gate_ro_ops,
1525                 .parent_hws = (const struct clk_hw *[]) {
1526                         &meson8b_vclk2_div12_div.hw
1527                 },
1528                 .num_parents = 1,
1529                 .flags = CLK_SET_RATE_PARENT,
1530         },
1531 };
1532
1533 static const struct clk_hw *meson8b_vclk_enc_mux_parent_hws[] = {
1534         &meson8b_vclk_div1_gate.hw,
1535         &meson8b_vclk_div2_div_gate.hw,
1536         &meson8b_vclk_div4_div_gate.hw,
1537         &meson8b_vclk_div6_div_gate.hw,
1538         &meson8b_vclk_div12_div_gate.hw,
1539 };
1540
1541 static struct clk_regmap meson8b_cts_enct_sel = {
1542         .data = &(struct clk_regmap_mux_data){
1543                 .offset = HHI_VID_CLK_DIV,
1544                 .mask = 0xf,
1545                 .shift = 20,
1546         },
1547         .hw.init = &(struct clk_init_data){
1548                 .name = "cts_enct_sel",
1549                 .ops = &clk_regmap_mux_ro_ops,
1550                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1551                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1552                 .flags = CLK_SET_RATE_PARENT,
1553         },
1554 };
1555
1556 static struct clk_regmap meson8b_cts_enct = {
1557         .data = &(struct clk_regmap_gate_data){
1558                 .offset = HHI_VID_CLK_CNTL2,
1559                 .bit_idx = 1,
1560         },
1561         .hw.init = &(struct clk_init_data){
1562                 .name = "cts_enct",
1563                 .ops = &clk_regmap_gate_ro_ops,
1564                 .parent_hws = (const struct clk_hw *[]) {
1565                         &meson8b_cts_enct_sel.hw
1566                 },
1567                 .num_parents = 1,
1568                 .flags = CLK_SET_RATE_PARENT,
1569         },
1570 };
1571
1572 static struct clk_regmap meson8b_cts_encp_sel = {
1573         .data = &(struct clk_regmap_mux_data){
1574                 .offset = HHI_VID_CLK_DIV,
1575                 .mask = 0xf,
1576                 .shift = 24,
1577         },
1578         .hw.init = &(struct clk_init_data){
1579                 .name = "cts_encp_sel",
1580                 .ops = &clk_regmap_mux_ro_ops,
1581                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1582                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1583                 .flags = CLK_SET_RATE_PARENT,
1584         },
1585 };
1586
1587 static struct clk_regmap meson8b_cts_encp = {
1588         .data = &(struct clk_regmap_gate_data){
1589                 .offset = HHI_VID_CLK_CNTL2,
1590                 .bit_idx = 2,
1591         },
1592         .hw.init = &(struct clk_init_data){
1593                 .name = "cts_encp",
1594                 .ops = &clk_regmap_gate_ro_ops,
1595                 .parent_hws = (const struct clk_hw *[]) {
1596                         &meson8b_cts_encp_sel.hw
1597                 },
1598                 .num_parents = 1,
1599                 .flags = CLK_SET_RATE_PARENT,
1600         },
1601 };
1602
1603 static struct clk_regmap meson8b_cts_enci_sel = {
1604         .data = &(struct clk_regmap_mux_data){
1605                 .offset = HHI_VID_CLK_DIV,
1606                 .mask = 0xf,
1607                 .shift = 28,
1608         },
1609         .hw.init = &(struct clk_init_data){
1610                 .name = "cts_enci_sel",
1611                 .ops = &clk_regmap_mux_ro_ops,
1612                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1613                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1614                 .flags = CLK_SET_RATE_PARENT,
1615         },
1616 };
1617
1618 static struct clk_regmap meson8b_cts_enci = {
1619         .data = &(struct clk_regmap_gate_data){
1620                 .offset = HHI_VID_CLK_CNTL2,
1621                 .bit_idx = 0,
1622         },
1623         .hw.init = &(struct clk_init_data){
1624                 .name = "cts_enci",
1625                 .ops = &clk_regmap_gate_ro_ops,
1626                 .parent_hws = (const struct clk_hw *[]) {
1627                         &meson8b_cts_enci_sel.hw
1628                 },
1629                 .num_parents = 1,
1630                 .flags = CLK_SET_RATE_PARENT,
1631         },
1632 };
1633
1634 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1635         .data = &(struct clk_regmap_mux_data){
1636                 .offset = HHI_HDMI_CLK_CNTL,
1637                 .mask = 0xf,
1638                 .shift = 16,
1639         },
1640         .hw.init = &(struct clk_init_data){
1641                 .name = "hdmi_tx_pixel_sel",
1642                 .ops = &clk_regmap_mux_ro_ops,
1643                 .parent_hws = meson8b_vclk_enc_mux_parent_hws,
1644                 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parent_hws),
1645                 .flags = CLK_SET_RATE_PARENT,
1646         },
1647 };
1648
1649 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1650         .data = &(struct clk_regmap_gate_data){
1651                 .offset = HHI_VID_CLK_CNTL2,
1652                 .bit_idx = 5,
1653         },
1654         .hw.init = &(struct clk_init_data){
1655                 .name = "hdmi_tx_pixel",
1656                 .ops = &clk_regmap_gate_ro_ops,
1657                 .parent_hws = (const struct clk_hw *[]) {
1658                         &meson8b_hdmi_tx_pixel_sel.hw
1659                 },
1660                 .num_parents = 1,
1661                 .flags = CLK_SET_RATE_PARENT,
1662         },
1663 };
1664
1665 static const struct clk_hw *meson8b_vclk2_enc_mux_parent_hws[] = {
1666         &meson8b_vclk2_div1_gate.hw,
1667         &meson8b_vclk2_div2_div_gate.hw,
1668         &meson8b_vclk2_div4_div_gate.hw,
1669         &meson8b_vclk2_div6_div_gate.hw,
1670         &meson8b_vclk2_div12_div_gate.hw,
1671 };
1672
1673 static struct clk_regmap meson8b_cts_encl_sel = {
1674         .data = &(struct clk_regmap_mux_data){
1675                 .offset = HHI_VIID_CLK_DIV,
1676                 .mask = 0xf,
1677                 .shift = 12,
1678         },
1679         .hw.init = &(struct clk_init_data){
1680                 .name = "cts_encl_sel",
1681                 .ops = &clk_regmap_mux_ro_ops,
1682                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1683                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1684                 .flags = CLK_SET_RATE_PARENT,
1685         },
1686 };
1687
1688 static struct clk_regmap meson8b_cts_encl = {
1689         .data = &(struct clk_regmap_gate_data){
1690                 .offset = HHI_VID_CLK_CNTL2,
1691                 .bit_idx = 3,
1692         },
1693         .hw.init = &(struct clk_init_data){
1694                 .name = "cts_encl",
1695                 .ops = &clk_regmap_gate_ro_ops,
1696                 .parent_hws = (const struct clk_hw *[]) {
1697                         &meson8b_cts_encl_sel.hw
1698                 },
1699                 .num_parents = 1,
1700                 .flags = CLK_SET_RATE_PARENT,
1701         },
1702 };
1703
1704 static struct clk_regmap meson8b_cts_vdac0_sel = {
1705         .data = &(struct clk_regmap_mux_data){
1706                 .offset = HHI_VIID_CLK_DIV,
1707                 .mask = 0xf,
1708                 .shift = 28,
1709         },
1710         .hw.init = &(struct clk_init_data){
1711                 .name = "cts_vdac0_sel",
1712                 .ops = &clk_regmap_mux_ro_ops,
1713                 .parent_hws = meson8b_vclk2_enc_mux_parent_hws,
1714                 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parent_hws),
1715                 .flags = CLK_SET_RATE_PARENT,
1716         },
1717 };
1718
1719 static struct clk_regmap meson8b_cts_vdac0 = {
1720         .data = &(struct clk_regmap_gate_data){
1721                 .offset = HHI_VID_CLK_CNTL2,
1722                 .bit_idx = 4,
1723         },
1724         .hw.init = &(struct clk_init_data){
1725                 .name = "cts_vdac0",
1726                 .ops = &clk_regmap_gate_ro_ops,
1727                 .parent_hws = (const struct clk_hw *[]) {
1728                         &meson8b_cts_vdac0_sel.hw
1729                 },
1730                 .num_parents = 1,
1731                 .flags = CLK_SET_RATE_PARENT,
1732         },
1733 };
1734
1735 static struct clk_regmap meson8b_hdmi_sys_sel = {
1736         .data = &(struct clk_regmap_mux_data){
1737                 .offset = HHI_HDMI_CLK_CNTL,
1738                 .mask = 0x3,
1739                 .shift = 9,
1740                 .flags = CLK_MUX_ROUND_CLOSEST,
1741         },
1742         .hw.init = &(struct clk_init_data){
1743                 .name = "hdmi_sys_sel",
1744                 .ops = &clk_regmap_mux_ops,
1745                 /* FIXME: all other parents are unknown */
1746                 .parent_data = &(const struct clk_parent_data) {
1747                         .fw_name = "xtal",
1748                         .name = "xtal",
1749                         .index = -1,
1750                 },
1751                 .num_parents = 1,
1752                 .flags = CLK_SET_RATE_NO_REPARENT,
1753         },
1754 };
1755
1756 static struct clk_regmap meson8b_hdmi_sys_div = {
1757         .data = &(struct clk_regmap_div_data){
1758                 .offset = HHI_HDMI_CLK_CNTL,
1759                 .shift = 0,
1760                 .width = 7,
1761         },
1762         .hw.init = &(struct clk_init_data){
1763                 .name = "hdmi_sys_div",
1764                 .ops = &clk_regmap_divider_ops,
1765                 .parent_hws = (const struct clk_hw *[]) {
1766                         &meson8b_hdmi_sys_sel.hw
1767                 },
1768                 .num_parents = 1,
1769                 .flags = CLK_SET_RATE_PARENT,
1770         },
1771 };
1772
1773 static struct clk_regmap meson8b_hdmi_sys = {
1774         .data = &(struct clk_regmap_gate_data){
1775                 .offset = HHI_HDMI_CLK_CNTL,
1776                 .bit_idx = 8,
1777         },
1778         .hw.init = &(struct clk_init_data) {
1779                 .name = "hdmi_sys",
1780                 .ops = &clk_regmap_gate_ops,
1781                 .parent_hws = (const struct clk_hw *[]) {
1782                         &meson8b_hdmi_sys_div.hw
1783                 },
1784                 .num_parents = 1,
1785                 .flags = CLK_SET_RATE_PARENT,
1786         },
1787 };
1788
1789 /*
1790  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1791  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
1792  * actually manage this glitch-free mux because it does top-to-bottom
1793  * updates the each clock tree and switches to the "inactive" one when
1794  * CLK_SET_RATE_GATE is set.
1795  * Meson8 only has mali_0 and no glitch-free mux.
1796  */
1797 static const struct clk_parent_data meson8b_mali_0_1_parent_data[] = {
1798         { .fw_name = "xtal", .name = "xtal", .index = -1, },
1799         { .hw = &meson8b_mpll2.hw, },
1800         { .hw = &meson8b_mpll1.hw, },
1801         { .hw = &meson8b_fclk_div7.hw, },
1802         { .hw = &meson8b_fclk_div4.hw, },
1803         { .hw = &meson8b_fclk_div3.hw, },
1804         { .hw = &meson8b_fclk_div5.hw, },
1805 };
1806
1807 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1808
1809 static struct clk_regmap meson8b_mali_0_sel = {
1810         .data = &(struct clk_regmap_mux_data){
1811                 .offset = HHI_MALI_CLK_CNTL,
1812                 .mask = 0x7,
1813                 .shift = 9,
1814                 .table = meson8b_mali_0_1_mux_table,
1815         },
1816         .hw.init = &(struct clk_init_data){
1817                 .name = "mali_0_sel",
1818                 .ops = &clk_regmap_mux_ops,
1819                 .parent_data = meson8b_mali_0_1_parent_data,
1820                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1821                 /*
1822                  * Don't propagate rate changes up because the only changeable
1823                  * parents are mpll1 and mpll2 but we need those for audio and
1824                  * RGMII (Ethernet). We don't want to change the audio or
1825                  * Ethernet clocks when setting the GPU frequency.
1826                  */
1827                 .flags = 0,
1828         },
1829 };
1830
1831 static struct clk_regmap meson8b_mali_0_div = {
1832         .data = &(struct clk_regmap_div_data){
1833                 .offset = HHI_MALI_CLK_CNTL,
1834                 .shift = 0,
1835                 .width = 7,
1836         },
1837         .hw.init = &(struct clk_init_data){
1838                 .name = "mali_0_div",
1839                 .ops = &clk_regmap_divider_ops,
1840                 .parent_hws = (const struct clk_hw *[]) {
1841                         &meson8b_mali_0_sel.hw
1842                 },
1843                 .num_parents = 1,
1844                 .flags = CLK_SET_RATE_PARENT,
1845         },
1846 };
1847
1848 static struct clk_regmap meson8b_mali_0 = {
1849         .data = &(struct clk_regmap_gate_data){
1850                 .offset = HHI_MALI_CLK_CNTL,
1851                 .bit_idx = 8,
1852         },
1853         .hw.init = &(struct clk_init_data){
1854                 .name = "mali_0",
1855                 .ops = &clk_regmap_gate_ops,
1856                 .parent_hws = (const struct clk_hw *[]) {
1857                         &meson8b_mali_0_div.hw
1858                 },
1859                 .num_parents = 1,
1860                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1861         },
1862 };
1863
1864 static struct clk_regmap meson8b_mali_1_sel = {
1865         .data = &(struct clk_regmap_mux_data){
1866                 .offset = HHI_MALI_CLK_CNTL,
1867                 .mask = 0x7,
1868                 .shift = 25,
1869                 .table = meson8b_mali_0_1_mux_table,
1870         },
1871         .hw.init = &(struct clk_init_data){
1872                 .name = "mali_1_sel",
1873                 .ops = &clk_regmap_mux_ops,
1874                 .parent_data = meson8b_mali_0_1_parent_data,
1875                 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_data),
1876                 /*
1877                  * Don't propagate rate changes up because the only changeable
1878                  * parents are mpll1 and mpll2 but we need those for audio and
1879                  * RGMII (Ethernet). We don't want to change the audio or
1880                  * Ethernet clocks when setting the GPU frequency.
1881                  */
1882                 .flags = 0,
1883         },
1884 };
1885
1886 static struct clk_regmap meson8b_mali_1_div = {
1887         .data = &(struct clk_regmap_div_data){
1888                 .offset = HHI_MALI_CLK_CNTL,
1889                 .shift = 16,
1890                 .width = 7,
1891         },
1892         .hw.init = &(struct clk_init_data){
1893                 .name = "mali_1_div",
1894                 .ops = &clk_regmap_divider_ops,
1895                 .parent_hws = (const struct clk_hw *[]) {
1896                         &meson8b_mali_1_sel.hw
1897                 },
1898                 .num_parents = 1,
1899                 .flags = CLK_SET_RATE_PARENT,
1900         },
1901 };
1902
1903 static struct clk_regmap meson8b_mali_1 = {
1904         .data = &(struct clk_regmap_gate_data){
1905                 .offset = HHI_MALI_CLK_CNTL,
1906                 .bit_idx = 24,
1907         },
1908         .hw.init = &(struct clk_init_data){
1909                 .name = "mali_1",
1910                 .ops = &clk_regmap_gate_ops,
1911                 .parent_hws = (const struct clk_hw *[]) {
1912                         &meson8b_mali_1_div.hw
1913                 },
1914                 .num_parents = 1,
1915                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1916         },
1917 };
1918
1919 static struct clk_regmap meson8b_mali = {
1920         .data = &(struct clk_regmap_mux_data){
1921                 .offset = HHI_MALI_CLK_CNTL,
1922                 .mask = 1,
1923                 .shift = 31,
1924         },
1925         .hw.init = &(struct clk_init_data){
1926                 .name = "mali",
1927                 .ops = &clk_regmap_mux_ops,
1928                 .parent_hws = (const struct clk_hw *[]) {
1929                         &meson8b_mali_0.hw,
1930                         &meson8b_mali_1.hw,
1931                 },
1932                 .num_parents = 2,
1933                 .flags = CLK_SET_RATE_PARENT,
1934         },
1935 };
1936
1937 static const struct reg_sequence meson8m2_gp_pll_init_regs[] = {
1938         { .reg = HHI_GP_PLL_CNTL2,      .def = 0x59c88000 },
1939         { .reg = HHI_GP_PLL_CNTL3,      .def = 0xca463823 },
1940         { .reg = HHI_GP_PLL_CNTL4,      .def = 0x0286a027 },
1941         { .reg = HHI_GP_PLL_CNTL5,      .def = 0x00003000 },
1942 };
1943
1944 static const struct pll_params_table meson8m2_gp_pll_params_table[] = {
1945         PLL_PARAMS(182, 3),
1946         { /* sentinel */ },
1947 };
1948
1949 static struct clk_regmap meson8m2_gp_pll_dco = {
1950         .data = &(struct meson_clk_pll_data){
1951                 .en = {
1952                         .reg_off = HHI_GP_PLL_CNTL,
1953                         .shift   = 30,
1954                         .width   = 1,
1955                 },
1956                 .m = {
1957                         .reg_off = HHI_GP_PLL_CNTL,
1958                         .shift   = 0,
1959                         .width   = 9,
1960                 },
1961                 .n = {
1962                         .reg_off = HHI_GP_PLL_CNTL,
1963                         .shift   = 9,
1964                         .width   = 5,
1965                 },
1966                 .l = {
1967                         .reg_off = HHI_GP_PLL_CNTL,
1968                         .shift   = 31,
1969                         .width   = 1,
1970                 },
1971                 .rst = {
1972                         .reg_off = HHI_GP_PLL_CNTL,
1973                         .shift   = 29,
1974                         .width   = 1,
1975                 },
1976                 .table = meson8m2_gp_pll_params_table,
1977                 .init_regs = meson8m2_gp_pll_init_regs,
1978                 .init_count = ARRAY_SIZE(meson8m2_gp_pll_init_regs),
1979         },
1980         .hw.init = &(struct clk_init_data){
1981                 .name = "gp_pll_dco",
1982                 .ops = &meson_clk_pll_ops,
1983                 .parent_data = &(const struct clk_parent_data) {
1984                         .fw_name = "xtal",
1985                         .name = "xtal",
1986                         .index = -1,
1987                 },
1988                 .num_parents = 1,
1989         },
1990 };
1991
1992 static struct clk_regmap meson8m2_gp_pll = {
1993         .data = &(struct clk_regmap_div_data){
1994                 .offset = HHI_GP_PLL_CNTL,
1995                 .shift = 16,
1996                 .width = 2,
1997                 .flags = CLK_DIVIDER_POWER_OF_TWO,
1998         },
1999         .hw.init = &(struct clk_init_data){
2000                 .name = "gp_pll",
2001                 .ops = &clk_regmap_divider_ops,
2002                 .parent_hws = (const struct clk_hw *[]) {
2003                         &meson8m2_gp_pll_dco.hw
2004                 },
2005                 .num_parents = 1,
2006                 .flags = CLK_SET_RATE_PARENT,
2007         },
2008 };
2009
2010 static const struct clk_hw *meson8b_vpu_0_1_parent_hws[] = {
2011         &meson8b_fclk_div4.hw,
2012         &meson8b_fclk_div3.hw,
2013         &meson8b_fclk_div5.hw,
2014         &meson8b_fclk_div7.hw,
2015 };
2016
2017 static const struct clk_hw *mmeson8m2_vpu_0_1_parent_hws[] = {
2018         &meson8b_fclk_div4.hw,
2019         &meson8b_fclk_div3.hw,
2020         &meson8b_fclk_div5.hw,
2021         &meson8m2_gp_pll.hw,
2022 };
2023
2024 static struct clk_regmap meson8b_vpu_0_sel = {
2025         .data = &(struct clk_regmap_mux_data){
2026                 .offset = HHI_VPU_CLK_CNTL,
2027                 .mask = 0x3,
2028                 .shift = 9,
2029         },
2030         .hw.init = &(struct clk_init_data){
2031                 .name = "vpu_0_sel",
2032                 .ops = &clk_regmap_mux_ops,
2033                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2034                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2035                 .flags = CLK_SET_RATE_PARENT,
2036         },
2037 };
2038
2039 static struct clk_regmap meson8m2_vpu_0_sel = {
2040         .data = &(struct clk_regmap_mux_data){
2041                 .offset = HHI_VPU_CLK_CNTL,
2042                 .mask = 0x3,
2043                 .shift = 9,
2044         },
2045         .hw.init = &(struct clk_init_data){
2046                 .name = "vpu_0_sel",
2047                 .ops = &clk_regmap_mux_ops,
2048                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2049                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2050                 .flags = CLK_SET_RATE_PARENT,
2051         },
2052 };
2053
2054 static struct clk_regmap meson8b_vpu_0_div = {
2055         .data = &(struct clk_regmap_div_data){
2056                 .offset = HHI_VPU_CLK_CNTL,
2057                 .shift = 0,
2058                 .width = 7,
2059         },
2060         .hw.init = &(struct clk_init_data){
2061                 .name = "vpu_0_div",
2062                 .ops = &clk_regmap_divider_ops,
2063                 .parent_data = &(const struct clk_parent_data) {
2064                         /*
2065                          * Note:
2066                          * meson8b and meson8m2 have different vpu_0_sels (with
2067                          * different struct clk_hw). We fallback to the global
2068                          * naming string mechanism so vpu_0_div picks up the
2069                          * appropriate one.
2070                          */
2071                         .name = "vpu_0_sel",
2072                         .index = -1,
2073                 },
2074                 .num_parents = 1,
2075                 .flags = CLK_SET_RATE_PARENT,
2076         },
2077 };
2078
2079 static struct clk_regmap meson8b_vpu_0 = {
2080         .data = &(struct clk_regmap_gate_data){
2081                 .offset = HHI_VPU_CLK_CNTL,
2082                 .bit_idx = 8,
2083         },
2084         .hw.init = &(struct clk_init_data) {
2085                 .name = "vpu_0",
2086                 .ops = &clk_regmap_gate_ops,
2087                 .parent_hws = (const struct clk_hw *[]) {
2088                         &meson8b_vpu_0_div.hw
2089                 },
2090                 .num_parents = 1,
2091                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2092         },
2093 };
2094
2095 static struct clk_regmap meson8b_vpu_1_sel = {
2096         .data = &(struct clk_regmap_mux_data){
2097                 .offset = HHI_VPU_CLK_CNTL,
2098                 .mask = 0x3,
2099                 .shift = 25,
2100         },
2101         .hw.init = &(struct clk_init_data){
2102                 .name = "vpu_1_sel",
2103                 .ops = &clk_regmap_mux_ops,
2104                 .parent_hws = meson8b_vpu_0_1_parent_hws,
2105                 .num_parents = ARRAY_SIZE(meson8b_vpu_0_1_parent_hws),
2106                 .flags = CLK_SET_RATE_PARENT,
2107         },
2108 };
2109
2110 static struct clk_regmap meson8m2_vpu_1_sel = {
2111         .data = &(struct clk_regmap_mux_data){
2112                 .offset = HHI_VPU_CLK_CNTL,
2113                 .mask = 0x3,
2114                 .shift = 25,
2115         },
2116         .hw.init = &(struct clk_init_data){
2117                 .name = "vpu_1_sel",
2118                 .ops = &clk_regmap_mux_ops,
2119                 .parent_hws = mmeson8m2_vpu_0_1_parent_hws,
2120                 .num_parents = ARRAY_SIZE(mmeson8m2_vpu_0_1_parent_hws),
2121                 .flags = CLK_SET_RATE_PARENT,
2122         },
2123 };
2124
2125 static struct clk_regmap meson8b_vpu_1_div = {
2126         .data = &(struct clk_regmap_div_data){
2127                 .offset = HHI_VPU_CLK_CNTL,
2128                 .shift = 16,
2129                 .width = 7,
2130         },
2131         .hw.init = &(struct clk_init_data){
2132                 .name = "vpu_1_div",
2133                 .ops = &clk_regmap_divider_ops,
2134                 .parent_data = &(const struct clk_parent_data) {
2135                         /*
2136                          * Note:
2137                          * meson8b and meson8m2 have different vpu_1_sels (with
2138                          * different struct clk_hw). We fallback to the global
2139                          * naming string mechanism so vpu_1_div picks up the
2140                          * appropriate one.
2141                          */
2142                         .name = "vpu_1_sel",
2143                         .index = -1,
2144                 },
2145                 .num_parents = 1,
2146                 .flags = CLK_SET_RATE_PARENT,
2147         },
2148 };
2149
2150 static struct clk_regmap meson8b_vpu_1 = {
2151         .data = &(struct clk_regmap_gate_data){
2152                 .offset = HHI_VPU_CLK_CNTL,
2153                 .bit_idx = 24,
2154         },
2155         .hw.init = &(struct clk_init_data) {
2156                 .name = "vpu_1",
2157                 .ops = &clk_regmap_gate_ops,
2158                 .parent_hws = (const struct clk_hw *[]) {
2159                         &meson8b_vpu_1_div.hw
2160                 },
2161                 .num_parents = 1,
2162                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
2163         },
2164 };
2165
2166 /*
2167  * The VPU clock has two two identical clock trees (vpu_0 and vpu_1)
2168  * muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
2169  * actually manage this glitch-free mux because it does top-to-bottom
2170  * updates the each clock tree and switches to the "inactive" one when
2171  * CLK_SET_RATE_GATE is set.
2172  * Meson8 only has vpu_0 and no glitch-free mux.
2173  */
2174 static struct clk_regmap meson8b_vpu = {
2175         .data = &(struct clk_regmap_mux_data){
2176                 .offset = HHI_VPU_CLK_CNTL,
2177                 .mask = 1,
2178                 .shift = 31,
2179         },
2180         .hw.init = &(struct clk_init_data){
2181                 .name = "vpu",
2182                 .ops = &clk_regmap_mux_ops,
2183                 .parent_hws = (const struct clk_hw *[]) {
2184                         &meson8b_vpu_0.hw,
2185                         &meson8b_vpu_1.hw,
2186                 },
2187                 .num_parents = 2,
2188                 .flags = CLK_SET_RATE_PARENT,
2189         },
2190 };
2191
2192 static const struct clk_hw *meson8b_vdec_parent_hws[] = {
2193         &meson8b_fclk_div4.hw,
2194         &meson8b_fclk_div3.hw,
2195         &meson8b_fclk_div5.hw,
2196         &meson8b_fclk_div7.hw,
2197         &meson8b_mpll2.hw,
2198         &meson8b_mpll1.hw,
2199 };
2200
2201 static struct clk_regmap meson8b_vdec_1_sel = {
2202         .data = &(struct clk_regmap_mux_data){
2203                 .offset = HHI_VDEC_CLK_CNTL,
2204                 .mask = 0x3,
2205                 .shift = 9,
2206                 .flags = CLK_MUX_ROUND_CLOSEST,
2207         },
2208         .hw.init = &(struct clk_init_data){
2209                 .name = "vdec_1_sel",
2210                 .ops = &clk_regmap_mux_ops,
2211                 .parent_hws = meson8b_vdec_parent_hws,
2212                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2213                 .flags = CLK_SET_RATE_PARENT,
2214         },
2215 };
2216
2217 static struct clk_regmap meson8b_vdec_1_1_div = {
2218         .data = &(struct clk_regmap_div_data){
2219                 .offset = HHI_VDEC_CLK_CNTL,
2220                 .shift = 0,
2221                 .width = 7,
2222                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2223         },
2224         .hw.init = &(struct clk_init_data){
2225                 .name = "vdec_1_1_div",
2226                 .ops = &clk_regmap_divider_ops,
2227                 .parent_hws = (const struct clk_hw *[]) {
2228                         &meson8b_vdec_1_sel.hw
2229                 },
2230                 .num_parents = 1,
2231                 .flags = CLK_SET_RATE_PARENT,
2232         },
2233 };
2234
2235 static struct clk_regmap meson8b_vdec_1_1 = {
2236         .data = &(struct clk_regmap_gate_data){
2237                 .offset = HHI_VDEC_CLK_CNTL,
2238                 .bit_idx = 8,
2239         },
2240         .hw.init = &(struct clk_init_data) {
2241                 .name = "vdec_1_1",
2242                 .ops = &clk_regmap_gate_ops,
2243                 .parent_hws = (const struct clk_hw *[]) {
2244                         &meson8b_vdec_1_1_div.hw
2245                 },
2246                 .num_parents = 1,
2247                 .flags = CLK_SET_RATE_PARENT,
2248         },
2249 };
2250
2251 static struct clk_regmap meson8b_vdec_1_2_div = {
2252         .data = &(struct clk_regmap_div_data){
2253                 .offset = HHI_VDEC3_CLK_CNTL,
2254                 .shift = 0,
2255                 .width = 7,
2256                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2257         },
2258         .hw.init = &(struct clk_init_data){
2259                 .name = "vdec_1_2_div",
2260                 .ops = &clk_regmap_divider_ops,
2261                 .parent_hws = (const struct clk_hw *[]) {
2262                         &meson8b_vdec_1_sel.hw
2263                 },
2264                 .num_parents = 1,
2265                 .flags = CLK_SET_RATE_PARENT,
2266         },
2267 };
2268
2269 static struct clk_regmap meson8b_vdec_1_2 = {
2270         .data = &(struct clk_regmap_gate_data){
2271                 .offset = HHI_VDEC3_CLK_CNTL,
2272                 .bit_idx = 8,
2273         },
2274         .hw.init = &(struct clk_init_data) {
2275                 .name = "vdec_1_2",
2276                 .ops = &clk_regmap_gate_ops,
2277                 .parent_hws = (const struct clk_hw *[]) {
2278                         &meson8b_vdec_1_2_div.hw
2279                 },
2280                 .num_parents = 1,
2281                 .flags = CLK_SET_RATE_PARENT,
2282         },
2283 };
2284
2285 static struct clk_regmap meson8b_vdec_1 = {
2286         .data = &(struct clk_regmap_mux_data){
2287                 .offset = HHI_VDEC3_CLK_CNTL,
2288                 .mask = 0x1,
2289                 .shift = 15,
2290                 .flags = CLK_MUX_ROUND_CLOSEST,
2291         },
2292         .hw.init = &(struct clk_init_data){
2293                 .name = "vdec_1",
2294                 .ops = &clk_regmap_mux_ops,
2295                 .parent_hws = (const struct clk_hw *[]) {
2296                         &meson8b_vdec_1_1.hw,
2297                         &meson8b_vdec_1_2.hw,
2298                 },
2299                 .num_parents = 2,
2300                 .flags = CLK_SET_RATE_PARENT,
2301         },
2302 };
2303
2304 static struct clk_regmap meson8b_vdec_hcodec_sel = {
2305         .data = &(struct clk_regmap_mux_data){
2306                 .offset = HHI_VDEC_CLK_CNTL,
2307                 .mask = 0x3,
2308                 .shift = 25,
2309                 .flags = CLK_MUX_ROUND_CLOSEST,
2310         },
2311         .hw.init = &(struct clk_init_data){
2312                 .name = "vdec_hcodec_sel",
2313                 .ops = &clk_regmap_mux_ops,
2314                 .parent_hws = meson8b_vdec_parent_hws,
2315                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2316                 .flags = CLK_SET_RATE_PARENT,
2317         },
2318 };
2319
2320 static struct clk_regmap meson8b_vdec_hcodec_div = {
2321         .data = &(struct clk_regmap_div_data){
2322                 .offset = HHI_VDEC_CLK_CNTL,
2323                 .shift = 16,
2324                 .width = 7,
2325                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2326         },
2327         .hw.init = &(struct clk_init_data){
2328                 .name = "vdec_hcodec_div",
2329                 .ops = &clk_regmap_divider_ops,
2330                 .parent_hws = (const struct clk_hw *[]) {
2331                         &meson8b_vdec_hcodec_sel.hw
2332                 },
2333                 .num_parents = 1,
2334                 .flags = CLK_SET_RATE_PARENT,
2335         },
2336 };
2337
2338 static struct clk_regmap meson8b_vdec_hcodec = {
2339         .data = &(struct clk_regmap_gate_data){
2340                 .offset = HHI_VDEC_CLK_CNTL,
2341                 .bit_idx = 24,
2342         },
2343         .hw.init = &(struct clk_init_data) {
2344                 .name = "vdec_hcodec",
2345                 .ops = &clk_regmap_gate_ops,
2346                 .parent_hws = (const struct clk_hw *[]) {
2347                         &meson8b_vdec_hcodec_div.hw
2348                 },
2349                 .num_parents = 1,
2350                 .flags = CLK_SET_RATE_PARENT,
2351         },
2352 };
2353
2354 static struct clk_regmap meson8b_vdec_2_sel = {
2355         .data = &(struct clk_regmap_mux_data){
2356                 .offset = HHI_VDEC2_CLK_CNTL,
2357                 .mask = 0x3,
2358                 .shift = 9,
2359                 .flags = CLK_MUX_ROUND_CLOSEST,
2360         },
2361         .hw.init = &(struct clk_init_data){
2362                 .name = "vdec_2_sel",
2363                 .ops = &clk_regmap_mux_ops,
2364                 .parent_hws = meson8b_vdec_parent_hws,
2365                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2366                 .flags = CLK_SET_RATE_PARENT,
2367         },
2368 };
2369
2370 static struct clk_regmap meson8b_vdec_2_div = {
2371         .data = &(struct clk_regmap_div_data){
2372                 .offset = HHI_VDEC2_CLK_CNTL,
2373                 .shift = 0,
2374                 .width = 7,
2375                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2376         },
2377         .hw.init = &(struct clk_init_data){
2378                 .name = "vdec_2_div",
2379                 .ops = &clk_regmap_divider_ops,
2380                 .parent_hws = (const struct clk_hw *[]) {
2381                         &meson8b_vdec_2_sel.hw
2382                 },
2383                 .num_parents = 1,
2384                 .flags = CLK_SET_RATE_PARENT,
2385         },
2386 };
2387
2388 static struct clk_regmap meson8b_vdec_2 = {
2389         .data = &(struct clk_regmap_gate_data){
2390                 .offset = HHI_VDEC2_CLK_CNTL,
2391                 .bit_idx = 8,
2392         },
2393         .hw.init = &(struct clk_init_data) {
2394                 .name = "vdec_2",
2395                 .ops = &clk_regmap_gate_ops,
2396                 .parent_hws = (const struct clk_hw *[]) {
2397                         &meson8b_vdec_2_div.hw
2398                 },
2399                 .num_parents = 1,
2400                 .flags = CLK_SET_RATE_PARENT,
2401         },
2402 };
2403
2404 static struct clk_regmap meson8b_vdec_hevc_sel = {
2405         .data = &(struct clk_regmap_mux_data){
2406                 .offset = HHI_VDEC2_CLK_CNTL,
2407                 .mask = 0x3,
2408                 .shift = 25,
2409                 .flags = CLK_MUX_ROUND_CLOSEST,
2410         },
2411         .hw.init = &(struct clk_init_data){
2412                 .name = "vdec_hevc_sel",
2413                 .ops = &clk_regmap_mux_ops,
2414                 .parent_hws = meson8b_vdec_parent_hws,
2415                 .num_parents = ARRAY_SIZE(meson8b_vdec_parent_hws),
2416                 .flags = CLK_SET_RATE_PARENT,
2417         },
2418 };
2419
2420 static struct clk_regmap meson8b_vdec_hevc_div = {
2421         .data = &(struct clk_regmap_div_data){
2422                 .offset = HHI_VDEC2_CLK_CNTL,
2423                 .shift = 16,
2424                 .width = 7,
2425                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2426         },
2427         .hw.init = &(struct clk_init_data){
2428                 .name = "vdec_hevc_div",
2429                 .ops = &clk_regmap_divider_ops,
2430                 .parent_hws = (const struct clk_hw *[]) {
2431                         &meson8b_vdec_hevc_sel.hw
2432                 },
2433                 .num_parents = 1,
2434                 .flags = CLK_SET_RATE_PARENT,
2435         },
2436 };
2437
2438 static struct clk_regmap meson8b_vdec_hevc_en = {
2439         .data = &(struct clk_regmap_gate_data){
2440                 .offset = HHI_VDEC2_CLK_CNTL,
2441                 .bit_idx = 24,
2442         },
2443         .hw.init = &(struct clk_init_data) {
2444                 .name = "vdec_hevc_en",
2445                 .ops = &clk_regmap_gate_ops,
2446                 .parent_hws = (const struct clk_hw *[]) {
2447                         &meson8b_vdec_hevc_div.hw
2448                 },
2449                 .num_parents = 1,
2450                 .flags = CLK_SET_RATE_PARENT,
2451         },
2452 };
2453
2454 static struct clk_regmap meson8b_vdec_hevc = {
2455         .data = &(struct clk_regmap_mux_data){
2456                 .offset = HHI_VDEC2_CLK_CNTL,
2457                 .mask = 0x1,
2458                 .shift = 31,
2459                 .flags = CLK_MUX_ROUND_CLOSEST,
2460         },
2461         .hw.init = &(struct clk_init_data){
2462                 .name = "vdec_hevc",
2463                 .ops = &clk_regmap_mux_ops,
2464                 /* TODO: The second parent is currently unknown */
2465                 .parent_hws = (const struct clk_hw *[]) {
2466                         &meson8b_vdec_hevc_en.hw
2467                 },
2468                 .num_parents = 1,
2469                 .flags = CLK_SET_RATE_PARENT,
2470         },
2471 };
2472
2473 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2474 static const struct clk_hw *meson8b_cts_amclk_parent_hws[] = {
2475         &meson8b_mpll0.hw,
2476         &meson8b_mpll1.hw,
2477         &meson8b_mpll2.hw
2478 };
2479
2480 static u32 meson8b_cts_amclk_mux_table[] = { 1, 2, 3 };
2481
2482 static struct clk_regmap meson8b_cts_amclk_sel = {
2483         .data = &(struct clk_regmap_mux_data){
2484                 .offset = HHI_AUD_CLK_CNTL,
2485                 .mask = 0x3,
2486                 .shift = 9,
2487                 .table = meson8b_cts_amclk_mux_table,
2488                 .flags = CLK_MUX_ROUND_CLOSEST,
2489         },
2490         .hw.init = &(struct clk_init_data){
2491                 .name = "cts_amclk_sel",
2492                 .ops = &clk_regmap_mux_ops,
2493                 .parent_hws = meson8b_cts_amclk_parent_hws,
2494                 .num_parents = ARRAY_SIZE(meson8b_cts_amclk_parent_hws),
2495         },
2496 };
2497
2498 static struct clk_regmap meson8b_cts_amclk_div = {
2499         .data = &(struct clk_regmap_div_data) {
2500                 .offset = HHI_AUD_CLK_CNTL,
2501                 .shift = 0,
2502                 .width = 8,
2503                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2504         },
2505         .hw.init = &(struct clk_init_data){
2506                 .name = "cts_amclk_div",
2507                 .ops = &clk_regmap_divider_ops,
2508                 .parent_hws = (const struct clk_hw *[]) {
2509                         &meson8b_cts_amclk_sel.hw
2510                 },
2511                 .num_parents = 1,
2512                 .flags = CLK_SET_RATE_PARENT,
2513         },
2514 };
2515
2516 static struct clk_regmap meson8b_cts_amclk = {
2517         .data = &(struct clk_regmap_gate_data){
2518                 .offset = HHI_AUD_CLK_CNTL,
2519                 .bit_idx = 8,
2520         },
2521         .hw.init = &(struct clk_init_data){
2522                 .name = "cts_amclk",
2523                 .ops = &clk_regmap_gate_ops,
2524                 .parent_hws = (const struct clk_hw *[]) {
2525                         &meson8b_cts_amclk_div.hw
2526                 },
2527                 .num_parents = 1,
2528                 .flags = CLK_SET_RATE_PARENT,
2529         },
2530 };
2531
2532 /* TODO: the clock at index 0 is "DDR_PLL" which we don't support yet */
2533 static const struct clk_hw *meson8b_cts_mclk_i958_parent_hws[] = {
2534         &meson8b_mpll0.hw,
2535         &meson8b_mpll1.hw,
2536         &meson8b_mpll2.hw
2537 };
2538
2539 static u32 meson8b_cts_mclk_i958_mux_table[] = { 1, 2, 3 };
2540
2541 static struct clk_regmap meson8b_cts_mclk_i958_sel = {
2542         .data = &(struct clk_regmap_mux_data){
2543                 .offset = HHI_AUD_CLK_CNTL2,
2544                 .mask = 0x3,
2545                 .shift = 25,
2546                 .table = meson8b_cts_mclk_i958_mux_table,
2547                 .flags = CLK_MUX_ROUND_CLOSEST,
2548         },
2549         .hw.init = &(struct clk_init_data) {
2550                 .name = "cts_mclk_i958_sel",
2551                 .ops = &clk_regmap_mux_ops,
2552                 .parent_hws = meson8b_cts_mclk_i958_parent_hws,
2553                 .num_parents = ARRAY_SIZE(meson8b_cts_mclk_i958_parent_hws),
2554         },
2555 };
2556
2557 static struct clk_regmap meson8b_cts_mclk_i958_div = {
2558         .data = &(struct clk_regmap_div_data){
2559                 .offset = HHI_AUD_CLK_CNTL2,
2560                 .shift = 16,
2561                 .width = 8,
2562                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2563         },
2564         .hw.init = &(struct clk_init_data) {
2565                 .name = "cts_mclk_i958_div",
2566                 .ops = &clk_regmap_divider_ops,
2567                 .parent_hws = (const struct clk_hw *[]) {
2568                         &meson8b_cts_mclk_i958_sel.hw
2569                 },
2570                 .num_parents = 1,
2571                 .flags = CLK_SET_RATE_PARENT,
2572         },
2573 };
2574
2575 static struct clk_regmap meson8b_cts_mclk_i958 = {
2576         .data = &(struct clk_regmap_gate_data){
2577                 .offset = HHI_AUD_CLK_CNTL2,
2578                 .bit_idx = 24,
2579         },
2580         .hw.init = &(struct clk_init_data){
2581                 .name = "cts_mclk_i958",
2582                 .ops = &clk_regmap_gate_ops,
2583                 .parent_hws = (const struct clk_hw *[]) {
2584                         &meson8b_cts_mclk_i958_div.hw
2585                 },
2586                 .num_parents = 1,
2587                 .flags = CLK_SET_RATE_PARENT,
2588         },
2589 };
2590
2591 static struct clk_regmap meson8b_cts_i958 = {
2592         .data = &(struct clk_regmap_mux_data){
2593                 .offset = HHI_AUD_CLK_CNTL2,
2594                 .mask = 0x1,
2595                 .shift = 27,
2596                 },
2597         .hw.init = &(struct clk_init_data){
2598                 .name = "cts_i958",
2599                 .ops = &clk_regmap_mux_ops,
2600                 .parent_hws = (const struct clk_hw *[]) {
2601                         &meson8b_cts_amclk.hw,
2602                         &meson8b_cts_mclk_i958.hw
2603                 },
2604                 .num_parents = 2,
2605                 /*
2606                  * The parent is specific to origin of the audio data. Let the
2607                  * consumer choose the appropriate parent.
2608                  */
2609                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
2610         },
2611 };
2612
2613 #define MESON_GATE(_name, _reg, _bit) \
2614         MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw)
2615
2616 /* Everything Else (EE) domain gates */
2617
2618 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
2619 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
2620 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
2621 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
2622 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
2623 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
2624 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
2625 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
2626 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
2627 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
2628 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
2629 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
2630 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
2631 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
2632 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
2633 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
2634 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
2635 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
2636 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
2637
2638 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
2639 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
2640 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
2641 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
2642 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
2643 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
2644 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
2645 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
2646 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
2647 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
2648 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
2649 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
2650 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
2651 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
2652 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
2653 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
2654 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
2655
2656 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2657 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2658 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2659 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2660 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2661 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2662 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
2663 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
2664 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
2665 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
2666 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
2667 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2668 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
2669
2670 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
2671 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
2672 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2673 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2674 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
2675 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2676 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
2677 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
2678 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
2679 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
2680 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
2681 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
2682 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2683 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
2684 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
2685 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
2686
2687 /* AIU gates */
2688 #define MESON_AIU_GLUE_GATE(_name, _reg, _bit) \
2689         MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw)
2690
2691 static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw);
2692 static MESON_AIU_GLUE_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
2693 static MESON_AIU_GLUE_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
2694 static MESON_AIU_GLUE_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
2695 static MESON_AIU_GLUE_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
2696 static MESON_AIU_GLUE_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
2697 static MESON_AIU_GLUE_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
2698 static MESON_AIU_GLUE_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
2699
2700 /* Always On (AO) domain gates */
2701
2702 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
2703 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
2704 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
2705 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
2706
2707 static struct clk_hw_onecell_data meson8_hw_onecell_data = {
2708         .hws = {
2709                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2710                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2711                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2712                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2713                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2714                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2715                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2716                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2717                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2718                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2719                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2720                 [CLKID_CLK81] = &meson8b_clk81.hw,
2721                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2722                 [CLKID_DOS]                 = &meson8b_dos.hw,
2723                 [CLKID_ISA]                 = &meson8b_isa.hw,
2724                 [CLKID_PL301]               = &meson8b_pl301.hw,
2725                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2726                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2727                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2728                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2729                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2730                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2731                 [CLKID_UART0]               = &meson8b_uart0.hw,
2732                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2733                 [CLKID_STREAM]              = &meson8b_stream.hw,
2734                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2735                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2736                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2737                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2738                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2739                 [CLKID_SPI]                 = &meson8b_spi.hw,
2740                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2741                 [CLKID_ETH]                 = &meson8b_eth.hw,
2742                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2743                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2744                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2745                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2746                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2747                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2748                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2749                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2750                 [CLKID_ADC]                 = &meson8b_adc.hw,
2751                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2752                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2753                 [CLKID_UART1]               = &meson8b_uart1.hw,
2754                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2755                 [CLKID_USB0]                = &meson8b_usb0.hw,
2756                 [CLKID_USB1]                = &meson8b_usb1.hw,
2757                 [CLKID_RESET]               = &meson8b_reset.hw,
2758                 [CLKID_NAND]                = &meson8b_nand.hw,
2759                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2760                 [CLKID_USB]                 = &meson8b_usb.hw,
2761                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2762                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2763                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2764                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2765                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2766                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2767                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2768                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2769                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2770                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2771                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2772                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2773                 [CLKID_UART2]               = &meson8b_uart2.hw,
2774                 [CLKID_SANA]                = &meson8b_sana.hw,
2775                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2776                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2777                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2778                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2779                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2780                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2781                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2782                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2783                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2784                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2785                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2786                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2787                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2788                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2789                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2790                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2791                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2792                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2793                 [CLKID_EDP]                 = &meson8b_edp.hw,
2794                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
2795                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
2796                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
2797                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
2798                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
2799                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
2800                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
2801                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
2802                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
2803                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
2804                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
2805                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
2806                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
2807                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
2808                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
2809                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
2810                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
2811                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
2812                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
2813                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
2814                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
2815                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
2816                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
2817                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
2818                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
2819                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
2820                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
2821                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
2822                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
2823                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
2824                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
2825                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
2826                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
2827                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
2828                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
2829                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
2830                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
2831                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
2832                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
2833                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
2834                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
2835                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
2836                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
2837                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
2838                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
2839                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
2840                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
2841                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
2842                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
2843                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
2844                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
2845                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
2846                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
2847                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
2848                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
2849                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
2850                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
2851                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
2852                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
2853                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
2854                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
2855                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
2856                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
2857                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
2858                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
2859                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
2860                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
2861                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
2862                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
2863                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
2864                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
2865                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
2866                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
2867                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
2868                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
2869                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
2870                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
2871                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
2872                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
2873                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
2874                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
2875                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
2876                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
2877                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
2878                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
2879                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
2880                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
2881                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
2882                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
2883                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
2884                 [CLKID_MALI]                = &meson8b_mali_0.hw,
2885                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
2886                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
2887                 [CLKID_VPU]                 = &meson8b_vpu_0.hw,
2888                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
2889                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
2890                 [CLKID_VDEC_1]              = &meson8b_vdec_1_1.hw,
2891                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
2892                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
2893                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
2894                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
2895                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
2896                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
2897                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
2898                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
2899                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
2900                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
2901                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
2902                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
2903                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
2904                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
2905                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
2906                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
2907                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
2908                 [CLK_NR_CLKS]               = NULL,
2909         },
2910         .num = CLK_NR_CLKS,
2911 };
2912
2913 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
2914         .hws = {
2915                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
2916                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
2917                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
2918                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
2919                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
2920                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
2921                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
2922                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
2923                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
2924                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
2925                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
2926                 [CLKID_CLK81] = &meson8b_clk81.hw,
2927                 [CLKID_DDR]                 = &meson8b_ddr.hw,
2928                 [CLKID_DOS]                 = &meson8b_dos.hw,
2929                 [CLKID_ISA]                 = &meson8b_isa.hw,
2930                 [CLKID_PL301]               = &meson8b_pl301.hw,
2931                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
2932                 [CLKID_SPICC]               = &meson8b_spicc.hw,
2933                 [CLKID_I2C]                 = &meson8b_i2c.hw,
2934                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
2935                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
2936                 [CLKID_RNG0]                = &meson8b_rng0.hw,
2937                 [CLKID_UART0]               = &meson8b_uart0.hw,
2938                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
2939                 [CLKID_STREAM]              = &meson8b_stream.hw,
2940                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
2941                 [CLKID_SDIO]                = &meson8b_sdio.hw,
2942                 [CLKID_ABUF]                = &meson8b_abuf.hw,
2943                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
2944                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
2945                 [CLKID_SPI]                 = &meson8b_spi.hw,
2946                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
2947                 [CLKID_ETH]                 = &meson8b_eth.hw,
2948                 [CLKID_DEMUX]               = &meson8b_demux.hw,
2949                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
2950                 [CLKID_IEC958]              = &meson8b_iec958.hw,
2951                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
2952                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
2953                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
2954                 [CLKID_MIXER]               = &meson8b_mixer.hw,
2955                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
2956                 [CLKID_ADC]                 = &meson8b_adc.hw,
2957                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
2958                 [CLKID_AIU]                 = &meson8b_aiu.hw,
2959                 [CLKID_UART1]               = &meson8b_uart1.hw,
2960                 [CLKID_G2D]                 = &meson8b_g2d.hw,
2961                 [CLKID_USB0]                = &meson8b_usb0.hw,
2962                 [CLKID_USB1]                = &meson8b_usb1.hw,
2963                 [CLKID_RESET]               = &meson8b_reset.hw,
2964                 [CLKID_NAND]                = &meson8b_nand.hw,
2965                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
2966                 [CLKID_USB]                 = &meson8b_usb.hw,
2967                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
2968                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
2969                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
2970                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
2971                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
2972                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
2973                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
2974                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
2975                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
2976                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
2977                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
2978                 [CLKID_DVIN]                = &meson8b_dvin.hw,
2979                 [CLKID_UART2]               = &meson8b_uart2.hw,
2980                 [CLKID_SANA]                = &meson8b_sana.hw,
2981                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
2982                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2983                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
2984                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
2985                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
2986                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
2987                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
2988                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
2989                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
2990                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
2991                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
2992                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
2993                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
2994                 [CLKID_RNG1]                = &meson8b_rng1.hw,
2995                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
2996                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
2997                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
2998                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
2999                 [CLKID_EDP]                 = &meson8b_edp.hw,
3000                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3001                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3002                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3003                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3004                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3005                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3006                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3007                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3008                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3009                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3010                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3011                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3012                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3013                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3014                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3015                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3016                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3017                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3018                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3019                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3020                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3021                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3022                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3023                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3024                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3025                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3026                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3027                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3028                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3029                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3030                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3031                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3032                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3033                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3034                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3035                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3036                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3037                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3038                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3039                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3040                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3041                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3042                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3043                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3044                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3045                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3046                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3047                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3048                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3049                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3050                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3051                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3052                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3053                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3054                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3055                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3056                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3057                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3058                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3059                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3060                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3061                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3062                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3063                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3064                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3065                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3066                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3067                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3068                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3069                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3070                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3071                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3072                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3073                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3074                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3075                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3076                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3077                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3078                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3079                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3080                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3081                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3082                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3083                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3084                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3085                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3086                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3087                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3088                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3089                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3090                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3091                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3092                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3093                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3094                 [CLKID_MALI]                = &meson8b_mali.hw,
3095                 [CLKID_VPU_0_SEL]           = &meson8b_vpu_0_sel.hw,
3096                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3097                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3098                 [CLKID_VPU_1_SEL]           = &meson8b_vpu_1_sel.hw,
3099                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3100                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3101                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3102                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3103                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3104                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3105                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3106                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3107                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3108                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3109                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3110                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3111                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3112                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3113                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3114                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3115                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3116                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3117                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3118                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3119                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3120                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3121                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3122                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3123                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3124                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3125                 [CLK_NR_CLKS]               = NULL,
3126         },
3127         .num = CLK_NR_CLKS,
3128 };
3129
3130 static struct clk_hw_onecell_data meson8m2_hw_onecell_data = {
3131         .hws = {
3132                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
3133                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
3134                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
3135                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
3136                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
3137                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
3138                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
3139                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
3140                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
3141                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
3142                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
3143                 [CLKID_CLK81] = &meson8b_clk81.hw,
3144                 [CLKID_DDR]                 = &meson8b_ddr.hw,
3145                 [CLKID_DOS]                 = &meson8b_dos.hw,
3146                 [CLKID_ISA]                 = &meson8b_isa.hw,
3147                 [CLKID_PL301]               = &meson8b_pl301.hw,
3148                 [CLKID_PERIPHS]             = &meson8b_periphs.hw,
3149                 [CLKID_SPICC]               = &meson8b_spicc.hw,
3150                 [CLKID_I2C]                 = &meson8b_i2c.hw,
3151                 [CLKID_SAR_ADC]             = &meson8b_sar_adc.hw,
3152                 [CLKID_SMART_CARD]          = &meson8b_smart_card.hw,
3153                 [CLKID_RNG0]                = &meson8b_rng0.hw,
3154                 [CLKID_UART0]               = &meson8b_uart0.hw,
3155                 [CLKID_SDHC]                = &meson8b_sdhc.hw,
3156                 [CLKID_STREAM]              = &meson8b_stream.hw,
3157                 [CLKID_ASYNC_FIFO]          = &meson8b_async_fifo.hw,
3158                 [CLKID_SDIO]                = &meson8b_sdio.hw,
3159                 [CLKID_ABUF]                = &meson8b_abuf.hw,
3160                 [CLKID_HIU_IFACE]           = &meson8b_hiu_iface.hw,
3161                 [CLKID_ASSIST_MISC]         = &meson8b_assist_misc.hw,
3162                 [CLKID_SPI]                 = &meson8b_spi.hw,
3163                 [CLKID_I2S_SPDIF]           = &meson8b_i2s_spdif.hw,
3164                 [CLKID_ETH]                 = &meson8b_eth.hw,
3165                 [CLKID_DEMUX]               = &meson8b_demux.hw,
3166                 [CLKID_AIU_GLUE]            = &meson8b_aiu_glue.hw,
3167                 [CLKID_IEC958]              = &meson8b_iec958.hw,
3168                 [CLKID_I2S_OUT]             = &meson8b_i2s_out.hw,
3169                 [CLKID_AMCLK]               = &meson8b_amclk.hw,
3170                 [CLKID_AIFIFO2]             = &meson8b_aififo2.hw,
3171                 [CLKID_MIXER]               = &meson8b_mixer.hw,
3172                 [CLKID_MIXER_IFACE]         = &meson8b_mixer_iface.hw,
3173                 [CLKID_ADC]                 = &meson8b_adc.hw,
3174                 [CLKID_BLKMV]               = &meson8b_blkmv.hw,
3175                 [CLKID_AIU]                 = &meson8b_aiu.hw,
3176                 [CLKID_UART1]               = &meson8b_uart1.hw,
3177                 [CLKID_G2D]                 = &meson8b_g2d.hw,
3178                 [CLKID_USB0]                = &meson8b_usb0.hw,
3179                 [CLKID_USB1]                = &meson8b_usb1.hw,
3180                 [CLKID_RESET]               = &meson8b_reset.hw,
3181                 [CLKID_NAND]                = &meson8b_nand.hw,
3182                 [CLKID_DOS_PARSER]          = &meson8b_dos_parser.hw,
3183                 [CLKID_USB]                 = &meson8b_usb.hw,
3184                 [CLKID_VDIN1]               = &meson8b_vdin1.hw,
3185                 [CLKID_AHB_ARB0]            = &meson8b_ahb_arb0.hw,
3186                 [CLKID_EFUSE]               = &meson8b_efuse.hw,
3187                 [CLKID_BOOT_ROM]            = &meson8b_boot_rom.hw,
3188                 [CLKID_AHB_DATA_BUS]        = &meson8b_ahb_data_bus.hw,
3189                 [CLKID_AHB_CTRL_BUS]        = &meson8b_ahb_ctrl_bus.hw,
3190                 [CLKID_HDMI_INTR_SYNC]      = &meson8b_hdmi_intr_sync.hw,
3191                 [CLKID_HDMI_PCLK]           = &meson8b_hdmi_pclk.hw,
3192                 [CLKID_USB1_DDR_BRIDGE]     = &meson8b_usb1_ddr_bridge.hw,
3193                 [CLKID_USB0_DDR_BRIDGE]     = &meson8b_usb0_ddr_bridge.hw,
3194                 [CLKID_MMC_PCLK]            = &meson8b_mmc_pclk.hw,
3195                 [CLKID_DVIN]                = &meson8b_dvin.hw,
3196                 [CLKID_UART2]               = &meson8b_uart2.hw,
3197                 [CLKID_SANA]                = &meson8b_sana.hw,
3198                 [CLKID_VPU_INTR]            = &meson8b_vpu_intr.hw,
3199                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
3200                 [CLKID_CLK81_A9]            = &meson8b_clk81_a9.hw,
3201                 [CLKID_VCLK2_VENCI0]        = &meson8b_vclk2_venci0.hw,
3202                 [CLKID_VCLK2_VENCI1]        = &meson8b_vclk2_venci1.hw,
3203                 [CLKID_VCLK2_VENCP0]        = &meson8b_vclk2_vencp0.hw,
3204                 [CLKID_VCLK2_VENCP1]        = &meson8b_vclk2_vencp1.hw,
3205                 [CLKID_GCLK_VENCI_INT]      = &meson8b_gclk_venci_int.hw,
3206                 [CLKID_GCLK_VENCP_INT]      = &meson8b_gclk_vencp_int.hw,
3207                 [CLKID_DAC_CLK]             = &meson8b_dac_clk.hw,
3208                 [CLKID_AOCLK_GATE]          = &meson8b_aoclk_gate.hw,
3209                 [CLKID_IEC958_GATE]         = &meson8b_iec958_gate.hw,
3210                 [CLKID_ENC480P]             = &meson8b_enc480p.hw,
3211                 [CLKID_RNG1]                = &meson8b_rng1.hw,
3212                 [CLKID_GCLK_VENCL_INT]      = &meson8b_gclk_vencl_int.hw,
3213                 [CLKID_VCLK2_VENCLMCC]      = &meson8b_vclk2_venclmcc.hw,
3214                 [CLKID_VCLK2_VENCL]         = &meson8b_vclk2_vencl.hw,
3215                 [CLKID_VCLK2_OTHER]         = &meson8b_vclk2_other.hw,
3216                 [CLKID_EDP]                 = &meson8b_edp.hw,
3217                 [CLKID_AO_MEDIA_CPU]        = &meson8b_ao_media_cpu.hw,
3218                 [CLKID_AO_AHB_SRAM]         = &meson8b_ao_ahb_sram.hw,
3219                 [CLKID_AO_AHB_BUS]          = &meson8b_ao_ahb_bus.hw,
3220                 [CLKID_AO_IFACE]            = &meson8b_ao_iface.hw,
3221                 [CLKID_MPLL0]               = &meson8b_mpll0.hw,
3222                 [CLKID_MPLL1]               = &meson8b_mpll1.hw,
3223                 [CLKID_MPLL2]               = &meson8b_mpll2.hw,
3224                 [CLKID_MPLL0_DIV]           = &meson8b_mpll0_div.hw,
3225                 [CLKID_MPLL1_DIV]           = &meson8b_mpll1_div.hw,
3226                 [CLKID_MPLL2_DIV]           = &meson8b_mpll2_div.hw,
3227                 [CLKID_CPU_IN_SEL]          = &meson8b_cpu_in_sel.hw,
3228                 [CLKID_CPU_IN_DIV2]         = &meson8b_cpu_in_div2.hw,
3229                 [CLKID_CPU_IN_DIV3]         = &meson8b_cpu_in_div3.hw,
3230                 [CLKID_CPU_SCALE_DIV]       = &meson8b_cpu_scale_div.hw,
3231                 [CLKID_CPU_SCALE_OUT_SEL]   = &meson8b_cpu_scale_out_sel.hw,
3232                 [CLKID_MPLL_PREDIV]         = &meson8b_mpll_prediv.hw,
3233                 [CLKID_FCLK_DIV2_DIV]       = &meson8b_fclk_div2_div.hw,
3234                 [CLKID_FCLK_DIV3_DIV]       = &meson8b_fclk_div3_div.hw,
3235                 [CLKID_FCLK_DIV4_DIV]       = &meson8b_fclk_div4_div.hw,
3236                 [CLKID_FCLK_DIV5_DIV]       = &meson8b_fclk_div5_div.hw,
3237                 [CLKID_FCLK_DIV7_DIV]       = &meson8b_fclk_div7_div.hw,
3238                 [CLKID_NAND_SEL]            = &meson8b_nand_clk_sel.hw,
3239                 [CLKID_NAND_DIV]            = &meson8b_nand_clk_div.hw,
3240                 [CLKID_NAND_CLK]            = &meson8b_nand_clk_gate.hw,
3241                 [CLKID_PLL_FIXED_DCO]       = &meson8b_fixed_pll_dco.hw,
3242                 [CLKID_HDMI_PLL_DCO]        = &meson8b_hdmi_pll_dco.hw,
3243                 [CLKID_PLL_SYS_DCO]         = &meson8b_sys_pll_dco.hw,
3244                 [CLKID_CPU_CLK_DIV2]        = &meson8b_cpu_clk_div2.hw,
3245                 [CLKID_CPU_CLK_DIV3]        = &meson8b_cpu_clk_div3.hw,
3246                 [CLKID_CPU_CLK_DIV4]        = &meson8b_cpu_clk_div4.hw,
3247                 [CLKID_CPU_CLK_DIV5]        = &meson8b_cpu_clk_div5.hw,
3248                 [CLKID_CPU_CLK_DIV6]        = &meson8b_cpu_clk_div6.hw,
3249                 [CLKID_CPU_CLK_DIV7]        = &meson8b_cpu_clk_div7.hw,
3250                 [CLKID_CPU_CLK_DIV8]        = &meson8b_cpu_clk_div8.hw,
3251                 [CLKID_APB_SEL]             = &meson8b_apb_clk_sel.hw,
3252                 [CLKID_APB]                 = &meson8b_apb_clk_gate.hw,
3253                 [CLKID_PERIPH_SEL]          = &meson8b_periph_clk_sel.hw,
3254                 [CLKID_PERIPH]              = &meson8b_periph_clk_gate.hw,
3255                 [CLKID_AXI_SEL]             = &meson8b_axi_clk_sel.hw,
3256                 [CLKID_AXI]                 = &meson8b_axi_clk_gate.hw,
3257                 [CLKID_L2_DRAM_SEL]         = &meson8b_l2_dram_clk_sel.hw,
3258                 [CLKID_L2_DRAM]             = &meson8b_l2_dram_clk_gate.hw,
3259                 [CLKID_HDMI_PLL_LVDS_OUT]   = &meson8b_hdmi_pll_lvds_out.hw,
3260                 [CLKID_HDMI_PLL_HDMI_OUT]   = &meson8b_hdmi_pll_hdmi_out.hw,
3261                 [CLKID_VID_PLL_IN_SEL]      = &meson8b_vid_pll_in_sel.hw,
3262                 [CLKID_VID_PLL_IN_EN]       = &meson8b_vid_pll_in_en.hw,
3263                 [CLKID_VID_PLL_PRE_DIV]     = &meson8b_vid_pll_pre_div.hw,
3264                 [CLKID_VID_PLL_POST_DIV]    = &meson8b_vid_pll_post_div.hw,
3265                 [CLKID_VID_PLL_FINAL_DIV]   = &meson8b_vid_pll_final_div.hw,
3266                 [CLKID_VCLK_IN_SEL]         = &meson8b_vclk_in_sel.hw,
3267                 [CLKID_VCLK_IN_EN]          = &meson8b_vclk_in_en.hw,
3268                 [CLKID_VCLK_EN]             = &meson8b_vclk_en.hw,
3269                 [CLKID_VCLK_DIV1]           = &meson8b_vclk_div1_gate.hw,
3270                 [CLKID_VCLK_DIV2_DIV]       = &meson8b_vclk_div2_div.hw,
3271                 [CLKID_VCLK_DIV2]           = &meson8b_vclk_div2_div_gate.hw,
3272                 [CLKID_VCLK_DIV4_DIV]       = &meson8b_vclk_div4_div.hw,
3273                 [CLKID_VCLK_DIV4]           = &meson8b_vclk_div4_div_gate.hw,
3274                 [CLKID_VCLK_DIV6_DIV]       = &meson8b_vclk_div6_div.hw,
3275                 [CLKID_VCLK_DIV6]           = &meson8b_vclk_div6_div_gate.hw,
3276                 [CLKID_VCLK_DIV12_DIV]      = &meson8b_vclk_div12_div.hw,
3277                 [CLKID_VCLK_DIV12]          = &meson8b_vclk_div12_div_gate.hw,
3278                 [CLKID_VCLK2_IN_SEL]        = &meson8b_vclk2_in_sel.hw,
3279                 [CLKID_VCLK2_IN_EN]         = &meson8b_vclk2_clk_in_en.hw,
3280                 [CLKID_VCLK2_EN]            = &meson8b_vclk2_clk_en.hw,
3281                 [CLKID_VCLK2_DIV1]          = &meson8b_vclk2_div1_gate.hw,
3282                 [CLKID_VCLK2_DIV2_DIV]      = &meson8b_vclk2_div2_div.hw,
3283                 [CLKID_VCLK2_DIV2]          = &meson8b_vclk2_div2_div_gate.hw,
3284                 [CLKID_VCLK2_DIV4_DIV]      = &meson8b_vclk2_div4_div.hw,
3285                 [CLKID_VCLK2_DIV4]          = &meson8b_vclk2_div4_div_gate.hw,
3286                 [CLKID_VCLK2_DIV6_DIV]      = &meson8b_vclk2_div6_div.hw,
3287                 [CLKID_VCLK2_DIV6]          = &meson8b_vclk2_div6_div_gate.hw,
3288                 [CLKID_VCLK2_DIV12_DIV]     = &meson8b_vclk2_div12_div.hw,
3289                 [CLKID_VCLK2_DIV12]         = &meson8b_vclk2_div12_div_gate.hw,
3290                 [CLKID_CTS_ENCT_SEL]        = &meson8b_cts_enct_sel.hw,
3291                 [CLKID_CTS_ENCT]            = &meson8b_cts_enct.hw,
3292                 [CLKID_CTS_ENCP_SEL]        = &meson8b_cts_encp_sel.hw,
3293                 [CLKID_CTS_ENCP]            = &meson8b_cts_encp.hw,
3294                 [CLKID_CTS_ENCI_SEL]        = &meson8b_cts_enci_sel.hw,
3295                 [CLKID_CTS_ENCI]            = &meson8b_cts_enci.hw,
3296                 [CLKID_HDMI_TX_PIXEL_SEL]   = &meson8b_hdmi_tx_pixel_sel.hw,
3297                 [CLKID_HDMI_TX_PIXEL]       = &meson8b_hdmi_tx_pixel.hw,
3298                 [CLKID_CTS_ENCL_SEL]        = &meson8b_cts_encl_sel.hw,
3299                 [CLKID_CTS_ENCL]            = &meson8b_cts_encl.hw,
3300                 [CLKID_CTS_VDAC0_SEL]       = &meson8b_cts_vdac0_sel.hw,
3301                 [CLKID_CTS_VDAC0]           = &meson8b_cts_vdac0.hw,
3302                 [CLKID_HDMI_SYS_SEL]        = &meson8b_hdmi_sys_sel.hw,
3303                 [CLKID_HDMI_SYS_DIV]        = &meson8b_hdmi_sys_div.hw,
3304                 [CLKID_HDMI_SYS]            = &meson8b_hdmi_sys.hw,
3305                 [CLKID_MALI_0_SEL]          = &meson8b_mali_0_sel.hw,
3306                 [CLKID_MALI_0_DIV]          = &meson8b_mali_0_div.hw,
3307                 [CLKID_MALI_0]              = &meson8b_mali_0.hw,
3308                 [CLKID_MALI_1_SEL]          = &meson8b_mali_1_sel.hw,
3309                 [CLKID_MALI_1_DIV]          = &meson8b_mali_1_div.hw,
3310                 [CLKID_MALI_1]              = &meson8b_mali_1.hw,
3311                 [CLKID_MALI]                = &meson8b_mali.hw,
3312                 [CLKID_GP_PLL_DCO]          = &meson8m2_gp_pll_dco.hw,
3313                 [CLKID_GP_PLL]              = &meson8m2_gp_pll.hw,
3314                 [CLKID_VPU_0_SEL]           = &meson8m2_vpu_0_sel.hw,
3315                 [CLKID_VPU_0_DIV]           = &meson8b_vpu_0_div.hw,
3316                 [CLKID_VPU_0]               = &meson8b_vpu_0.hw,
3317                 [CLKID_VPU_1_SEL]           = &meson8m2_vpu_1_sel.hw,
3318                 [CLKID_VPU_1_DIV]           = &meson8b_vpu_1_div.hw,
3319                 [CLKID_VPU_1]               = &meson8b_vpu_1.hw,
3320                 [CLKID_VPU]                 = &meson8b_vpu.hw,
3321                 [CLKID_VDEC_1_SEL]          = &meson8b_vdec_1_sel.hw,
3322                 [CLKID_VDEC_1_1_DIV]        = &meson8b_vdec_1_1_div.hw,
3323                 [CLKID_VDEC_1_1]            = &meson8b_vdec_1_1.hw,
3324                 [CLKID_VDEC_1_2_DIV]        = &meson8b_vdec_1_2_div.hw,
3325                 [CLKID_VDEC_1_2]            = &meson8b_vdec_1_2.hw,
3326                 [CLKID_VDEC_1]              = &meson8b_vdec_1.hw,
3327                 [CLKID_VDEC_HCODEC_SEL]     = &meson8b_vdec_hcodec_sel.hw,
3328                 [CLKID_VDEC_HCODEC_DIV]     = &meson8b_vdec_hcodec_div.hw,
3329                 [CLKID_VDEC_HCODEC]         = &meson8b_vdec_hcodec.hw,
3330                 [CLKID_VDEC_2_SEL]          = &meson8b_vdec_2_sel.hw,
3331                 [CLKID_VDEC_2_DIV]          = &meson8b_vdec_2_div.hw,
3332                 [CLKID_VDEC_2]              = &meson8b_vdec_2.hw,
3333                 [CLKID_VDEC_HEVC_SEL]       = &meson8b_vdec_hevc_sel.hw,
3334                 [CLKID_VDEC_HEVC_DIV]       = &meson8b_vdec_hevc_div.hw,
3335                 [CLKID_VDEC_HEVC_EN]        = &meson8b_vdec_hevc_en.hw,
3336                 [CLKID_VDEC_HEVC]           = &meson8b_vdec_hevc.hw,
3337                 [CLKID_CTS_AMCLK_SEL]       = &meson8b_cts_amclk_sel.hw,
3338                 [CLKID_CTS_AMCLK_DIV]       = &meson8b_cts_amclk_div.hw,
3339                 [CLKID_CTS_AMCLK]           = &meson8b_cts_amclk.hw,
3340                 [CLKID_CTS_MCLK_I958_SEL]   = &meson8b_cts_mclk_i958_sel.hw,
3341                 [CLKID_CTS_MCLK_I958_DIV]   = &meson8b_cts_mclk_i958_div.hw,
3342                 [CLKID_CTS_MCLK_I958]       = &meson8b_cts_mclk_i958.hw,
3343                 [CLKID_CTS_I958]            = &meson8b_cts_i958.hw,
3344                 [CLK_NR_CLKS]               = NULL,
3345         },
3346         .num = CLK_NR_CLKS,
3347 };
3348
3349 static struct clk_regmap *const meson8b_clk_regmaps[] = {
3350         &meson8b_clk81,
3351         &meson8b_ddr,
3352         &meson8b_dos,
3353         &meson8b_isa,
3354         &meson8b_pl301,
3355         &meson8b_periphs,
3356         &meson8b_spicc,
3357         &meson8b_i2c,
3358         &meson8b_sar_adc,
3359         &meson8b_smart_card,
3360         &meson8b_rng0,
3361         &meson8b_uart0,
3362         &meson8b_sdhc,
3363         &meson8b_stream,
3364         &meson8b_async_fifo,
3365         &meson8b_sdio,
3366         &meson8b_abuf,
3367         &meson8b_hiu_iface,
3368         &meson8b_assist_misc,
3369         &meson8b_spi,
3370         &meson8b_i2s_spdif,
3371         &meson8b_eth,
3372         &meson8b_demux,
3373         &meson8b_aiu_glue,
3374         &meson8b_iec958,
3375         &meson8b_i2s_out,
3376         &meson8b_amclk,
3377         &meson8b_aififo2,
3378         &meson8b_mixer,
3379         &meson8b_mixer_iface,
3380         &meson8b_adc,
3381         &meson8b_blkmv,
3382         &meson8b_aiu,
3383         &meson8b_uart1,
3384         &meson8b_g2d,
3385         &meson8b_usb0,
3386         &meson8b_usb1,
3387         &meson8b_reset,
3388         &meson8b_nand,
3389         &meson8b_dos_parser,
3390         &meson8b_usb,
3391         &meson8b_vdin1,
3392         &meson8b_ahb_arb0,
3393         &meson8b_efuse,
3394         &meson8b_boot_rom,
3395         &meson8b_ahb_data_bus,
3396         &meson8b_ahb_ctrl_bus,
3397         &meson8b_hdmi_intr_sync,
3398         &meson8b_hdmi_pclk,
3399         &meson8b_usb1_ddr_bridge,
3400         &meson8b_usb0_ddr_bridge,
3401         &meson8b_mmc_pclk,
3402         &meson8b_dvin,
3403         &meson8b_uart2,
3404         &meson8b_sana,
3405         &meson8b_vpu_intr,
3406         &meson8b_sec_ahb_ahb3_bridge,
3407         &meson8b_clk81_a9,
3408         &meson8b_vclk2_venci0,
3409         &meson8b_vclk2_venci1,
3410         &meson8b_vclk2_vencp0,
3411         &meson8b_vclk2_vencp1,
3412         &meson8b_gclk_venci_int,
3413         &meson8b_gclk_vencp_int,
3414         &meson8b_dac_clk,
3415         &meson8b_aoclk_gate,
3416         &meson8b_iec958_gate,
3417         &meson8b_enc480p,
3418         &meson8b_rng1,
3419         &meson8b_gclk_vencl_int,
3420         &meson8b_vclk2_venclmcc,
3421         &meson8b_vclk2_vencl,
3422         &meson8b_vclk2_other,
3423         &meson8b_edp,
3424         &meson8b_ao_media_cpu,
3425         &meson8b_ao_ahb_sram,
3426         &meson8b_ao_ahb_bus,
3427         &meson8b_ao_iface,
3428         &meson8b_mpeg_clk_div,
3429         &meson8b_mpeg_clk_sel,
3430         &meson8b_mpll0,
3431         &meson8b_mpll1,
3432         &meson8b_mpll2,
3433         &meson8b_mpll0_div,
3434         &meson8b_mpll1_div,
3435         &meson8b_mpll2_div,
3436         &meson8b_fixed_pll,
3437         &meson8b_sys_pll,
3438         &meson8b_cpu_in_sel,
3439         &meson8b_cpu_scale_div,
3440         &meson8b_cpu_scale_out_sel,
3441         &meson8b_cpu_clk,
3442         &meson8b_mpll_prediv,
3443         &meson8b_fclk_div2,
3444         &meson8b_fclk_div3,
3445         &meson8b_fclk_div4,
3446         &meson8b_fclk_div5,
3447         &meson8b_fclk_div7,
3448         &meson8b_nand_clk_sel,
3449         &meson8b_nand_clk_div,
3450         &meson8b_nand_clk_gate,
3451         &meson8b_fixed_pll_dco,
3452         &meson8b_hdmi_pll_dco,
3453         &meson8b_sys_pll_dco,
3454         &meson8b_apb_clk_sel,
3455         &meson8b_apb_clk_gate,
3456         &meson8b_periph_clk_sel,
3457         &meson8b_periph_clk_gate,
3458         &meson8b_axi_clk_sel,
3459         &meson8b_axi_clk_gate,
3460         &meson8b_l2_dram_clk_sel,
3461         &meson8b_l2_dram_clk_gate,
3462         &meson8b_hdmi_pll_lvds_out,
3463         &meson8b_hdmi_pll_hdmi_out,
3464         &meson8b_vid_pll_in_sel,
3465         &meson8b_vid_pll_in_en,
3466         &meson8b_vid_pll_pre_div,
3467         &meson8b_vid_pll_post_div,
3468         &meson8b_vid_pll,
3469         &meson8b_vid_pll_final_div,
3470         &meson8b_vclk_in_sel,
3471         &meson8b_vclk_in_en,
3472         &meson8b_vclk_en,
3473         &meson8b_vclk_div1_gate,
3474         &meson8b_vclk_div2_div_gate,
3475         &meson8b_vclk_div4_div_gate,
3476         &meson8b_vclk_div6_div_gate,
3477         &meson8b_vclk_div12_div_gate,
3478         &meson8b_vclk2_in_sel,
3479         &meson8b_vclk2_clk_in_en,
3480         &meson8b_vclk2_clk_en,
3481         &meson8b_vclk2_div1_gate,
3482         &meson8b_vclk2_div2_div_gate,
3483         &meson8b_vclk2_div4_div_gate,
3484         &meson8b_vclk2_div6_div_gate,
3485         &meson8b_vclk2_div12_div_gate,
3486         &meson8b_cts_enct_sel,
3487         &meson8b_cts_enct,
3488         &meson8b_cts_encp_sel,
3489         &meson8b_cts_encp,
3490         &meson8b_cts_enci_sel,
3491         &meson8b_cts_enci,
3492         &meson8b_hdmi_tx_pixel_sel,
3493         &meson8b_hdmi_tx_pixel,
3494         &meson8b_cts_encl_sel,
3495         &meson8b_cts_encl,
3496         &meson8b_cts_vdac0_sel,
3497         &meson8b_cts_vdac0,
3498         &meson8b_hdmi_sys_sel,
3499         &meson8b_hdmi_sys_div,
3500         &meson8b_hdmi_sys,
3501         &meson8b_mali_0_sel,
3502         &meson8b_mali_0_div,
3503         &meson8b_mali_0,
3504         &meson8b_mali_1_sel,
3505         &meson8b_mali_1_div,
3506         &meson8b_mali_1,
3507         &meson8b_mali,
3508         &meson8m2_gp_pll_dco,
3509         &meson8m2_gp_pll,
3510         &meson8b_vpu_0_sel,
3511         &meson8m2_vpu_0_sel,
3512         &meson8b_vpu_0_div,
3513         &meson8b_vpu_0,
3514         &meson8b_vpu_1_sel,
3515         &meson8m2_vpu_1_sel,
3516         &meson8b_vpu_1_div,
3517         &meson8b_vpu_1,
3518         &meson8b_vpu,
3519         &meson8b_vdec_1_sel,
3520         &meson8b_vdec_1_1_div,
3521         &meson8b_vdec_1_1,
3522         &meson8b_vdec_1_2_div,
3523         &meson8b_vdec_1_2,
3524         &meson8b_vdec_1,
3525         &meson8b_vdec_hcodec_sel,
3526         &meson8b_vdec_hcodec_div,
3527         &meson8b_vdec_hcodec,
3528         &meson8b_vdec_2_sel,
3529         &meson8b_vdec_2_div,
3530         &meson8b_vdec_2,
3531         &meson8b_vdec_hevc_sel,
3532         &meson8b_vdec_hevc_div,
3533         &meson8b_vdec_hevc_en,
3534         &meson8b_vdec_hevc,
3535         &meson8b_cts_amclk,
3536         &meson8b_cts_amclk_sel,
3537         &meson8b_cts_amclk_div,
3538         &meson8b_cts_mclk_i958_sel,
3539         &meson8b_cts_mclk_i958_div,
3540         &meson8b_cts_mclk_i958,
3541         &meson8b_cts_i958,
3542 };
3543
3544 static const struct meson8b_clk_reset_line {
3545         u32 reg;
3546         u8 bit_idx;
3547         bool active_low;
3548 } meson8b_clk_reset_bits[] = {
3549         [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
3550                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3551                 .bit_idx = 30,
3552                 .active_low = false,
3553         },
3554         [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
3555                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3556                 .bit_idx = 29,
3557                 .active_low = false,
3558         },
3559         [CLKC_RESET_SCU_SOFT_RESET] = {
3560                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3561                 .bit_idx = 28,
3562                 .active_low = false,
3563         },
3564         [CLKC_RESET_CPU3_SOFT_RESET] = {
3565                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3566                 .bit_idx = 27,
3567                 .active_low = false,
3568         },
3569         [CLKC_RESET_CPU2_SOFT_RESET] = {
3570                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3571                 .bit_idx = 26,
3572                 .active_low = false,
3573         },
3574         [CLKC_RESET_CPU1_SOFT_RESET] = {
3575                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3576                 .bit_idx = 25,
3577                 .active_low = false,
3578         },
3579         [CLKC_RESET_CPU0_SOFT_RESET] = {
3580                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3581                 .bit_idx = 24,
3582                 .active_low = false,
3583         },
3584         [CLKC_RESET_A5_GLOBAL_RESET] = {
3585                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3586                 .bit_idx = 18,
3587                 .active_low = false,
3588         },
3589         [CLKC_RESET_A5_AXI_SOFT_RESET] = {
3590                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3591                 .bit_idx = 17,
3592                 .active_low = false,
3593         },
3594         [CLKC_RESET_A5_ABP_SOFT_RESET] = {
3595                 .reg = HHI_SYS_CPU_CLK_CNTL0,
3596                 .bit_idx = 16,
3597                 .active_low = false,
3598         },
3599         [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
3600                 .reg = HHI_SYS_CPU_CLK_CNTL1,
3601                 .bit_idx = 30,
3602                 .active_low = false,
3603         },
3604         [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
3605                 .reg = HHI_VID_CLK_CNTL,
3606                 .bit_idx = 15,
3607                 .active_low = false,
3608         },
3609         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
3610                 .reg = HHI_VID_DIVIDER_CNTL,
3611                 .bit_idx = 7,
3612                 .active_low = false,
3613         },
3614         [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
3615                 .reg = HHI_VID_DIVIDER_CNTL,
3616                 .bit_idx = 3,
3617                 .active_low = false,
3618         },
3619         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
3620                 .reg = HHI_VID_DIVIDER_CNTL,
3621                 .bit_idx = 1,
3622                 .active_low = true,
3623         },
3624         [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
3625                 .reg = HHI_VID_DIVIDER_CNTL,
3626                 .bit_idx = 0,
3627                 .active_low = true,
3628         },
3629 };
3630
3631 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
3632                                     unsigned long id, bool assert)
3633 {
3634         struct meson8b_clk_reset *meson8b_clk_reset =
3635                 container_of(rcdev, struct meson8b_clk_reset, reset);
3636         const struct meson8b_clk_reset_line *reset;
3637         unsigned int value = 0;
3638         unsigned long flags;
3639
3640         if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
3641                 return -EINVAL;
3642
3643         reset = &meson8b_clk_reset_bits[id];
3644
3645         if (assert != reset->active_low)
3646                 value = BIT(reset->bit_idx);
3647
3648         spin_lock_irqsave(&meson_clk_lock, flags);
3649
3650         regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
3651                            BIT(reset->bit_idx), value);
3652
3653         spin_unlock_irqrestore(&meson_clk_lock, flags);
3654
3655         return 0;
3656 }
3657
3658 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
3659                                      unsigned long id)
3660 {
3661         return meson8b_clk_reset_update(rcdev, id, true);
3662 }
3663
3664 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
3665                                        unsigned long id)
3666 {
3667         return meson8b_clk_reset_update(rcdev, id, false);
3668 }
3669
3670 static const struct reset_control_ops meson8b_clk_reset_ops = {
3671         .assert = meson8b_clk_reset_assert,
3672         .deassert = meson8b_clk_reset_deassert,
3673 };
3674
3675 struct meson8b_nb_data {
3676         struct notifier_block nb;
3677         struct clk_hw *cpu_clk;
3678 };
3679
3680 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
3681                                        unsigned long event, void *data)
3682 {
3683         struct meson8b_nb_data *nb_data =
3684                 container_of(nb, struct meson8b_nb_data, nb);
3685         struct clk_hw *parent_clk;
3686         int ret;
3687
3688         switch (event) {
3689         case PRE_RATE_CHANGE:
3690                 /* xtal */
3691                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 0);
3692                 break;
3693
3694         case POST_RATE_CHANGE:
3695                 /* cpu_scale_out_sel */
3696                 parent_clk = clk_hw_get_parent_by_index(nb_data->cpu_clk, 1);
3697                 break;
3698
3699         default:
3700                 return NOTIFY_DONE;
3701         }
3702
3703         ret = clk_hw_set_parent(nb_data->cpu_clk, parent_clk);
3704         if (ret)
3705                 return notifier_from_errno(ret);
3706
3707         udelay(100);
3708
3709         return NOTIFY_OK;
3710 }
3711
3712 static struct meson8b_nb_data meson8b_cpu_nb_data = {
3713         .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
3714 };
3715
3716 static void __init meson8b_clkc_init_common(struct device_node *np,
3717                         struct clk_hw_onecell_data *clk_hw_onecell_data)
3718 {
3719         struct meson8b_clk_reset *rstc;
3720         const char *notifier_clk_name;
3721         struct clk *notifier_clk;
3722         struct regmap *map;
3723         int i, ret;
3724
3725         map = syscon_node_to_regmap(of_get_parent(np));
3726         if (IS_ERR(map)) {
3727                 pr_err("failed to get HHI regmap - Trying obsolete regs\n");
3728                 return;
3729         }
3730
3731         rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
3732         if (!rstc)
3733                 return;
3734
3735         /* Reset Controller */
3736         rstc->regmap = map;
3737         rstc->reset.ops = &meson8b_clk_reset_ops;
3738         rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
3739         rstc->reset.of_node = np;
3740         ret = reset_controller_register(&rstc->reset);
3741         if (ret) {
3742                 pr_err("%s: Failed to register clkc reset controller: %d\n",
3743                        __func__, ret);
3744                 return;
3745         }
3746
3747         /* Populate regmap for the regmap backed clocks */
3748         for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
3749                 meson8b_clk_regmaps[i]->map = map;
3750
3751         /*
3752          * register all clks and start with the first used ID (which is
3753          * CLKID_PLL_FIXED)
3754          */
3755         for (i = CLKID_PLL_FIXED; i < CLK_NR_CLKS; i++) {
3756                 /* array might be sparse */
3757                 if (!clk_hw_onecell_data->hws[i])
3758                         continue;
3759
3760                 ret = of_clk_hw_register(np, clk_hw_onecell_data->hws[i]);
3761                 if (ret)
3762                         return;
3763         }
3764
3765         meson8b_cpu_nb_data.cpu_clk = clk_hw_onecell_data->hws[CLKID_CPUCLK];
3766
3767         /*
3768          * FIXME we shouldn't program the muxes in notifier handlers. The
3769          * tricky programming sequence will be handled by the forthcoming
3770          * coordinated clock rates mechanism once that feature is released.
3771          */
3772         notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
3773         notifier_clk = __clk_lookup(notifier_clk_name);
3774         ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
3775         if (ret) {
3776                 pr_err("%s: failed to register the CPU clock notifier\n",
3777                        __func__);
3778                 return;
3779         }
3780
3781         ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
3782                                      clk_hw_onecell_data);
3783         if (ret)
3784                 pr_err("%s: failed to register clock provider\n", __func__);
3785 }
3786
3787 static void __init meson8_clkc_init(struct device_node *np)
3788 {
3789         return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
3790 }
3791
3792 static void __init meson8b_clkc_init(struct device_node *np)
3793 {
3794         return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
3795 }
3796
3797 static void __init meson8m2_clkc_init(struct device_node *np)
3798 {
3799         return meson8b_clkc_init_common(np, &meson8m2_hw_onecell_data);
3800 }
3801
3802 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
3803                       meson8_clkc_init);
3804 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
3805                       meson8b_clkc_init);
3806 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",
3807                       meson8m2_clkc_init);