1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
6 * Copyright (c) 2016 BayLibre, Inc.
7 * Michael Turquette <mturquette@baylibre.com>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/init.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/of_address.h>
15 #include <linux/reset-controller.h>
16 #include <linux/slab.h>
17 #include <linux/regmap.h>
20 #include "clk-regmap.h"
24 static DEFINE_SPINLOCK(meson_clk_lock);
26 struct meson8b_clk_reset {
27 struct reset_controller_dev reset;
28 struct regmap *regmap;
31 static const struct pll_params_table sys_pll_params_table[] = {
55 static struct clk_fixed_rate meson8b_xtal = {
56 .fixed_rate = 24000000,
57 .hw.init = &(struct clk_init_data){
60 .ops = &clk_fixed_rate_ops,
64 static struct clk_regmap meson8b_fixed_pll_dco = {
65 .data = &(struct meson_clk_pll_data){
67 .reg_off = HHI_MPLL_CNTL,
72 .reg_off = HHI_MPLL_CNTL,
77 .reg_off = HHI_MPLL_CNTL,
82 .reg_off = HHI_MPLL_CNTL2,
87 .reg_off = HHI_MPLL_CNTL,
92 .reg_off = HHI_MPLL_CNTL,
97 .hw.init = &(struct clk_init_data){
98 .name = "fixed_pll_dco",
99 .ops = &meson_clk_pll_ro_ops,
100 .parent_names = (const char *[]){ "xtal" },
105 static struct clk_regmap meson8b_fixed_pll = {
106 .data = &(struct clk_regmap_div_data){
107 .offset = HHI_MPLL_CNTL,
110 .flags = CLK_DIVIDER_POWER_OF_TWO,
112 .hw.init = &(struct clk_init_data){
114 .ops = &clk_regmap_divider_ro_ops,
115 .parent_names = (const char *[]){ "fixed_pll_dco" },
118 * This clock won't ever change at runtime so
119 * CLK_SET_RATE_PARENT is not required
124 static struct clk_regmap meson8b_hdmi_pll_dco = {
125 .data = &(struct meson_clk_pll_data){
127 .reg_off = HHI_VID_PLL_CNTL,
132 .reg_off = HHI_VID_PLL_CNTL,
137 .reg_off = HHI_VID_PLL_CNTL,
142 .reg_off = HHI_VID_PLL_CNTL2,
147 .reg_off = HHI_VID_PLL_CNTL,
152 .reg_off = HHI_VID_PLL_CNTL,
157 .hw.init = &(struct clk_init_data){
158 /* sometimes also called "HPLL" or "HPLL PLL" */
159 .name = "hdmi_pll_dco",
160 .ops = &meson_clk_pll_ro_ops,
161 .parent_names = (const char *[]){ "xtal" },
166 static struct clk_regmap meson8b_hdmi_pll_lvds_out = {
167 .data = &(struct clk_regmap_div_data){
168 .offset = HHI_VID_PLL_CNTL,
171 .flags = CLK_DIVIDER_POWER_OF_TWO,
173 .hw.init = &(struct clk_init_data){
174 .name = "hdmi_pll_lvds_out",
175 .ops = &clk_regmap_divider_ro_ops,
176 .parent_names = (const char *[]){ "hdmi_pll_dco" },
178 .flags = CLK_SET_RATE_PARENT,
182 static struct clk_regmap meson8b_hdmi_pll_hdmi_out = {
183 .data = &(struct clk_regmap_div_data){
184 .offset = HHI_VID_PLL_CNTL,
187 .flags = CLK_DIVIDER_POWER_OF_TWO,
189 .hw.init = &(struct clk_init_data){
190 .name = "hdmi_pll_hdmi_out",
191 .ops = &clk_regmap_divider_ro_ops,
192 .parent_names = (const char *[]){ "hdmi_pll_dco" },
194 .flags = CLK_SET_RATE_PARENT,
198 static struct clk_regmap meson8b_sys_pll_dco = {
199 .data = &(struct meson_clk_pll_data){
201 .reg_off = HHI_SYS_PLL_CNTL,
206 .reg_off = HHI_SYS_PLL_CNTL,
211 .reg_off = HHI_SYS_PLL_CNTL,
216 .reg_off = HHI_SYS_PLL_CNTL,
221 .reg_off = HHI_SYS_PLL_CNTL,
225 .table = sys_pll_params_table,
227 .hw.init = &(struct clk_init_data){
228 .name = "sys_pll_dco",
229 .ops = &meson_clk_pll_ops,
230 .parent_names = (const char *[]){ "xtal" },
235 static struct clk_regmap meson8b_sys_pll = {
236 .data = &(struct clk_regmap_div_data){
237 .offset = HHI_SYS_PLL_CNTL,
240 .flags = CLK_DIVIDER_POWER_OF_TWO,
242 .hw.init = &(struct clk_init_data){
244 .ops = &clk_regmap_divider_ops,
245 .parent_names = (const char *[]){ "sys_pll_dco" },
247 .flags = CLK_SET_RATE_PARENT,
251 static struct clk_fixed_factor meson8b_fclk_div2_div = {
254 .hw.init = &(struct clk_init_data){
255 .name = "fclk_div2_div",
256 .ops = &clk_fixed_factor_ops,
257 .parent_names = (const char *[]){ "fixed_pll" },
262 static struct clk_regmap meson8b_fclk_div2 = {
263 .data = &(struct clk_regmap_gate_data){
264 .offset = HHI_MPLL_CNTL6,
267 .hw.init = &(struct clk_init_data){
269 .ops = &clk_regmap_gate_ops,
270 .parent_names = (const char *[]){ "fclk_div2_div" },
273 * FIXME: Ethernet with a RGMII PHYs is not working if
274 * fclk_div2 is disabled. it is currently unclear why this
275 * is. keep it enabled until the Ethernet driver knows how
276 * to manage this clock.
278 .flags = CLK_IS_CRITICAL,
282 static struct clk_fixed_factor meson8b_fclk_div3_div = {
285 .hw.init = &(struct clk_init_data){
286 .name = "fclk_div3_div",
287 .ops = &clk_fixed_factor_ops,
288 .parent_names = (const char *[]){ "fixed_pll" },
293 static struct clk_regmap meson8b_fclk_div3 = {
294 .data = &(struct clk_regmap_gate_data){
295 .offset = HHI_MPLL_CNTL6,
298 .hw.init = &(struct clk_init_data){
300 .ops = &clk_regmap_gate_ops,
301 .parent_names = (const char *[]){ "fclk_div3_div" },
306 static struct clk_fixed_factor meson8b_fclk_div4_div = {
309 .hw.init = &(struct clk_init_data){
310 .name = "fclk_div4_div",
311 .ops = &clk_fixed_factor_ops,
312 .parent_names = (const char *[]){ "fixed_pll" },
317 static struct clk_regmap meson8b_fclk_div4 = {
318 .data = &(struct clk_regmap_gate_data){
319 .offset = HHI_MPLL_CNTL6,
322 .hw.init = &(struct clk_init_data){
324 .ops = &clk_regmap_gate_ops,
325 .parent_names = (const char *[]){ "fclk_div4_div" },
330 static struct clk_fixed_factor meson8b_fclk_div5_div = {
333 .hw.init = &(struct clk_init_data){
334 .name = "fclk_div5_div",
335 .ops = &clk_fixed_factor_ops,
336 .parent_names = (const char *[]){ "fixed_pll" },
341 static struct clk_regmap meson8b_fclk_div5 = {
342 .data = &(struct clk_regmap_gate_data){
343 .offset = HHI_MPLL_CNTL6,
346 .hw.init = &(struct clk_init_data){
348 .ops = &clk_regmap_gate_ops,
349 .parent_names = (const char *[]){ "fclk_div5_div" },
354 static struct clk_fixed_factor meson8b_fclk_div7_div = {
357 .hw.init = &(struct clk_init_data){
358 .name = "fclk_div7_div",
359 .ops = &clk_fixed_factor_ops,
360 .parent_names = (const char *[]){ "fixed_pll" },
365 static struct clk_regmap meson8b_fclk_div7 = {
366 .data = &(struct clk_regmap_gate_data){
367 .offset = HHI_MPLL_CNTL6,
370 .hw.init = &(struct clk_init_data){
372 .ops = &clk_regmap_gate_ops,
373 .parent_names = (const char *[]){ "fclk_div7_div" },
378 static struct clk_regmap meson8b_mpll_prediv = {
379 .data = &(struct clk_regmap_div_data){
380 .offset = HHI_MPLL_CNTL5,
384 .hw.init = &(struct clk_init_data){
385 .name = "mpll_prediv",
386 .ops = &clk_regmap_divider_ro_ops,
387 .parent_names = (const char *[]){ "fixed_pll" },
392 static struct clk_regmap meson8b_mpll0_div = {
393 .data = &(struct meson_clk_mpll_data){
395 .reg_off = HHI_MPLL_CNTL7,
400 .reg_off = HHI_MPLL_CNTL7,
405 .reg_off = HHI_MPLL_CNTL7,
410 .reg_off = HHI_MPLL_CNTL,
414 .lock = &meson_clk_lock,
416 .hw.init = &(struct clk_init_data){
418 .ops = &meson_clk_mpll_ops,
419 .parent_names = (const char *[]){ "mpll_prediv" },
424 static struct clk_regmap meson8b_mpll0 = {
425 .data = &(struct clk_regmap_gate_data){
426 .offset = HHI_MPLL_CNTL7,
429 .hw.init = &(struct clk_init_data){
431 .ops = &clk_regmap_gate_ops,
432 .parent_names = (const char *[]){ "mpll0_div" },
434 .flags = CLK_SET_RATE_PARENT,
438 static struct clk_regmap meson8b_mpll1_div = {
439 .data = &(struct meson_clk_mpll_data){
441 .reg_off = HHI_MPLL_CNTL8,
446 .reg_off = HHI_MPLL_CNTL8,
451 .reg_off = HHI_MPLL_CNTL8,
455 .lock = &meson_clk_lock,
457 .hw.init = &(struct clk_init_data){
459 .ops = &meson_clk_mpll_ops,
460 .parent_names = (const char *[]){ "mpll_prediv" },
465 static struct clk_regmap meson8b_mpll1 = {
466 .data = &(struct clk_regmap_gate_data){
467 .offset = HHI_MPLL_CNTL8,
470 .hw.init = &(struct clk_init_data){
472 .ops = &clk_regmap_gate_ops,
473 .parent_names = (const char *[]){ "mpll1_div" },
475 .flags = CLK_SET_RATE_PARENT,
479 static struct clk_regmap meson8b_mpll2_div = {
480 .data = &(struct meson_clk_mpll_data){
482 .reg_off = HHI_MPLL_CNTL9,
487 .reg_off = HHI_MPLL_CNTL9,
492 .reg_off = HHI_MPLL_CNTL9,
496 .lock = &meson_clk_lock,
498 .hw.init = &(struct clk_init_data){
500 .ops = &meson_clk_mpll_ops,
501 .parent_names = (const char *[]){ "mpll_prediv" },
506 static struct clk_regmap meson8b_mpll2 = {
507 .data = &(struct clk_regmap_gate_data){
508 .offset = HHI_MPLL_CNTL9,
511 .hw.init = &(struct clk_init_data){
513 .ops = &clk_regmap_gate_ops,
514 .parent_names = (const char *[]){ "mpll2_div" },
516 .flags = CLK_SET_RATE_PARENT,
520 static u32 mux_table_clk81[] = { 6, 5, 7 };
521 static struct clk_regmap meson8b_mpeg_clk_sel = {
522 .data = &(struct clk_regmap_mux_data){
523 .offset = HHI_MPEG_CLK_CNTL,
526 .table = mux_table_clk81,
528 .hw.init = &(struct clk_init_data){
529 .name = "mpeg_clk_sel",
530 .ops = &clk_regmap_mux_ro_ops,
532 * FIXME bits 14:12 selects from 8 possible parents:
533 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
534 * fclk_div4, fclk_div3, fclk_div5
536 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
542 static struct clk_regmap meson8b_mpeg_clk_div = {
543 .data = &(struct clk_regmap_div_data){
544 .offset = HHI_MPEG_CLK_CNTL,
548 .hw.init = &(struct clk_init_data){
549 .name = "mpeg_clk_div",
550 .ops = &clk_regmap_divider_ro_ops,
551 .parent_names = (const char *[]){ "mpeg_clk_sel" },
556 static struct clk_regmap meson8b_clk81 = {
557 .data = &(struct clk_regmap_gate_data){
558 .offset = HHI_MPEG_CLK_CNTL,
561 .hw.init = &(struct clk_init_data){
563 .ops = &clk_regmap_gate_ops,
564 .parent_names = (const char *[]){ "mpeg_clk_div" },
566 .flags = CLK_IS_CRITICAL,
570 static struct clk_regmap meson8b_cpu_in_sel = {
571 .data = &(struct clk_regmap_mux_data){
572 .offset = HHI_SYS_CPU_CLK_CNTL0,
576 .hw.init = &(struct clk_init_data){
577 .name = "cpu_in_sel",
578 .ops = &clk_regmap_mux_ops,
579 .parent_names = (const char *[]){ "xtal", "sys_pll" },
581 .flags = (CLK_SET_RATE_PARENT |
582 CLK_SET_RATE_NO_REPARENT),
586 static struct clk_fixed_factor meson8b_cpu_in_div2 = {
589 .hw.init = &(struct clk_init_data){
590 .name = "cpu_in_div2",
591 .ops = &clk_fixed_factor_ops,
592 .parent_names = (const char *[]){ "cpu_in_sel" },
594 .flags = CLK_SET_RATE_PARENT,
598 static struct clk_fixed_factor meson8b_cpu_in_div3 = {
601 .hw.init = &(struct clk_init_data){
602 .name = "cpu_in_div3",
603 .ops = &clk_fixed_factor_ops,
604 .parent_names = (const char *[]){ "cpu_in_sel" },
606 .flags = CLK_SET_RATE_PARENT,
610 static const struct clk_div_table cpu_scale_table[] = {
611 { .val = 1, .div = 4 },
612 { .val = 2, .div = 6 },
613 { .val = 3, .div = 8 },
614 { .val = 4, .div = 10 },
615 { .val = 5, .div = 12 },
616 { .val = 6, .div = 14 },
617 { .val = 7, .div = 16 },
618 { .val = 8, .div = 18 },
622 static struct clk_regmap meson8b_cpu_scale_div = {
623 .data = &(struct clk_regmap_div_data){
624 .offset = HHI_SYS_CPU_CLK_CNTL1,
627 .table = cpu_scale_table,
628 .flags = CLK_DIVIDER_ALLOW_ZERO,
630 .hw.init = &(struct clk_init_data){
631 .name = "cpu_scale_div",
632 .ops = &clk_regmap_divider_ops,
633 .parent_names = (const char *[]){ "cpu_in_sel" },
635 .flags = CLK_SET_RATE_PARENT,
639 static u32 mux_table_cpu_scale_out_sel[] = { 0, 1, 3 };
640 static struct clk_regmap meson8b_cpu_scale_out_sel = {
641 .data = &(struct clk_regmap_mux_data){
642 .offset = HHI_SYS_CPU_CLK_CNTL0,
645 .table = mux_table_cpu_scale_out_sel,
647 .hw.init = &(struct clk_init_data){
648 .name = "cpu_scale_out_sel",
649 .ops = &clk_regmap_mux_ops,
651 * NOTE: We are skipping the parent with value 0x2 (which is
652 * "cpu_in_div3") because it results in a duty cycle of 33%
653 * which makes the system unstable and can result in a lockup
654 * of the whole system.
656 .parent_names = (const char *[]) { "cpu_in_sel",
660 .flags = CLK_SET_RATE_PARENT,
664 static struct clk_regmap meson8b_cpu_clk = {
665 .data = &(struct clk_regmap_mux_data){
666 .offset = HHI_SYS_CPU_CLK_CNTL0,
670 .hw.init = &(struct clk_init_data){
672 .ops = &clk_regmap_mux_ops,
673 .parent_names = (const char *[]){ "xtal",
674 "cpu_scale_out_sel" },
676 .flags = (CLK_SET_RATE_PARENT |
677 CLK_SET_RATE_NO_REPARENT |
682 static struct clk_regmap meson8b_nand_clk_sel = {
683 .data = &(struct clk_regmap_mux_data){
684 .offset = HHI_NAND_CLK_CNTL,
687 .flags = CLK_MUX_ROUND_CLOSEST,
689 .hw.init = &(struct clk_init_data){
690 .name = "nand_clk_sel",
691 .ops = &clk_regmap_mux_ops,
692 /* FIXME all other parents are unknown: */
693 .parent_names = (const char *[]){ "fclk_div4", "fclk_div3",
694 "fclk_div5", "fclk_div7", "xtal" },
696 .flags = CLK_SET_RATE_PARENT,
700 static struct clk_regmap meson8b_nand_clk_div = {
701 .data = &(struct clk_regmap_div_data){
702 .offset = HHI_NAND_CLK_CNTL,
705 .flags = CLK_DIVIDER_ROUND_CLOSEST,
707 .hw.init = &(struct clk_init_data){
708 .name = "nand_clk_div",
709 .ops = &clk_regmap_divider_ops,
710 .parent_names = (const char *[]){ "nand_clk_sel" },
712 .flags = CLK_SET_RATE_PARENT,
716 static struct clk_regmap meson8b_nand_clk_gate = {
717 .data = &(struct clk_regmap_gate_data){
718 .offset = HHI_NAND_CLK_CNTL,
721 .hw.init = &(struct clk_init_data){
722 .name = "nand_clk_gate",
723 .ops = &clk_regmap_gate_ops,
724 .parent_names = (const char *[]){ "nand_clk_div" },
726 .flags = CLK_SET_RATE_PARENT,
730 static struct clk_fixed_factor meson8b_cpu_clk_div2 = {
733 .hw.init = &(struct clk_init_data){
734 .name = "cpu_clk_div2",
735 .ops = &clk_fixed_factor_ops,
736 .parent_names = (const char *[]){ "cpu_clk" },
741 static struct clk_fixed_factor meson8b_cpu_clk_div3 = {
744 .hw.init = &(struct clk_init_data){
745 .name = "cpu_clk_div3",
746 .ops = &clk_fixed_factor_ops,
747 .parent_names = (const char *[]){ "cpu_clk" },
752 static struct clk_fixed_factor meson8b_cpu_clk_div4 = {
755 .hw.init = &(struct clk_init_data){
756 .name = "cpu_clk_div4",
757 .ops = &clk_fixed_factor_ops,
758 .parent_names = (const char *[]){ "cpu_clk" },
763 static struct clk_fixed_factor meson8b_cpu_clk_div5 = {
766 .hw.init = &(struct clk_init_data){
767 .name = "cpu_clk_div5",
768 .ops = &clk_fixed_factor_ops,
769 .parent_names = (const char *[]){ "cpu_clk" },
774 static struct clk_fixed_factor meson8b_cpu_clk_div6 = {
777 .hw.init = &(struct clk_init_data){
778 .name = "cpu_clk_div6",
779 .ops = &clk_fixed_factor_ops,
780 .parent_names = (const char *[]){ "cpu_clk" },
785 static struct clk_fixed_factor meson8b_cpu_clk_div7 = {
788 .hw.init = &(struct clk_init_data){
789 .name = "cpu_clk_div7",
790 .ops = &clk_fixed_factor_ops,
791 .parent_names = (const char *[]){ "cpu_clk" },
796 static struct clk_fixed_factor meson8b_cpu_clk_div8 = {
799 .hw.init = &(struct clk_init_data){
800 .name = "cpu_clk_div8",
801 .ops = &clk_fixed_factor_ops,
802 .parent_names = (const char *[]){ "cpu_clk" },
807 static u32 mux_table_apb[] = { 1, 2, 3, 4, 5, 6, 7 };
808 static struct clk_regmap meson8b_apb_clk_sel = {
809 .data = &(struct clk_regmap_mux_data){
810 .offset = HHI_SYS_CPU_CLK_CNTL1,
813 .table = mux_table_apb,
815 .hw.init = &(struct clk_init_data){
816 .name = "apb_clk_sel",
817 .ops = &clk_regmap_mux_ops,
818 .parent_names = (const char *[]){ "cpu_clk_div2",
829 static struct clk_regmap meson8b_apb_clk_gate = {
830 .data = &(struct clk_regmap_gate_data){
831 .offset = HHI_SYS_CPU_CLK_CNTL1,
833 .flags = CLK_GATE_SET_TO_DISABLE,
835 .hw.init = &(struct clk_init_data){
836 .name = "apb_clk_dis",
837 .ops = &clk_regmap_gate_ro_ops,
838 .parent_names = (const char *[]){ "apb_clk_sel" },
840 .flags = CLK_SET_RATE_PARENT,
844 static struct clk_regmap meson8b_periph_clk_sel = {
845 .data = &(struct clk_regmap_mux_data){
846 .offset = HHI_SYS_CPU_CLK_CNTL1,
850 .hw.init = &(struct clk_init_data){
851 .name = "periph_clk_sel",
852 .ops = &clk_regmap_mux_ops,
853 .parent_names = (const char *[]){ "cpu_clk_div2",
864 static struct clk_regmap meson8b_periph_clk_gate = {
865 .data = &(struct clk_regmap_gate_data){
866 .offset = HHI_SYS_CPU_CLK_CNTL1,
868 .flags = CLK_GATE_SET_TO_DISABLE,
870 .hw.init = &(struct clk_init_data){
871 .name = "periph_clk_dis",
872 .ops = &clk_regmap_gate_ro_ops,
873 .parent_names = (const char *[]){ "periph_clk_sel" },
875 .flags = CLK_SET_RATE_PARENT,
879 static u32 mux_table_axi[] = { 1, 2, 3, 4, 5, 6, 7 };
880 static struct clk_regmap meson8b_axi_clk_sel = {
881 .data = &(struct clk_regmap_mux_data){
882 .offset = HHI_SYS_CPU_CLK_CNTL1,
885 .table = mux_table_axi,
887 .hw.init = &(struct clk_init_data){
888 .name = "axi_clk_sel",
889 .ops = &clk_regmap_mux_ops,
890 .parent_names = (const char *[]){ "cpu_clk_div2",
901 static struct clk_regmap meson8b_axi_clk_gate = {
902 .data = &(struct clk_regmap_gate_data){
903 .offset = HHI_SYS_CPU_CLK_CNTL1,
905 .flags = CLK_GATE_SET_TO_DISABLE,
907 .hw.init = &(struct clk_init_data){
908 .name = "axi_clk_dis",
909 .ops = &clk_regmap_gate_ro_ops,
910 .parent_names = (const char *[]){ "axi_clk_sel" },
912 .flags = CLK_SET_RATE_PARENT,
916 static struct clk_regmap meson8b_l2_dram_clk_sel = {
917 .data = &(struct clk_regmap_mux_data){
918 .offset = HHI_SYS_CPU_CLK_CNTL1,
922 .hw.init = &(struct clk_init_data){
923 .name = "l2_dram_clk_sel",
924 .ops = &clk_regmap_mux_ops,
925 .parent_names = (const char *[]){ "cpu_clk_div2",
936 static struct clk_regmap meson8b_l2_dram_clk_gate = {
937 .data = &(struct clk_regmap_gate_data){
938 .offset = HHI_SYS_CPU_CLK_CNTL1,
940 .flags = CLK_GATE_SET_TO_DISABLE,
942 .hw.init = &(struct clk_init_data){
943 .name = "l2_dram_clk_dis",
944 .ops = &clk_regmap_gate_ro_ops,
945 .parent_names = (const char *[]){ "l2_dram_clk_sel" },
947 .flags = CLK_SET_RATE_PARENT,
951 static struct clk_regmap meson8b_vid_pll_in_sel = {
952 .data = &(struct clk_regmap_mux_data){
953 .offset = HHI_VID_DIVIDER_CNTL,
957 .hw.init = &(struct clk_init_data){
958 .name = "vid_pll_in_sel",
959 .ops = &clk_regmap_mux_ro_ops,
961 * TODO: depending on the SoC there is also a second parent:
963 * Meson8b: hdmi_pll_dco
966 .parent_names = (const char *[]){ "hdmi_pll_dco" },
968 .flags = CLK_SET_RATE_PARENT,
972 static struct clk_regmap meson8b_vid_pll_in_en = {
973 .data = &(struct clk_regmap_gate_data){
974 .offset = HHI_VID_DIVIDER_CNTL,
977 .hw.init = &(struct clk_init_data){
978 .name = "vid_pll_in_en",
979 .ops = &clk_regmap_gate_ro_ops,
980 .parent_names = (const char *[]){ "vid_pll_in_sel" },
982 .flags = CLK_SET_RATE_PARENT,
986 static struct clk_regmap meson8b_vid_pll_pre_div = {
987 .data = &(struct clk_regmap_div_data){
988 .offset = HHI_VID_DIVIDER_CNTL,
992 .hw.init = &(struct clk_init_data){
993 .name = "vid_pll_pre_div",
994 .ops = &clk_regmap_divider_ro_ops,
995 .parent_names = (const char *[]){ "vid_pll_in_en" },
997 .flags = CLK_SET_RATE_PARENT,
1001 static struct clk_regmap meson8b_vid_pll_post_div = {
1002 .data = &(struct clk_regmap_div_data){
1003 .offset = HHI_VID_DIVIDER_CNTL,
1007 .hw.init = &(struct clk_init_data){
1008 .name = "vid_pll_post_div",
1009 .ops = &clk_regmap_divider_ro_ops,
1010 .parent_names = (const char *[]){ "vid_pll_pre_div" },
1012 .flags = CLK_SET_RATE_PARENT,
1016 static struct clk_regmap meson8b_vid_pll = {
1017 .data = &(struct clk_regmap_mux_data){
1018 .offset = HHI_VID_DIVIDER_CNTL,
1022 .hw.init = &(struct clk_init_data){
1024 .ops = &clk_regmap_mux_ro_ops,
1025 /* TODO: parent 0x2 is vid_pll_pre_div_mult7_div2 */
1026 .parent_names = (const char *[]){ "vid_pll_pre_div",
1027 "vid_pll_post_div" },
1029 .flags = CLK_SET_RATE_PARENT,
1033 static struct clk_regmap meson8b_vid_pll_final_div = {
1034 .data = &(struct clk_regmap_div_data){
1035 .offset = HHI_VID_CLK_DIV,
1039 .hw.init = &(struct clk_init_data){
1040 .name = "vid_pll_final_div",
1041 .ops = &clk_regmap_divider_ro_ops,
1042 .parent_names = (const char *[]){ "vid_pll" },
1044 .flags = CLK_SET_RATE_PARENT,
1048 static const char * const meson8b_vclk_mux_parents[] = {
1049 "vid_pll_final_div", "fclk_div4", "fclk_div3", "fclk_div5",
1050 "vid_pll_final_div", "fclk_div7", "mpll1"
1053 static struct clk_regmap meson8b_vclk_in_sel = {
1054 .data = &(struct clk_regmap_mux_data){
1055 .offset = HHI_VID_CLK_CNTL,
1059 .hw.init = &(struct clk_init_data){
1060 .name = "vclk_in_sel",
1061 .ops = &clk_regmap_mux_ro_ops,
1062 .parent_names = meson8b_vclk_mux_parents,
1063 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
1064 .flags = CLK_SET_RATE_PARENT,
1068 static struct clk_regmap meson8b_vclk_in_en = {
1069 .data = &(struct clk_regmap_gate_data){
1070 .offset = HHI_VID_CLK_DIV,
1073 .hw.init = &(struct clk_init_data){
1074 .name = "vclk_in_en",
1075 .ops = &clk_regmap_gate_ro_ops,
1076 .parent_names = (const char *[]){ "vclk_in_sel" },
1078 .flags = CLK_SET_RATE_PARENT,
1082 static struct clk_regmap meson8b_vclk_div1_gate = {
1083 .data = &(struct clk_regmap_gate_data){
1084 .offset = HHI_VID_CLK_DIV,
1087 .hw.init = &(struct clk_init_data){
1088 .name = "vclk_div1_en",
1089 .ops = &clk_regmap_gate_ro_ops,
1090 .parent_names = (const char *[]){ "vclk_in_en" },
1092 .flags = CLK_SET_RATE_PARENT,
1096 static struct clk_fixed_factor meson8b_vclk_div2_div = {
1099 .hw.init = &(struct clk_init_data){
1100 .name = "vclk_div2",
1101 .ops = &clk_fixed_factor_ops,
1102 .parent_names = (const char *[]){ "vclk_in_en" },
1104 .flags = CLK_SET_RATE_PARENT,
1108 static struct clk_regmap meson8b_vclk_div2_div_gate = {
1109 .data = &(struct clk_regmap_gate_data){
1110 .offset = HHI_VID_CLK_DIV,
1113 .hw.init = &(struct clk_init_data){
1114 .name = "vclk_div2_en",
1115 .ops = &clk_regmap_gate_ro_ops,
1116 .parent_names = (const char *[]){ "vclk_div2" },
1118 .flags = CLK_SET_RATE_PARENT,
1122 static struct clk_fixed_factor meson8b_vclk_div4_div = {
1125 .hw.init = &(struct clk_init_data){
1126 .name = "vclk_div4",
1127 .ops = &clk_fixed_factor_ops,
1128 .parent_names = (const char *[]){ "vclk_in_en" },
1130 .flags = CLK_SET_RATE_PARENT,
1134 static struct clk_regmap meson8b_vclk_div4_div_gate = {
1135 .data = &(struct clk_regmap_gate_data){
1136 .offset = HHI_VID_CLK_DIV,
1139 .hw.init = &(struct clk_init_data){
1140 .name = "vclk_div4_en",
1141 .ops = &clk_regmap_gate_ro_ops,
1142 .parent_names = (const char *[]){ "vclk_div4" },
1144 .flags = CLK_SET_RATE_PARENT,
1148 static struct clk_fixed_factor meson8b_vclk_div6_div = {
1151 .hw.init = &(struct clk_init_data){
1152 .name = "vclk_div6",
1153 .ops = &clk_fixed_factor_ops,
1154 .parent_names = (const char *[]){ "vclk_in_en" },
1156 .flags = CLK_SET_RATE_PARENT,
1160 static struct clk_regmap meson8b_vclk_div6_div_gate = {
1161 .data = &(struct clk_regmap_gate_data){
1162 .offset = HHI_VID_CLK_DIV,
1165 .hw.init = &(struct clk_init_data){
1166 .name = "vclk_div6_en",
1167 .ops = &clk_regmap_gate_ro_ops,
1168 .parent_names = (const char *[]){ "vclk_div6" },
1170 .flags = CLK_SET_RATE_PARENT,
1174 static struct clk_fixed_factor meson8b_vclk_div12_div = {
1177 .hw.init = &(struct clk_init_data){
1178 .name = "vclk_div12",
1179 .ops = &clk_fixed_factor_ops,
1180 .parent_names = (const char *[]){ "vclk_in_en" },
1182 .flags = CLK_SET_RATE_PARENT,
1186 static struct clk_regmap meson8b_vclk_div12_div_gate = {
1187 .data = &(struct clk_regmap_gate_data){
1188 .offset = HHI_VID_CLK_DIV,
1191 .hw.init = &(struct clk_init_data){
1192 .name = "vclk_div12_en",
1193 .ops = &clk_regmap_gate_ro_ops,
1194 .parent_names = (const char *[]){ "vclk_div12" },
1196 .flags = CLK_SET_RATE_PARENT,
1200 static struct clk_regmap meson8b_vclk2_in_sel = {
1201 .data = &(struct clk_regmap_mux_data){
1202 .offset = HHI_VIID_CLK_CNTL,
1206 .hw.init = &(struct clk_init_data){
1207 .name = "vclk2_in_sel",
1208 .ops = &clk_regmap_mux_ro_ops,
1209 .parent_names = meson8b_vclk_mux_parents,
1210 .num_parents = ARRAY_SIZE(meson8b_vclk_mux_parents),
1211 .flags = CLK_SET_RATE_PARENT,
1215 static struct clk_regmap meson8b_vclk2_clk_in_en = {
1216 .data = &(struct clk_regmap_gate_data){
1217 .offset = HHI_VIID_CLK_DIV,
1220 .hw.init = &(struct clk_init_data){
1221 .name = "vclk2_in_en",
1222 .ops = &clk_regmap_gate_ro_ops,
1223 .parent_names = (const char *[]){ "vclk2_in_sel" },
1225 .flags = CLK_SET_RATE_PARENT,
1229 static struct clk_regmap meson8b_vclk2_div1_gate = {
1230 .data = &(struct clk_regmap_gate_data){
1231 .offset = HHI_VIID_CLK_DIV,
1234 .hw.init = &(struct clk_init_data){
1235 .name = "vclk2_div1_en",
1236 .ops = &clk_regmap_gate_ro_ops,
1237 .parent_names = (const char *[]){ "vclk2_in_en" },
1239 .flags = CLK_SET_RATE_PARENT,
1243 static struct clk_fixed_factor meson8b_vclk2_div2_div = {
1246 .hw.init = &(struct clk_init_data){
1247 .name = "vclk2_div2",
1248 .ops = &clk_fixed_factor_ops,
1249 .parent_names = (const char *[]){ "vclk2_in_en" },
1251 .flags = CLK_SET_RATE_PARENT,
1255 static struct clk_regmap meson8b_vclk2_div2_div_gate = {
1256 .data = &(struct clk_regmap_gate_data){
1257 .offset = HHI_VIID_CLK_DIV,
1260 .hw.init = &(struct clk_init_data){
1261 .name = "vclk2_div2_en",
1262 .ops = &clk_regmap_gate_ro_ops,
1263 .parent_names = (const char *[]){ "vclk2_div2" },
1265 .flags = CLK_SET_RATE_PARENT,
1269 static struct clk_fixed_factor meson8b_vclk2_div4_div = {
1272 .hw.init = &(struct clk_init_data){
1273 .name = "vclk2_div4",
1274 .ops = &clk_fixed_factor_ops,
1275 .parent_names = (const char *[]){ "vclk2_in_en" },
1277 .flags = CLK_SET_RATE_PARENT,
1281 static struct clk_regmap meson8b_vclk2_div4_div_gate = {
1282 .data = &(struct clk_regmap_gate_data){
1283 .offset = HHI_VIID_CLK_DIV,
1286 .hw.init = &(struct clk_init_data){
1287 .name = "vclk2_div4_en",
1288 .ops = &clk_regmap_gate_ro_ops,
1289 .parent_names = (const char *[]){ "vclk2_div4" },
1291 .flags = CLK_SET_RATE_PARENT,
1295 static struct clk_fixed_factor meson8b_vclk2_div6_div = {
1298 .hw.init = &(struct clk_init_data){
1299 .name = "vclk2_div6",
1300 .ops = &clk_fixed_factor_ops,
1301 .parent_names = (const char *[]){ "vclk2_in_en" },
1303 .flags = CLK_SET_RATE_PARENT,
1307 static struct clk_regmap meson8b_vclk2_div6_div_gate = {
1308 .data = &(struct clk_regmap_gate_data){
1309 .offset = HHI_VIID_CLK_DIV,
1312 .hw.init = &(struct clk_init_data){
1313 .name = "vclk2_div6_en",
1314 .ops = &clk_regmap_gate_ro_ops,
1315 .parent_names = (const char *[]){ "vclk2_div6" },
1317 .flags = CLK_SET_RATE_PARENT,
1321 static struct clk_fixed_factor meson8b_vclk2_div12_div = {
1324 .hw.init = &(struct clk_init_data){
1325 .name = "vclk2_div12",
1326 .ops = &clk_fixed_factor_ops,
1327 .parent_names = (const char *[]){ "vclk2_in_en" },
1329 .flags = CLK_SET_RATE_PARENT,
1333 static struct clk_regmap meson8b_vclk2_div12_div_gate = {
1334 .data = &(struct clk_regmap_gate_data){
1335 .offset = HHI_VIID_CLK_DIV,
1338 .hw.init = &(struct clk_init_data){
1339 .name = "vclk2_div12_en",
1340 .ops = &clk_regmap_gate_ro_ops,
1341 .parent_names = (const char *[]){ "vclk2_div12" },
1343 .flags = CLK_SET_RATE_PARENT,
1347 static const char * const meson8b_vclk_enc_mux_parents[] = {
1348 "vclk_div1_en", "vclk_div2_en", "vclk_div4_en", "vclk_div6_en",
1352 static struct clk_regmap meson8b_cts_enct_sel = {
1353 .data = &(struct clk_regmap_mux_data){
1354 .offset = HHI_VID_CLK_DIV,
1358 .hw.init = &(struct clk_init_data){
1359 .name = "cts_enct_sel",
1360 .ops = &clk_regmap_mux_ro_ops,
1361 .parent_names = meson8b_vclk_enc_mux_parents,
1362 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1363 .flags = CLK_SET_RATE_PARENT,
1367 static struct clk_regmap meson8b_cts_enct = {
1368 .data = &(struct clk_regmap_gate_data){
1369 .offset = HHI_VID_CLK_CNTL2,
1372 .hw.init = &(struct clk_init_data){
1374 .ops = &clk_regmap_gate_ro_ops,
1375 .parent_names = (const char *[]){ "cts_enct_sel" },
1377 .flags = CLK_SET_RATE_PARENT,
1381 static struct clk_regmap meson8b_cts_encp_sel = {
1382 .data = &(struct clk_regmap_mux_data){
1383 .offset = HHI_VID_CLK_DIV,
1387 .hw.init = &(struct clk_init_data){
1388 .name = "cts_encp_sel",
1389 .ops = &clk_regmap_mux_ro_ops,
1390 .parent_names = meson8b_vclk_enc_mux_parents,
1391 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1392 .flags = CLK_SET_RATE_PARENT,
1396 static struct clk_regmap meson8b_cts_encp = {
1397 .data = &(struct clk_regmap_gate_data){
1398 .offset = HHI_VID_CLK_CNTL2,
1401 .hw.init = &(struct clk_init_data){
1403 .ops = &clk_regmap_gate_ro_ops,
1404 .parent_names = (const char *[]){ "cts_encp_sel" },
1406 .flags = CLK_SET_RATE_PARENT,
1410 static struct clk_regmap meson8b_cts_enci_sel = {
1411 .data = &(struct clk_regmap_mux_data){
1412 .offset = HHI_VID_CLK_DIV,
1416 .hw.init = &(struct clk_init_data){
1417 .name = "cts_enci_sel",
1418 .ops = &clk_regmap_mux_ro_ops,
1419 .parent_names = meson8b_vclk_enc_mux_parents,
1420 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1421 .flags = CLK_SET_RATE_PARENT,
1425 static struct clk_regmap meson8b_cts_enci = {
1426 .data = &(struct clk_regmap_gate_data){
1427 .offset = HHI_VID_CLK_CNTL2,
1430 .hw.init = &(struct clk_init_data){
1432 .ops = &clk_regmap_gate_ro_ops,
1433 .parent_names = (const char *[]){ "cts_enci_sel" },
1435 .flags = CLK_SET_RATE_PARENT,
1439 static struct clk_regmap meson8b_hdmi_tx_pixel_sel = {
1440 .data = &(struct clk_regmap_mux_data){
1441 .offset = HHI_HDMI_CLK_CNTL,
1445 .hw.init = &(struct clk_init_data){
1446 .name = "hdmi_tx_pixel_sel",
1447 .ops = &clk_regmap_mux_ro_ops,
1448 .parent_names = meson8b_vclk_enc_mux_parents,
1449 .num_parents = ARRAY_SIZE(meson8b_vclk_enc_mux_parents),
1450 .flags = CLK_SET_RATE_PARENT,
1454 static struct clk_regmap meson8b_hdmi_tx_pixel = {
1455 .data = &(struct clk_regmap_gate_data){
1456 .offset = HHI_VID_CLK_CNTL2,
1459 .hw.init = &(struct clk_init_data){
1460 .name = "hdmi_tx_pixel",
1461 .ops = &clk_regmap_gate_ro_ops,
1462 .parent_names = (const char *[]){ "hdmi_tx_pixel_sel" },
1464 .flags = CLK_SET_RATE_PARENT,
1468 static const char * const meson8b_vclk2_enc_mux_parents[] = {
1469 "vclk2_div1_en", "vclk2_div2_en", "vclk2_div4_en", "vclk2_div6_en",
1473 static struct clk_regmap meson8b_cts_encl_sel = {
1474 .data = &(struct clk_regmap_mux_data){
1475 .offset = HHI_VIID_CLK_DIV,
1479 .hw.init = &(struct clk_init_data){
1480 .name = "cts_encl_sel",
1481 .ops = &clk_regmap_mux_ro_ops,
1482 .parent_names = meson8b_vclk2_enc_mux_parents,
1483 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
1484 .flags = CLK_SET_RATE_PARENT,
1488 static struct clk_regmap meson8b_cts_encl = {
1489 .data = &(struct clk_regmap_gate_data){
1490 .offset = HHI_VID_CLK_CNTL2,
1493 .hw.init = &(struct clk_init_data){
1495 .ops = &clk_regmap_gate_ro_ops,
1496 .parent_names = (const char *[]){ "cts_encl_sel" },
1498 .flags = CLK_SET_RATE_PARENT,
1502 static struct clk_regmap meson8b_cts_vdac0_sel = {
1503 .data = &(struct clk_regmap_mux_data){
1504 .offset = HHI_VIID_CLK_DIV,
1508 .hw.init = &(struct clk_init_data){
1509 .name = "cts_vdac0_sel",
1510 .ops = &clk_regmap_mux_ro_ops,
1511 .parent_names = meson8b_vclk2_enc_mux_parents,
1512 .num_parents = ARRAY_SIZE(meson8b_vclk2_enc_mux_parents),
1513 .flags = CLK_SET_RATE_PARENT,
1517 static struct clk_regmap meson8b_cts_vdac0 = {
1518 .data = &(struct clk_regmap_gate_data){
1519 .offset = HHI_VID_CLK_CNTL2,
1522 .hw.init = &(struct clk_init_data){
1523 .name = "cts_vdac0",
1524 .ops = &clk_regmap_gate_ro_ops,
1525 .parent_names = (const char *[]){ "cts_vdac0_sel" },
1527 .flags = CLK_SET_RATE_PARENT,
1531 static struct clk_regmap meson8b_hdmi_sys_sel = {
1532 .data = &(struct clk_regmap_mux_data){
1533 .offset = HHI_HDMI_CLK_CNTL,
1536 .flags = CLK_MUX_ROUND_CLOSEST,
1538 .hw.init = &(struct clk_init_data){
1539 .name = "hdmi_sys_sel",
1540 .ops = &clk_regmap_mux_ro_ops,
1541 /* FIXME: all other parents are unknown */
1542 .parent_names = (const char *[]){ "xtal" },
1544 .flags = CLK_SET_RATE_NO_REPARENT,
1548 static struct clk_regmap meson8b_hdmi_sys_div = {
1549 .data = &(struct clk_regmap_div_data){
1550 .offset = HHI_HDMI_CLK_CNTL,
1554 .hw.init = &(struct clk_init_data){
1555 .name = "hdmi_sys_div",
1556 .ops = &clk_regmap_divider_ro_ops,
1557 .parent_names = (const char *[]){ "hdmi_sys_sel" },
1559 .flags = CLK_SET_RATE_PARENT,
1563 static struct clk_regmap meson8b_hdmi_sys = {
1564 .data = &(struct clk_regmap_gate_data){
1565 .offset = HHI_HDMI_CLK_CNTL,
1568 .hw.init = &(struct clk_init_data) {
1570 .ops = &clk_regmap_gate_ro_ops,
1571 .parent_names = (const char *[]){ "hdmi_sys_div" },
1573 .flags = CLK_SET_RATE_PARENT,
1578 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
1579 * muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
1580 * has mali_0 and no glitch-free mux.
1582 static const char * const meson8b_mali_0_1_parent_names[] = {
1583 "xtal", "mpll2", "mpll1", "fclk_div7", "fclk_div4", "fclk_div3",
1587 static u32 meson8b_mali_0_1_mux_table[] = { 0, 2, 3, 4, 5, 6, 7 };
1589 static struct clk_regmap meson8b_mali_0_sel = {
1590 .data = &(struct clk_regmap_mux_data){
1591 .offset = HHI_MALI_CLK_CNTL,
1594 .table = meson8b_mali_0_1_mux_table,
1596 .hw.init = &(struct clk_init_data){
1597 .name = "mali_0_sel",
1598 .ops = &clk_regmap_mux_ops,
1599 .parent_names = meson8b_mali_0_1_parent_names,
1600 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
1602 * Don't propagate rate changes up because the only changeable
1603 * parents are mpll1 and mpll2 but we need those for audio and
1604 * RGMII (Ethernet). We don't want to change the audio or
1605 * Ethernet clocks when setting the GPU frequency.
1611 static struct clk_regmap meson8b_mali_0_div = {
1612 .data = &(struct clk_regmap_div_data){
1613 .offset = HHI_MALI_CLK_CNTL,
1617 .hw.init = &(struct clk_init_data){
1618 .name = "mali_0_div",
1619 .ops = &clk_regmap_divider_ops,
1620 .parent_names = (const char *[]){ "mali_0_sel" },
1622 .flags = CLK_SET_RATE_PARENT,
1626 static struct clk_regmap meson8b_mali_0 = {
1627 .data = &(struct clk_regmap_gate_data){
1628 .offset = HHI_MALI_CLK_CNTL,
1631 .hw.init = &(struct clk_init_data){
1633 .ops = &clk_regmap_gate_ops,
1634 .parent_names = (const char *[]){ "mali_0_div" },
1636 .flags = CLK_SET_RATE_PARENT,
1640 static struct clk_regmap meson8b_mali_1_sel = {
1641 .data = &(struct clk_regmap_mux_data){
1642 .offset = HHI_MALI_CLK_CNTL,
1645 .table = meson8b_mali_0_1_mux_table,
1647 .hw.init = &(struct clk_init_data){
1648 .name = "mali_1_sel",
1649 .ops = &clk_regmap_mux_ops,
1650 .parent_names = meson8b_mali_0_1_parent_names,
1651 .num_parents = ARRAY_SIZE(meson8b_mali_0_1_parent_names),
1653 * Don't propagate rate changes up because the only changeable
1654 * parents are mpll1 and mpll2 but we need those for audio and
1655 * RGMII (Ethernet). We don't want to change the audio or
1656 * Ethernet clocks when setting the GPU frequency.
1662 static struct clk_regmap meson8b_mali_1_div = {
1663 .data = &(struct clk_regmap_div_data){
1664 .offset = HHI_MALI_CLK_CNTL,
1668 .hw.init = &(struct clk_init_data){
1669 .name = "mali_1_div",
1670 .ops = &clk_regmap_divider_ops,
1671 .parent_names = (const char *[]){ "mali_1_sel" },
1673 .flags = CLK_SET_RATE_PARENT,
1677 static struct clk_regmap meson8b_mali_1 = {
1678 .data = &(struct clk_regmap_gate_data){
1679 .offset = HHI_MALI_CLK_CNTL,
1682 .hw.init = &(struct clk_init_data){
1684 .ops = &clk_regmap_gate_ops,
1685 .parent_names = (const char *[]){ "mali_1_div" },
1687 .flags = CLK_SET_RATE_PARENT,
1691 static struct clk_regmap meson8b_mali = {
1692 .data = &(struct clk_regmap_mux_data){
1693 .offset = HHI_MALI_CLK_CNTL,
1697 .hw.init = &(struct clk_init_data){
1699 .ops = &clk_regmap_mux_ops,
1700 .parent_names = (const char *[]){ "mali_0", "mali_1" },
1702 .flags = CLK_SET_RATE_PARENT,
1706 /* Everything Else (EE) domain gates */
1708 static MESON_GATE(meson8b_ddr, HHI_GCLK_MPEG0, 0);
1709 static MESON_GATE(meson8b_dos, HHI_GCLK_MPEG0, 1);
1710 static MESON_GATE(meson8b_isa, HHI_GCLK_MPEG0, 5);
1711 static MESON_GATE(meson8b_pl301, HHI_GCLK_MPEG0, 6);
1712 static MESON_GATE(meson8b_periphs, HHI_GCLK_MPEG0, 7);
1713 static MESON_GATE(meson8b_spicc, HHI_GCLK_MPEG0, 8);
1714 static MESON_GATE(meson8b_i2c, HHI_GCLK_MPEG0, 9);
1715 static MESON_GATE(meson8b_sar_adc, HHI_GCLK_MPEG0, 10);
1716 static MESON_GATE(meson8b_smart_card, HHI_GCLK_MPEG0, 11);
1717 static MESON_GATE(meson8b_rng0, HHI_GCLK_MPEG0, 12);
1718 static MESON_GATE(meson8b_uart0, HHI_GCLK_MPEG0, 13);
1719 static MESON_GATE(meson8b_sdhc, HHI_GCLK_MPEG0, 14);
1720 static MESON_GATE(meson8b_stream, HHI_GCLK_MPEG0, 15);
1721 static MESON_GATE(meson8b_async_fifo, HHI_GCLK_MPEG0, 16);
1722 static MESON_GATE(meson8b_sdio, HHI_GCLK_MPEG0, 17);
1723 static MESON_GATE(meson8b_abuf, HHI_GCLK_MPEG0, 18);
1724 static MESON_GATE(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19);
1725 static MESON_GATE(meson8b_assist_misc, HHI_GCLK_MPEG0, 23);
1726 static MESON_GATE(meson8b_spi, HHI_GCLK_MPEG0, 30);
1728 static MESON_GATE(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2);
1729 static MESON_GATE(meson8b_eth, HHI_GCLK_MPEG1, 3);
1730 static MESON_GATE(meson8b_demux, HHI_GCLK_MPEG1, 4);
1731 static MESON_GATE(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6);
1732 static MESON_GATE(meson8b_iec958, HHI_GCLK_MPEG1, 7);
1733 static MESON_GATE(meson8b_i2s_out, HHI_GCLK_MPEG1, 8);
1734 static MESON_GATE(meson8b_amclk, HHI_GCLK_MPEG1, 9);
1735 static MESON_GATE(meson8b_aififo2, HHI_GCLK_MPEG1, 10);
1736 static MESON_GATE(meson8b_mixer, HHI_GCLK_MPEG1, 11);
1737 static MESON_GATE(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12);
1738 static MESON_GATE(meson8b_adc, HHI_GCLK_MPEG1, 13);
1739 static MESON_GATE(meson8b_blkmv, HHI_GCLK_MPEG1, 14);
1740 static MESON_GATE(meson8b_aiu, HHI_GCLK_MPEG1, 15);
1741 static MESON_GATE(meson8b_uart1, HHI_GCLK_MPEG1, 16);
1742 static MESON_GATE(meson8b_g2d, HHI_GCLK_MPEG1, 20);
1743 static MESON_GATE(meson8b_usb0, HHI_GCLK_MPEG1, 21);
1744 static MESON_GATE(meson8b_usb1, HHI_GCLK_MPEG1, 22);
1745 static MESON_GATE(meson8b_reset, HHI_GCLK_MPEG1, 23);
1746 static MESON_GATE(meson8b_nand, HHI_GCLK_MPEG1, 24);
1747 static MESON_GATE(meson8b_dos_parser, HHI_GCLK_MPEG1, 25);
1748 static MESON_GATE(meson8b_usb, HHI_GCLK_MPEG1, 26);
1749 static MESON_GATE(meson8b_vdin1, HHI_GCLK_MPEG1, 28);
1750 static MESON_GATE(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29);
1751 static MESON_GATE(meson8b_efuse, HHI_GCLK_MPEG1, 30);
1752 static MESON_GATE(meson8b_boot_rom, HHI_GCLK_MPEG1, 31);
1754 static MESON_GATE(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1755 static MESON_GATE(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1756 static MESON_GATE(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
1757 static MESON_GATE(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4);
1758 static MESON_GATE(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
1759 static MESON_GATE(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
1760 static MESON_GATE(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11);
1761 static MESON_GATE(meson8b_dvin, HHI_GCLK_MPEG2, 12);
1762 static MESON_GATE(meson8b_uart2, HHI_GCLK_MPEG2, 15);
1763 static MESON_GATE(meson8b_sana, HHI_GCLK_MPEG2, 22);
1764 static MESON_GATE(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25);
1765 static MESON_GATE(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1766 static MESON_GATE(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29);
1768 static MESON_GATE(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1);
1769 static MESON_GATE(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2);
1770 static MESON_GATE(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3);
1771 static MESON_GATE(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4);
1772 static MESON_GATE(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8);
1773 static MESON_GATE(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9);
1774 static MESON_GATE(meson8b_dac_clk, HHI_GCLK_OTHER, 10);
1775 static MESON_GATE(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14);
1776 static MESON_GATE(meson8b_iec958_gate, HHI_GCLK_OTHER, 16);
1777 static MESON_GATE(meson8b_enc480p, HHI_GCLK_OTHER, 20);
1778 static MESON_GATE(meson8b_rng1, HHI_GCLK_OTHER, 21);
1779 static MESON_GATE(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22);
1780 static MESON_GATE(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
1781 static MESON_GATE(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25);
1782 static MESON_GATE(meson8b_vclk2_other, HHI_GCLK_OTHER, 26);
1783 static MESON_GATE(meson8b_edp, HHI_GCLK_OTHER, 31);
1785 /* Always On (AO) domain gates */
1787 static MESON_GATE(meson8b_ao_media_cpu, HHI_GCLK_AO, 0);
1788 static MESON_GATE(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1);
1789 static MESON_GATE(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2);
1790 static MESON_GATE(meson8b_ao_iface, HHI_GCLK_AO, 3);
1792 static struct clk_hw_onecell_data meson8_hw_onecell_data = {
1794 [CLKID_XTAL] = &meson8b_xtal.hw,
1795 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
1796 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
1797 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
1798 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
1799 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
1800 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
1801 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
1802 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
1803 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
1804 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
1805 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
1806 [CLKID_CLK81] = &meson8b_clk81.hw,
1807 [CLKID_DDR] = &meson8b_ddr.hw,
1808 [CLKID_DOS] = &meson8b_dos.hw,
1809 [CLKID_ISA] = &meson8b_isa.hw,
1810 [CLKID_PL301] = &meson8b_pl301.hw,
1811 [CLKID_PERIPHS] = &meson8b_periphs.hw,
1812 [CLKID_SPICC] = &meson8b_spicc.hw,
1813 [CLKID_I2C] = &meson8b_i2c.hw,
1814 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
1815 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
1816 [CLKID_RNG0] = &meson8b_rng0.hw,
1817 [CLKID_UART0] = &meson8b_uart0.hw,
1818 [CLKID_SDHC] = &meson8b_sdhc.hw,
1819 [CLKID_STREAM] = &meson8b_stream.hw,
1820 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
1821 [CLKID_SDIO] = &meson8b_sdio.hw,
1822 [CLKID_ABUF] = &meson8b_abuf.hw,
1823 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
1824 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
1825 [CLKID_SPI] = &meson8b_spi.hw,
1826 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
1827 [CLKID_ETH] = &meson8b_eth.hw,
1828 [CLKID_DEMUX] = &meson8b_demux.hw,
1829 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
1830 [CLKID_IEC958] = &meson8b_iec958.hw,
1831 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
1832 [CLKID_AMCLK] = &meson8b_amclk.hw,
1833 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
1834 [CLKID_MIXER] = &meson8b_mixer.hw,
1835 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
1836 [CLKID_ADC] = &meson8b_adc.hw,
1837 [CLKID_BLKMV] = &meson8b_blkmv.hw,
1838 [CLKID_AIU] = &meson8b_aiu.hw,
1839 [CLKID_UART1] = &meson8b_uart1.hw,
1840 [CLKID_G2D] = &meson8b_g2d.hw,
1841 [CLKID_USB0] = &meson8b_usb0.hw,
1842 [CLKID_USB1] = &meson8b_usb1.hw,
1843 [CLKID_RESET] = &meson8b_reset.hw,
1844 [CLKID_NAND] = &meson8b_nand.hw,
1845 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
1846 [CLKID_USB] = &meson8b_usb.hw,
1847 [CLKID_VDIN1] = &meson8b_vdin1.hw,
1848 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
1849 [CLKID_EFUSE] = &meson8b_efuse.hw,
1850 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
1851 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
1852 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
1853 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
1854 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
1855 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
1856 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
1857 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
1858 [CLKID_DVIN] = &meson8b_dvin.hw,
1859 [CLKID_UART2] = &meson8b_uart2.hw,
1860 [CLKID_SANA] = &meson8b_sana.hw,
1861 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
1862 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
1863 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
1864 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
1865 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
1866 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
1867 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
1868 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
1869 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
1870 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
1871 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
1872 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
1873 [CLKID_ENC480P] = &meson8b_enc480p.hw,
1874 [CLKID_RNG1] = &meson8b_rng1.hw,
1875 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
1876 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
1877 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
1878 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
1879 [CLKID_EDP] = &meson8b_edp.hw,
1880 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
1881 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
1882 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
1883 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
1884 [CLKID_MPLL0] = &meson8b_mpll0.hw,
1885 [CLKID_MPLL1] = &meson8b_mpll1.hw,
1886 [CLKID_MPLL2] = &meson8b_mpll2.hw,
1887 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
1888 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
1889 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
1890 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
1891 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
1892 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
1893 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
1894 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
1895 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
1896 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
1897 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
1898 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
1899 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
1900 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
1901 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
1902 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
1903 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
1904 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
1905 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
1906 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
1907 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
1908 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
1909 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
1910 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
1911 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
1912 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
1913 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
1914 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
1915 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
1916 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
1917 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
1918 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
1919 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
1920 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
1921 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
1922 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
1923 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
1924 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
1925 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
1926 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
1927 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
1928 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
1929 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
1930 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
1931 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
1932 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
1933 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
1934 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
1935 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
1936 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
1937 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
1938 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
1939 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
1940 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
1941 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
1942 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
1943 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
1944 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
1945 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
1946 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
1947 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
1948 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
1949 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
1950 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
1951 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
1952 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
1953 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
1954 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
1955 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
1956 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
1957 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
1958 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
1959 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
1960 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
1961 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
1962 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
1963 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
1964 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
1965 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
1966 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
1967 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
1968 [CLKID_MALI] = &meson8b_mali_0.hw,
1969 [CLK_NR_CLKS] = NULL,
1974 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
1976 [CLKID_XTAL] = &meson8b_xtal.hw,
1977 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
1978 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
1979 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
1980 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
1981 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
1982 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
1983 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
1984 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
1985 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
1986 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
1987 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
1988 [CLKID_CLK81] = &meson8b_clk81.hw,
1989 [CLKID_DDR] = &meson8b_ddr.hw,
1990 [CLKID_DOS] = &meson8b_dos.hw,
1991 [CLKID_ISA] = &meson8b_isa.hw,
1992 [CLKID_PL301] = &meson8b_pl301.hw,
1993 [CLKID_PERIPHS] = &meson8b_periphs.hw,
1994 [CLKID_SPICC] = &meson8b_spicc.hw,
1995 [CLKID_I2C] = &meson8b_i2c.hw,
1996 [CLKID_SAR_ADC] = &meson8b_sar_adc.hw,
1997 [CLKID_SMART_CARD] = &meson8b_smart_card.hw,
1998 [CLKID_RNG0] = &meson8b_rng0.hw,
1999 [CLKID_UART0] = &meson8b_uart0.hw,
2000 [CLKID_SDHC] = &meson8b_sdhc.hw,
2001 [CLKID_STREAM] = &meson8b_stream.hw,
2002 [CLKID_ASYNC_FIFO] = &meson8b_async_fifo.hw,
2003 [CLKID_SDIO] = &meson8b_sdio.hw,
2004 [CLKID_ABUF] = &meson8b_abuf.hw,
2005 [CLKID_HIU_IFACE] = &meson8b_hiu_iface.hw,
2006 [CLKID_ASSIST_MISC] = &meson8b_assist_misc.hw,
2007 [CLKID_SPI] = &meson8b_spi.hw,
2008 [CLKID_I2S_SPDIF] = &meson8b_i2s_spdif.hw,
2009 [CLKID_ETH] = &meson8b_eth.hw,
2010 [CLKID_DEMUX] = &meson8b_demux.hw,
2011 [CLKID_AIU_GLUE] = &meson8b_aiu_glue.hw,
2012 [CLKID_IEC958] = &meson8b_iec958.hw,
2013 [CLKID_I2S_OUT] = &meson8b_i2s_out.hw,
2014 [CLKID_AMCLK] = &meson8b_amclk.hw,
2015 [CLKID_AIFIFO2] = &meson8b_aififo2.hw,
2016 [CLKID_MIXER] = &meson8b_mixer.hw,
2017 [CLKID_MIXER_IFACE] = &meson8b_mixer_iface.hw,
2018 [CLKID_ADC] = &meson8b_adc.hw,
2019 [CLKID_BLKMV] = &meson8b_blkmv.hw,
2020 [CLKID_AIU] = &meson8b_aiu.hw,
2021 [CLKID_UART1] = &meson8b_uart1.hw,
2022 [CLKID_G2D] = &meson8b_g2d.hw,
2023 [CLKID_USB0] = &meson8b_usb0.hw,
2024 [CLKID_USB1] = &meson8b_usb1.hw,
2025 [CLKID_RESET] = &meson8b_reset.hw,
2026 [CLKID_NAND] = &meson8b_nand.hw,
2027 [CLKID_DOS_PARSER] = &meson8b_dos_parser.hw,
2028 [CLKID_USB] = &meson8b_usb.hw,
2029 [CLKID_VDIN1] = &meson8b_vdin1.hw,
2030 [CLKID_AHB_ARB0] = &meson8b_ahb_arb0.hw,
2031 [CLKID_EFUSE] = &meson8b_efuse.hw,
2032 [CLKID_BOOT_ROM] = &meson8b_boot_rom.hw,
2033 [CLKID_AHB_DATA_BUS] = &meson8b_ahb_data_bus.hw,
2034 [CLKID_AHB_CTRL_BUS] = &meson8b_ahb_ctrl_bus.hw,
2035 [CLKID_HDMI_INTR_SYNC] = &meson8b_hdmi_intr_sync.hw,
2036 [CLKID_HDMI_PCLK] = &meson8b_hdmi_pclk.hw,
2037 [CLKID_USB1_DDR_BRIDGE] = &meson8b_usb1_ddr_bridge.hw,
2038 [CLKID_USB0_DDR_BRIDGE] = &meson8b_usb0_ddr_bridge.hw,
2039 [CLKID_MMC_PCLK] = &meson8b_mmc_pclk.hw,
2040 [CLKID_DVIN] = &meson8b_dvin.hw,
2041 [CLKID_UART2] = &meson8b_uart2.hw,
2042 [CLKID_SANA] = &meson8b_sana.hw,
2043 [CLKID_VPU_INTR] = &meson8b_vpu_intr.hw,
2044 [CLKID_SEC_AHB_AHB3_BRIDGE] = &meson8b_sec_ahb_ahb3_bridge.hw,
2045 [CLKID_CLK81_A9] = &meson8b_clk81_a9.hw,
2046 [CLKID_VCLK2_VENCI0] = &meson8b_vclk2_venci0.hw,
2047 [CLKID_VCLK2_VENCI1] = &meson8b_vclk2_venci1.hw,
2048 [CLKID_VCLK2_VENCP0] = &meson8b_vclk2_vencp0.hw,
2049 [CLKID_VCLK2_VENCP1] = &meson8b_vclk2_vencp1.hw,
2050 [CLKID_GCLK_VENCI_INT] = &meson8b_gclk_venci_int.hw,
2051 [CLKID_GCLK_VENCP_INT] = &meson8b_gclk_vencp_int.hw,
2052 [CLKID_DAC_CLK] = &meson8b_dac_clk.hw,
2053 [CLKID_AOCLK_GATE] = &meson8b_aoclk_gate.hw,
2054 [CLKID_IEC958_GATE] = &meson8b_iec958_gate.hw,
2055 [CLKID_ENC480P] = &meson8b_enc480p.hw,
2056 [CLKID_RNG1] = &meson8b_rng1.hw,
2057 [CLKID_GCLK_VENCL_INT] = &meson8b_gclk_vencl_int.hw,
2058 [CLKID_VCLK2_VENCLMCC] = &meson8b_vclk2_venclmcc.hw,
2059 [CLKID_VCLK2_VENCL] = &meson8b_vclk2_vencl.hw,
2060 [CLKID_VCLK2_OTHER] = &meson8b_vclk2_other.hw,
2061 [CLKID_EDP] = &meson8b_edp.hw,
2062 [CLKID_AO_MEDIA_CPU] = &meson8b_ao_media_cpu.hw,
2063 [CLKID_AO_AHB_SRAM] = &meson8b_ao_ahb_sram.hw,
2064 [CLKID_AO_AHB_BUS] = &meson8b_ao_ahb_bus.hw,
2065 [CLKID_AO_IFACE] = &meson8b_ao_iface.hw,
2066 [CLKID_MPLL0] = &meson8b_mpll0.hw,
2067 [CLKID_MPLL1] = &meson8b_mpll1.hw,
2068 [CLKID_MPLL2] = &meson8b_mpll2.hw,
2069 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
2070 [CLKID_MPLL1_DIV] = &meson8b_mpll1_div.hw,
2071 [CLKID_MPLL2_DIV] = &meson8b_mpll2_div.hw,
2072 [CLKID_CPU_IN_SEL] = &meson8b_cpu_in_sel.hw,
2073 [CLKID_CPU_IN_DIV2] = &meson8b_cpu_in_div2.hw,
2074 [CLKID_CPU_IN_DIV3] = &meson8b_cpu_in_div3.hw,
2075 [CLKID_CPU_SCALE_DIV] = &meson8b_cpu_scale_div.hw,
2076 [CLKID_CPU_SCALE_OUT_SEL] = &meson8b_cpu_scale_out_sel.hw,
2077 [CLKID_MPLL_PREDIV] = &meson8b_mpll_prediv.hw,
2078 [CLKID_FCLK_DIV2_DIV] = &meson8b_fclk_div2_div.hw,
2079 [CLKID_FCLK_DIV3_DIV] = &meson8b_fclk_div3_div.hw,
2080 [CLKID_FCLK_DIV4_DIV] = &meson8b_fclk_div4_div.hw,
2081 [CLKID_FCLK_DIV5_DIV] = &meson8b_fclk_div5_div.hw,
2082 [CLKID_FCLK_DIV7_DIV] = &meson8b_fclk_div7_div.hw,
2083 [CLKID_NAND_SEL] = &meson8b_nand_clk_sel.hw,
2084 [CLKID_NAND_DIV] = &meson8b_nand_clk_div.hw,
2085 [CLKID_NAND_CLK] = &meson8b_nand_clk_gate.hw,
2086 [CLKID_PLL_FIXED_DCO] = &meson8b_fixed_pll_dco.hw,
2087 [CLKID_HDMI_PLL_DCO] = &meson8b_hdmi_pll_dco.hw,
2088 [CLKID_PLL_SYS_DCO] = &meson8b_sys_pll_dco.hw,
2089 [CLKID_CPU_CLK_DIV2] = &meson8b_cpu_clk_div2.hw,
2090 [CLKID_CPU_CLK_DIV3] = &meson8b_cpu_clk_div3.hw,
2091 [CLKID_CPU_CLK_DIV4] = &meson8b_cpu_clk_div4.hw,
2092 [CLKID_CPU_CLK_DIV5] = &meson8b_cpu_clk_div5.hw,
2093 [CLKID_CPU_CLK_DIV6] = &meson8b_cpu_clk_div6.hw,
2094 [CLKID_CPU_CLK_DIV7] = &meson8b_cpu_clk_div7.hw,
2095 [CLKID_CPU_CLK_DIV8] = &meson8b_cpu_clk_div8.hw,
2096 [CLKID_APB_SEL] = &meson8b_apb_clk_sel.hw,
2097 [CLKID_APB] = &meson8b_apb_clk_gate.hw,
2098 [CLKID_PERIPH_SEL] = &meson8b_periph_clk_sel.hw,
2099 [CLKID_PERIPH] = &meson8b_periph_clk_gate.hw,
2100 [CLKID_AXI_SEL] = &meson8b_axi_clk_sel.hw,
2101 [CLKID_AXI] = &meson8b_axi_clk_gate.hw,
2102 [CLKID_L2_DRAM_SEL] = &meson8b_l2_dram_clk_sel.hw,
2103 [CLKID_L2_DRAM] = &meson8b_l2_dram_clk_gate.hw,
2104 [CLKID_HDMI_PLL_LVDS_OUT] = &meson8b_hdmi_pll_lvds_out.hw,
2105 [CLKID_HDMI_PLL_HDMI_OUT] = &meson8b_hdmi_pll_hdmi_out.hw,
2106 [CLKID_VID_PLL_IN_SEL] = &meson8b_vid_pll_in_sel.hw,
2107 [CLKID_VID_PLL_IN_EN] = &meson8b_vid_pll_in_en.hw,
2108 [CLKID_VID_PLL_PRE_DIV] = &meson8b_vid_pll_pre_div.hw,
2109 [CLKID_VID_PLL_POST_DIV] = &meson8b_vid_pll_post_div.hw,
2110 [CLKID_VID_PLL_FINAL_DIV] = &meson8b_vid_pll_final_div.hw,
2111 [CLKID_VCLK_IN_SEL] = &meson8b_vclk_in_sel.hw,
2112 [CLKID_VCLK_IN_EN] = &meson8b_vclk_in_en.hw,
2113 [CLKID_VCLK_DIV1] = &meson8b_vclk_div1_gate.hw,
2114 [CLKID_VCLK_DIV2_DIV] = &meson8b_vclk_div2_div.hw,
2115 [CLKID_VCLK_DIV2] = &meson8b_vclk_div2_div_gate.hw,
2116 [CLKID_VCLK_DIV4_DIV] = &meson8b_vclk_div4_div.hw,
2117 [CLKID_VCLK_DIV4] = &meson8b_vclk_div4_div_gate.hw,
2118 [CLKID_VCLK_DIV6_DIV] = &meson8b_vclk_div6_div.hw,
2119 [CLKID_VCLK_DIV6] = &meson8b_vclk_div6_div_gate.hw,
2120 [CLKID_VCLK_DIV12_DIV] = &meson8b_vclk_div12_div.hw,
2121 [CLKID_VCLK_DIV12] = &meson8b_vclk_div12_div_gate.hw,
2122 [CLKID_VCLK2_IN_SEL] = &meson8b_vclk2_in_sel.hw,
2123 [CLKID_VCLK2_IN_EN] = &meson8b_vclk2_clk_in_en.hw,
2124 [CLKID_VCLK2_DIV1] = &meson8b_vclk2_div1_gate.hw,
2125 [CLKID_VCLK2_DIV2_DIV] = &meson8b_vclk2_div2_div.hw,
2126 [CLKID_VCLK2_DIV2] = &meson8b_vclk2_div2_div_gate.hw,
2127 [CLKID_VCLK2_DIV4_DIV] = &meson8b_vclk2_div4_div.hw,
2128 [CLKID_VCLK2_DIV4] = &meson8b_vclk2_div4_div_gate.hw,
2129 [CLKID_VCLK2_DIV6_DIV] = &meson8b_vclk2_div6_div.hw,
2130 [CLKID_VCLK2_DIV6] = &meson8b_vclk2_div6_div_gate.hw,
2131 [CLKID_VCLK2_DIV12_DIV] = &meson8b_vclk2_div12_div.hw,
2132 [CLKID_VCLK2_DIV12] = &meson8b_vclk2_div12_div_gate.hw,
2133 [CLKID_CTS_ENCT_SEL] = &meson8b_cts_enct_sel.hw,
2134 [CLKID_CTS_ENCT] = &meson8b_cts_enct.hw,
2135 [CLKID_CTS_ENCP_SEL] = &meson8b_cts_encp_sel.hw,
2136 [CLKID_CTS_ENCP] = &meson8b_cts_encp.hw,
2137 [CLKID_CTS_ENCI_SEL] = &meson8b_cts_enci_sel.hw,
2138 [CLKID_CTS_ENCI] = &meson8b_cts_enci.hw,
2139 [CLKID_HDMI_TX_PIXEL_SEL] = &meson8b_hdmi_tx_pixel_sel.hw,
2140 [CLKID_HDMI_TX_PIXEL] = &meson8b_hdmi_tx_pixel.hw,
2141 [CLKID_CTS_ENCL_SEL] = &meson8b_cts_encl_sel.hw,
2142 [CLKID_CTS_ENCL] = &meson8b_cts_encl.hw,
2143 [CLKID_CTS_VDAC0_SEL] = &meson8b_cts_vdac0_sel.hw,
2144 [CLKID_CTS_VDAC0] = &meson8b_cts_vdac0.hw,
2145 [CLKID_HDMI_SYS_SEL] = &meson8b_hdmi_sys_sel.hw,
2146 [CLKID_HDMI_SYS_DIV] = &meson8b_hdmi_sys_div.hw,
2147 [CLKID_HDMI_SYS] = &meson8b_hdmi_sys.hw,
2148 [CLKID_MALI_0_SEL] = &meson8b_mali_0_sel.hw,
2149 [CLKID_MALI_0_DIV] = &meson8b_mali_0_div.hw,
2150 [CLKID_MALI_0] = &meson8b_mali_0.hw,
2151 [CLKID_MALI_1_SEL] = &meson8b_mali_1_sel.hw,
2152 [CLKID_MALI_1_DIV] = &meson8b_mali_1_div.hw,
2153 [CLKID_MALI_1] = &meson8b_mali_1.hw,
2154 [CLKID_MALI] = &meson8b_mali.hw,
2155 [CLK_NR_CLKS] = NULL,
2160 static struct clk_regmap *const meson8b_clk_regmaps[] = {
2170 &meson8b_smart_card,
2175 &meson8b_async_fifo,
2179 &meson8b_assist_misc,
2190 &meson8b_mixer_iface,
2200 &meson8b_dos_parser,
2206 &meson8b_ahb_data_bus,
2207 &meson8b_ahb_ctrl_bus,
2208 &meson8b_hdmi_intr_sync,
2210 &meson8b_usb1_ddr_bridge,
2211 &meson8b_usb0_ddr_bridge,
2217 &meson8b_sec_ahb_ahb3_bridge,
2219 &meson8b_vclk2_venci0,
2220 &meson8b_vclk2_venci1,
2221 &meson8b_vclk2_vencp0,
2222 &meson8b_vclk2_vencp1,
2223 &meson8b_gclk_venci_int,
2224 &meson8b_gclk_vencp_int,
2226 &meson8b_aoclk_gate,
2227 &meson8b_iec958_gate,
2230 &meson8b_gclk_vencl_int,
2231 &meson8b_vclk2_venclmcc,
2232 &meson8b_vclk2_vencl,
2233 &meson8b_vclk2_other,
2235 &meson8b_ao_media_cpu,
2236 &meson8b_ao_ahb_sram,
2237 &meson8b_ao_ahb_bus,
2239 &meson8b_mpeg_clk_div,
2240 &meson8b_mpeg_clk_sel,
2249 &meson8b_cpu_in_sel,
2250 &meson8b_cpu_scale_div,
2251 &meson8b_cpu_scale_out_sel,
2253 &meson8b_mpll_prediv,
2259 &meson8b_nand_clk_sel,
2260 &meson8b_nand_clk_div,
2261 &meson8b_nand_clk_gate,
2262 &meson8b_fixed_pll_dco,
2263 &meson8b_hdmi_pll_dco,
2264 &meson8b_sys_pll_dco,
2265 &meson8b_apb_clk_sel,
2266 &meson8b_apb_clk_gate,
2267 &meson8b_periph_clk_sel,
2268 &meson8b_periph_clk_gate,
2269 &meson8b_axi_clk_sel,
2270 &meson8b_axi_clk_gate,
2271 &meson8b_l2_dram_clk_sel,
2272 &meson8b_l2_dram_clk_gate,
2273 &meson8b_hdmi_pll_lvds_out,
2274 &meson8b_hdmi_pll_hdmi_out,
2275 &meson8b_vid_pll_in_sel,
2276 &meson8b_vid_pll_in_en,
2277 &meson8b_vid_pll_pre_div,
2278 &meson8b_vid_pll_post_div,
2280 &meson8b_vid_pll_final_div,
2281 &meson8b_vclk_in_sel,
2282 &meson8b_vclk_in_en,
2283 &meson8b_vclk_div1_gate,
2284 &meson8b_vclk_div2_div_gate,
2285 &meson8b_vclk_div4_div_gate,
2286 &meson8b_vclk_div6_div_gate,
2287 &meson8b_vclk_div12_div_gate,
2288 &meson8b_vclk2_in_sel,
2289 &meson8b_vclk2_clk_in_en,
2290 &meson8b_vclk2_div1_gate,
2291 &meson8b_vclk2_div2_div_gate,
2292 &meson8b_vclk2_div4_div_gate,
2293 &meson8b_vclk2_div6_div_gate,
2294 &meson8b_vclk2_div12_div_gate,
2295 &meson8b_cts_enct_sel,
2297 &meson8b_cts_encp_sel,
2299 &meson8b_cts_enci_sel,
2301 &meson8b_hdmi_tx_pixel_sel,
2302 &meson8b_hdmi_tx_pixel,
2303 &meson8b_cts_encl_sel,
2305 &meson8b_cts_vdac0_sel,
2307 &meson8b_hdmi_sys_sel,
2308 &meson8b_hdmi_sys_div,
2310 &meson8b_mali_0_sel,
2311 &meson8b_mali_0_div,
2313 &meson8b_mali_1_sel,
2314 &meson8b_mali_1_div,
2319 static const struct meson8b_clk_reset_line {
2322 } meson8b_clk_reset_bits[] = {
2323 [CLKC_RESET_L2_CACHE_SOFT_RESET] = {
2324 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 30
2326 [CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET] = {
2327 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 29
2329 [CLKC_RESET_SCU_SOFT_RESET] = {
2330 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 28
2332 [CLKC_RESET_CPU3_SOFT_RESET] = {
2333 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 27
2335 [CLKC_RESET_CPU2_SOFT_RESET] = {
2336 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 26
2338 [CLKC_RESET_CPU1_SOFT_RESET] = {
2339 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 25
2341 [CLKC_RESET_CPU0_SOFT_RESET] = {
2342 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 24
2344 [CLKC_RESET_A5_GLOBAL_RESET] = {
2345 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 18
2347 [CLKC_RESET_A5_AXI_SOFT_RESET] = {
2348 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 17
2350 [CLKC_RESET_A5_ABP_SOFT_RESET] = {
2351 .reg = HHI_SYS_CPU_CLK_CNTL0, .bit_idx = 16
2353 [CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET] = {
2354 .reg = HHI_SYS_CPU_CLK_CNTL1, .bit_idx = 30
2356 [CLKC_RESET_VID_CLK_CNTL_SOFT_RESET] = {
2357 .reg = HHI_VID_CLK_CNTL, .bit_idx = 15
2359 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST] = {
2360 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 7
2362 [CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE] = {
2363 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 3
2365 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST] = {
2366 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 1
2368 [CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE] = {
2369 .reg = HHI_VID_DIVIDER_CNTL, .bit_idx = 0
2373 static int meson8b_clk_reset_update(struct reset_controller_dev *rcdev,
2374 unsigned long id, bool assert)
2376 struct meson8b_clk_reset *meson8b_clk_reset =
2377 container_of(rcdev, struct meson8b_clk_reset, reset);
2378 unsigned long flags;
2379 const struct meson8b_clk_reset_line *reset;
2381 if (id >= ARRAY_SIZE(meson8b_clk_reset_bits))
2384 reset = &meson8b_clk_reset_bits[id];
2386 spin_lock_irqsave(&meson_clk_lock, flags);
2389 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
2390 BIT(reset->bit_idx), BIT(reset->bit_idx));
2392 regmap_update_bits(meson8b_clk_reset->regmap, reset->reg,
2393 BIT(reset->bit_idx), 0);
2395 spin_unlock_irqrestore(&meson_clk_lock, flags);
2400 static int meson8b_clk_reset_assert(struct reset_controller_dev *rcdev,
2403 return meson8b_clk_reset_update(rcdev, id, true);
2406 static int meson8b_clk_reset_deassert(struct reset_controller_dev *rcdev,
2409 return meson8b_clk_reset_update(rcdev, id, false);
2412 static const struct reset_control_ops meson8b_clk_reset_ops = {
2413 .assert = meson8b_clk_reset_assert,
2414 .deassert = meson8b_clk_reset_deassert,
2417 struct meson8b_nb_data {
2418 struct notifier_block nb;
2419 struct clk_hw_onecell_data *onecell_data;
2422 static int meson8b_cpu_clk_notifier_cb(struct notifier_block *nb,
2423 unsigned long event, void *data)
2425 struct meson8b_nb_data *nb_data =
2426 container_of(nb, struct meson8b_nb_data, nb);
2427 struct clk_hw **hws = nb_data->onecell_data->hws;
2428 struct clk_hw *cpu_clk_hw, *parent_clk_hw;
2429 struct clk *cpu_clk, *parent_clk;
2433 case PRE_RATE_CHANGE:
2434 parent_clk_hw = hws[CLKID_XTAL];
2437 case POST_RATE_CHANGE:
2438 parent_clk_hw = hws[CLKID_CPU_SCALE_OUT_SEL];
2445 cpu_clk_hw = hws[CLKID_CPUCLK];
2446 cpu_clk = __clk_lookup(clk_hw_get_name(cpu_clk_hw));
2448 parent_clk = __clk_lookup(clk_hw_get_name(parent_clk_hw));
2450 ret = clk_set_parent(cpu_clk, parent_clk);
2452 return notifier_from_errno(ret);
2459 static struct meson8b_nb_data meson8b_cpu_nb_data = {
2460 .nb.notifier_call = meson8b_cpu_clk_notifier_cb,
2463 static const struct regmap_config clkc_regmap_config = {
2469 static void __init meson8b_clkc_init_common(struct device_node *np,
2470 struct clk_hw_onecell_data *clk_hw_onecell_data)
2472 struct meson8b_clk_reset *rstc;
2473 const char *notifier_clk_name;
2474 struct clk *notifier_clk;
2475 void __iomem *clk_base;
2479 map = syscon_node_to_regmap(of_get_parent(np));
2481 pr_info("failed to get HHI regmap - Trying obsolete regs\n");
2483 /* Generic clocks, PLLs and some of the reset-bits */
2484 clk_base = of_iomap(np, 1);
2486 pr_err("%s: Unable to map clk base\n", __func__);
2490 map = regmap_init_mmio(NULL, clk_base, &clkc_regmap_config);
2495 rstc = kzalloc(sizeof(*rstc), GFP_KERNEL);
2499 /* Reset Controller */
2501 rstc->reset.ops = &meson8b_clk_reset_ops;
2502 rstc->reset.nr_resets = ARRAY_SIZE(meson8b_clk_reset_bits);
2503 rstc->reset.of_node = np;
2504 ret = reset_controller_register(&rstc->reset);
2506 pr_err("%s: Failed to register clkc reset controller: %d\n",
2511 /* Populate regmap for the regmap backed clocks */
2512 for (i = 0; i < ARRAY_SIZE(meson8b_clk_regmaps); i++)
2513 meson8b_clk_regmaps[i]->map = map;
2517 * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
2519 for (i = CLKID_XTAL; i < CLK_NR_CLKS; i++) {
2520 /* array might be sparse */
2521 if (!clk_hw_onecell_data->hws[i])
2524 ret = clk_hw_register(NULL, clk_hw_onecell_data->hws[i]);
2529 meson8b_cpu_nb_data.onecell_data = clk_hw_onecell_data;
2532 * FIXME we shouldn't program the muxes in notifier handlers. The
2533 * tricky programming sequence will be handled by the forthcoming
2534 * coordinated clock rates mechanism once that feature is released.
2536 notifier_clk_name = clk_hw_get_name(&meson8b_cpu_scale_out_sel.hw);
2537 notifier_clk = __clk_lookup(notifier_clk_name);
2538 ret = clk_notifier_register(notifier_clk, &meson8b_cpu_nb_data.nb);
2540 pr_err("%s: failed to register the CPU clock notifier\n",
2545 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
2546 clk_hw_onecell_data);
2548 pr_err("%s: failed to register clock provider\n", __func__);
2551 static void __init meson8_clkc_init(struct device_node *np)
2553 return meson8b_clkc_init_common(np, &meson8_hw_onecell_data);
2556 static void __init meson8b_clkc_init(struct device_node *np)
2558 return meson8b_clkc_init_common(np, &meson8b_hw_onecell_data);
2561 CLK_OF_DECLARE_DRIVER(meson8_clkc, "amlogic,meson8-clkc",
2563 CLK_OF_DECLARE_DRIVER(meson8b_clkc, "amlogic,meson8b-clkc",
2565 CLK_OF_DECLARE_DRIVER(meson8m2_clkc, "amlogic,meson8m2-clkc",