1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
8 #include <linux/clk-provider.h>
9 #include <linux/init.h>
10 #include <linux/of_device.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/platform_device.h>
13 #include <linux/regmap.h>
17 #include "clk-regmap.h"
19 static DEFINE_SPINLOCK(meson_clk_lock);
21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
85 static struct clk_regmap gxbb_fixed_pll_dco = {
86 .data = &(struct meson_clk_pll_data){
88 .reg_off = HHI_MPLL_CNTL,
93 .reg_off = HHI_MPLL_CNTL,
98 .reg_off = HHI_MPLL_CNTL,
103 .reg_off = HHI_MPLL_CNTL2,
108 .reg_off = HHI_MPLL_CNTL,
113 .reg_off = HHI_MPLL_CNTL,
118 .hw.init = &(struct clk_init_data){
119 .name = "fixed_pll_dco",
120 .ops = &meson_clk_pll_ro_ops,
121 .parent_names = (const char *[]){ "xtal" },
126 static struct clk_regmap gxbb_fixed_pll = {
127 .data = &(struct clk_regmap_div_data){
128 .offset = HHI_MPLL_CNTL,
131 .flags = CLK_DIVIDER_POWER_OF_TWO,
133 .hw.init = &(struct clk_init_data){
135 .ops = &clk_regmap_divider_ro_ops,
136 .parent_names = (const char *[]){ "fixed_pll_dco" },
139 * This clock won't ever change at runtime so
140 * CLK_SET_RATE_PARENT is not required
145 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
148 .hw.init = &(struct clk_init_data){
149 .name = "hdmi_pll_pre_mult",
150 .ops = &clk_fixed_factor_ops,
151 .parent_names = (const char *[]){ "xtal" },
156 static struct clk_regmap gxbb_hdmi_pll_dco = {
157 .data = &(struct meson_clk_pll_data){
159 .reg_off = HHI_HDMI_PLL_CNTL,
164 .reg_off = HHI_HDMI_PLL_CNTL,
169 .reg_off = HHI_HDMI_PLL_CNTL,
174 .reg_off = HHI_HDMI_PLL_CNTL2,
179 .reg_off = HHI_HDMI_PLL_CNTL,
184 .reg_off = HHI_HDMI_PLL_CNTL,
189 .hw.init = &(struct clk_init_data){
190 .name = "hdmi_pll_dco",
191 .ops = &meson_clk_pll_ro_ops,
192 .parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
195 * Display directly handle hdmi pll registers ATM, we need
196 * NOCACHE to keep our view of the clock as accurate as possible
198 .flags = CLK_GET_RATE_NOCACHE,
202 static struct clk_regmap gxl_hdmi_pll_dco = {
203 .data = &(struct meson_clk_pll_data){
205 .reg_off = HHI_HDMI_PLL_CNTL,
210 .reg_off = HHI_HDMI_PLL_CNTL,
215 .reg_off = HHI_HDMI_PLL_CNTL,
220 * On gxl, there is a register shift due to
221 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
222 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
223 * instead which is defined at the same offset.
226 .reg_off = HHI_HDMI_PLL_CNTL2,
231 .reg_off = HHI_HDMI_PLL_CNTL,
236 .reg_off = HHI_HDMI_PLL_CNTL,
241 .hw.init = &(struct clk_init_data){
242 .name = "hdmi_pll_dco",
243 .ops = &meson_clk_pll_ro_ops,
244 .parent_names = (const char *[]){ "xtal" },
247 * Display directly handle hdmi pll registers ATM, we need
248 * NOCACHE to keep our view of the clock as accurate as possible
250 .flags = CLK_GET_RATE_NOCACHE,
254 static struct clk_regmap gxbb_hdmi_pll_od = {
255 .data = &(struct clk_regmap_div_data){
256 .offset = HHI_HDMI_PLL_CNTL2,
259 .flags = CLK_DIVIDER_POWER_OF_TWO,
261 .hw.init = &(struct clk_init_data){
262 .name = "hdmi_pll_od",
263 .ops = &clk_regmap_divider_ro_ops,
264 .parent_names = (const char *[]){ "hdmi_pll_dco" },
266 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
270 static struct clk_regmap gxbb_hdmi_pll_od2 = {
271 .data = &(struct clk_regmap_div_data){
272 .offset = HHI_HDMI_PLL_CNTL2,
275 .flags = CLK_DIVIDER_POWER_OF_TWO,
277 .hw.init = &(struct clk_init_data){
278 .name = "hdmi_pll_od2",
279 .ops = &clk_regmap_divider_ro_ops,
280 .parent_names = (const char *[]){ "hdmi_pll_od" },
282 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
286 static struct clk_regmap gxbb_hdmi_pll = {
287 .data = &(struct clk_regmap_div_data){
288 .offset = HHI_HDMI_PLL_CNTL2,
291 .flags = CLK_DIVIDER_POWER_OF_TWO,
293 .hw.init = &(struct clk_init_data){
295 .ops = &clk_regmap_divider_ro_ops,
296 .parent_names = (const char *[]){ "hdmi_pll_od2" },
298 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
302 static struct clk_regmap gxl_hdmi_pll_od = {
303 .data = &(struct clk_regmap_div_data){
304 .offset = HHI_HDMI_PLL_CNTL + 8,
307 .flags = CLK_DIVIDER_POWER_OF_TWO,
309 .hw.init = &(struct clk_init_data){
310 .name = "hdmi_pll_od",
311 .ops = &clk_regmap_divider_ro_ops,
312 .parent_names = (const char *[]){ "hdmi_pll_dco" },
314 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
318 static struct clk_regmap gxl_hdmi_pll_od2 = {
319 .data = &(struct clk_regmap_div_data){
320 .offset = HHI_HDMI_PLL_CNTL + 8,
323 .flags = CLK_DIVIDER_POWER_OF_TWO,
325 .hw.init = &(struct clk_init_data){
326 .name = "hdmi_pll_od2",
327 .ops = &clk_regmap_divider_ro_ops,
328 .parent_names = (const char *[]){ "hdmi_pll_od" },
330 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
334 static struct clk_regmap gxl_hdmi_pll = {
335 .data = &(struct clk_regmap_div_data){
336 .offset = HHI_HDMI_PLL_CNTL + 8,
339 .flags = CLK_DIVIDER_POWER_OF_TWO,
341 .hw.init = &(struct clk_init_data){
343 .ops = &clk_regmap_divider_ro_ops,
344 .parent_names = (const char *[]){ "hdmi_pll_od2" },
346 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
350 static struct clk_regmap gxbb_sys_pll_dco = {
351 .data = &(struct meson_clk_pll_data){
353 .reg_off = HHI_SYS_PLL_CNTL,
358 .reg_off = HHI_SYS_PLL_CNTL,
363 .reg_off = HHI_SYS_PLL_CNTL,
368 .reg_off = HHI_SYS_PLL_CNTL,
373 .reg_off = HHI_SYS_PLL_CNTL,
378 .hw.init = &(struct clk_init_data){
379 .name = "sys_pll_dco",
380 .ops = &meson_clk_pll_ro_ops,
381 .parent_names = (const char *[]){ "xtal" },
386 static struct clk_regmap gxbb_sys_pll = {
387 .data = &(struct clk_regmap_div_data){
388 .offset = HHI_SYS_PLL_CNTL,
391 .flags = CLK_DIVIDER_POWER_OF_TWO,
393 .hw.init = &(struct clk_init_data){
395 .ops = &clk_regmap_divider_ro_ops,
396 .parent_names = (const char *[]){ "sys_pll_dco" },
398 .flags = CLK_SET_RATE_PARENT,
402 static const struct reg_sequence gxbb_gp0_init_regs[] = {
403 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
404 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
405 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
408 static struct clk_regmap gxbb_gp0_pll_dco = {
409 .data = &(struct meson_clk_pll_data){
411 .reg_off = HHI_GP0_PLL_CNTL,
416 .reg_off = HHI_GP0_PLL_CNTL,
421 .reg_off = HHI_GP0_PLL_CNTL,
426 .reg_off = HHI_GP0_PLL_CNTL,
431 .reg_off = HHI_GP0_PLL_CNTL,
435 .table = gxbb_gp0_pll_params_table,
436 .init_regs = gxbb_gp0_init_regs,
437 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
439 .hw.init = &(struct clk_init_data){
440 .name = "gp0_pll_dco",
441 .ops = &meson_clk_pll_ops,
442 .parent_names = (const char *[]){ "xtal" },
447 static const struct reg_sequence gxl_gp0_init_regs[] = {
448 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
449 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
450 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
451 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
452 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
455 static struct clk_regmap gxl_gp0_pll_dco = {
456 .data = &(struct meson_clk_pll_data){
458 .reg_off = HHI_GP0_PLL_CNTL,
463 .reg_off = HHI_GP0_PLL_CNTL,
468 .reg_off = HHI_GP0_PLL_CNTL,
473 .reg_off = HHI_GP0_PLL_CNTL1,
478 .reg_off = HHI_GP0_PLL_CNTL,
483 .reg_off = HHI_GP0_PLL_CNTL,
487 .table = gxl_gp0_pll_params_table,
488 .init_regs = gxl_gp0_init_regs,
489 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
491 .hw.init = &(struct clk_init_data){
492 .name = "gp0_pll_dco",
493 .ops = &meson_clk_pll_ops,
494 .parent_names = (const char *[]){ "xtal" },
499 static struct clk_regmap gxbb_gp0_pll = {
500 .data = &(struct clk_regmap_div_data){
501 .offset = HHI_GP0_PLL_CNTL,
504 .flags = CLK_DIVIDER_POWER_OF_TWO,
506 .hw.init = &(struct clk_init_data){
508 .ops = &clk_regmap_divider_ops,
509 .parent_names = (const char *[]){ "gp0_pll_dco" },
511 .flags = CLK_SET_RATE_PARENT,
515 static struct clk_fixed_factor gxbb_fclk_div2_div = {
518 .hw.init = &(struct clk_init_data){
519 .name = "fclk_div2_div",
520 .ops = &clk_fixed_factor_ops,
521 .parent_names = (const char *[]){ "fixed_pll" },
526 static struct clk_regmap gxbb_fclk_div2 = {
527 .data = &(struct clk_regmap_gate_data){
528 .offset = HHI_MPLL_CNTL6,
531 .hw.init = &(struct clk_init_data){
533 .ops = &clk_regmap_gate_ops,
534 .parent_names = (const char *[]){ "fclk_div2_div" },
536 .flags = CLK_IS_CRITICAL,
540 static struct clk_fixed_factor gxbb_fclk_div3_div = {
543 .hw.init = &(struct clk_init_data){
544 .name = "fclk_div3_div",
545 .ops = &clk_fixed_factor_ops,
546 .parent_names = (const char *[]){ "fixed_pll" },
551 static struct clk_regmap gxbb_fclk_div3 = {
552 .data = &(struct clk_regmap_gate_data){
553 .offset = HHI_MPLL_CNTL6,
556 .hw.init = &(struct clk_init_data){
558 .ops = &clk_regmap_gate_ops,
559 .parent_names = (const char *[]){ "fclk_div3_div" },
563 * This clock, as fdiv2, is used by the SCPI FW and is required
564 * by the platform to operate correctly.
565 * Until the following condition are met, we need this clock to
566 * be marked as critical:
567 * a) The SCPI generic driver claims and enable all the clocks
569 * b) CCF has a clock hand-off mechanism to make the sure the
570 * clock stays on until the proper driver comes along
572 .flags = CLK_IS_CRITICAL,
576 static struct clk_fixed_factor gxbb_fclk_div4_div = {
579 .hw.init = &(struct clk_init_data){
580 .name = "fclk_div4_div",
581 .ops = &clk_fixed_factor_ops,
582 .parent_names = (const char *[]){ "fixed_pll" },
587 static struct clk_regmap gxbb_fclk_div4 = {
588 .data = &(struct clk_regmap_gate_data){
589 .offset = HHI_MPLL_CNTL6,
592 .hw.init = &(struct clk_init_data){
594 .ops = &clk_regmap_gate_ops,
595 .parent_names = (const char *[]){ "fclk_div4_div" },
600 static struct clk_fixed_factor gxbb_fclk_div5_div = {
603 .hw.init = &(struct clk_init_data){
604 .name = "fclk_div5_div",
605 .ops = &clk_fixed_factor_ops,
606 .parent_names = (const char *[]){ "fixed_pll" },
611 static struct clk_regmap gxbb_fclk_div5 = {
612 .data = &(struct clk_regmap_gate_data){
613 .offset = HHI_MPLL_CNTL6,
616 .hw.init = &(struct clk_init_data){
618 .ops = &clk_regmap_gate_ops,
619 .parent_names = (const char *[]){ "fclk_div5_div" },
624 static struct clk_fixed_factor gxbb_fclk_div7_div = {
627 .hw.init = &(struct clk_init_data){
628 .name = "fclk_div7_div",
629 .ops = &clk_fixed_factor_ops,
630 .parent_names = (const char *[]){ "fixed_pll" },
635 static struct clk_regmap gxbb_fclk_div7 = {
636 .data = &(struct clk_regmap_gate_data){
637 .offset = HHI_MPLL_CNTL6,
640 .hw.init = &(struct clk_init_data){
642 .ops = &clk_regmap_gate_ops,
643 .parent_names = (const char *[]){ "fclk_div7_div" },
648 static struct clk_regmap gxbb_mpll_prediv = {
649 .data = &(struct clk_regmap_div_data){
650 .offset = HHI_MPLL_CNTL5,
654 .hw.init = &(struct clk_init_data){
655 .name = "mpll_prediv",
656 .ops = &clk_regmap_divider_ro_ops,
657 .parent_names = (const char *[]){ "fixed_pll" },
662 static struct clk_regmap gxbb_mpll0_div = {
663 .data = &(struct meson_clk_mpll_data){
665 .reg_off = HHI_MPLL_CNTL7,
670 .reg_off = HHI_MPLL_CNTL7,
675 .reg_off = HHI_MPLL_CNTL7,
680 .reg_off = HHI_MPLL_CNTL,
684 .lock = &meson_clk_lock,
686 .hw.init = &(struct clk_init_data){
688 .ops = &meson_clk_mpll_ops,
689 .parent_names = (const char *[]){ "mpll_prediv" },
694 static struct clk_regmap gxbb_mpll0 = {
695 .data = &(struct clk_regmap_gate_data){
696 .offset = HHI_MPLL_CNTL7,
699 .hw.init = &(struct clk_init_data){
701 .ops = &clk_regmap_gate_ops,
702 .parent_names = (const char *[]){ "mpll0_div" },
704 .flags = CLK_SET_RATE_PARENT,
708 static struct clk_regmap gxbb_mpll1_div = {
709 .data = &(struct meson_clk_mpll_data){
711 .reg_off = HHI_MPLL_CNTL8,
716 .reg_off = HHI_MPLL_CNTL8,
721 .reg_off = HHI_MPLL_CNTL8,
725 .lock = &meson_clk_lock,
727 .hw.init = &(struct clk_init_data){
729 .ops = &meson_clk_mpll_ops,
730 .parent_names = (const char *[]){ "mpll_prediv" },
735 static struct clk_regmap gxbb_mpll1 = {
736 .data = &(struct clk_regmap_gate_data){
737 .offset = HHI_MPLL_CNTL8,
740 .hw.init = &(struct clk_init_data){
742 .ops = &clk_regmap_gate_ops,
743 .parent_names = (const char *[]){ "mpll1_div" },
745 .flags = CLK_SET_RATE_PARENT,
749 static struct clk_regmap gxbb_mpll2_div = {
750 .data = &(struct meson_clk_mpll_data){
752 .reg_off = HHI_MPLL_CNTL9,
757 .reg_off = HHI_MPLL_CNTL9,
762 .reg_off = HHI_MPLL_CNTL9,
766 .lock = &meson_clk_lock,
768 .hw.init = &(struct clk_init_data){
770 .ops = &meson_clk_mpll_ops,
771 .parent_names = (const char *[]){ "mpll_prediv" },
776 static struct clk_regmap gxbb_mpll2 = {
777 .data = &(struct clk_regmap_gate_data){
778 .offset = HHI_MPLL_CNTL9,
781 .hw.init = &(struct clk_init_data){
783 .ops = &clk_regmap_gate_ops,
784 .parent_names = (const char *[]){ "mpll2_div" },
786 .flags = CLK_SET_RATE_PARENT,
790 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
791 static const char * const clk81_parent_names[] = {
792 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
793 "fclk_div3", "fclk_div5"
796 static struct clk_regmap gxbb_mpeg_clk_sel = {
797 .data = &(struct clk_regmap_mux_data){
798 .offset = HHI_MPEG_CLK_CNTL,
801 .table = mux_table_clk81,
803 .hw.init = &(struct clk_init_data){
804 .name = "mpeg_clk_sel",
805 .ops = &clk_regmap_mux_ro_ops,
807 * bits 14:12 selects from 8 possible parents:
808 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
809 * fclk_div4, fclk_div3, fclk_div5
811 .parent_names = clk81_parent_names,
812 .num_parents = ARRAY_SIZE(clk81_parent_names),
816 static struct clk_regmap gxbb_mpeg_clk_div = {
817 .data = &(struct clk_regmap_div_data){
818 .offset = HHI_MPEG_CLK_CNTL,
822 .hw.init = &(struct clk_init_data){
823 .name = "mpeg_clk_div",
824 .ops = &clk_regmap_divider_ro_ops,
825 .parent_names = (const char *[]){ "mpeg_clk_sel" },
830 /* the mother of dragons gates */
831 static struct clk_regmap gxbb_clk81 = {
832 .data = &(struct clk_regmap_gate_data){
833 .offset = HHI_MPEG_CLK_CNTL,
836 .hw.init = &(struct clk_init_data){
838 .ops = &clk_regmap_gate_ops,
839 .parent_names = (const char *[]){ "mpeg_clk_div" },
841 .flags = CLK_IS_CRITICAL,
845 static struct clk_regmap gxbb_sar_adc_clk_sel = {
846 .data = &(struct clk_regmap_mux_data){
847 .offset = HHI_SAR_CLK_CNTL,
851 .hw.init = &(struct clk_init_data){
852 .name = "sar_adc_clk_sel",
853 .ops = &clk_regmap_mux_ops,
854 /* NOTE: The datasheet doesn't list the parents for bit 10 */
855 .parent_names = (const char *[]){ "xtal", "clk81", },
860 static struct clk_regmap gxbb_sar_adc_clk_div = {
861 .data = &(struct clk_regmap_div_data){
862 .offset = HHI_SAR_CLK_CNTL,
866 .hw.init = &(struct clk_init_data){
867 .name = "sar_adc_clk_div",
868 .ops = &clk_regmap_divider_ops,
869 .parent_names = (const char *[]){ "sar_adc_clk_sel" },
874 static struct clk_regmap gxbb_sar_adc_clk = {
875 .data = &(struct clk_regmap_gate_data){
876 .offset = HHI_SAR_CLK_CNTL,
879 .hw.init = &(struct clk_init_data){
880 .name = "sar_adc_clk",
881 .ops = &clk_regmap_gate_ops,
882 .parent_names = (const char *[]){ "sar_adc_clk_div" },
884 .flags = CLK_SET_RATE_PARENT,
889 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
890 * muxed by a glitch-free switch.
893 static const char * const gxbb_mali_0_1_parent_names[] = {
894 "xtal", "gp0_pll", "mpll2", "mpll1", "fclk_div7",
895 "fclk_div4", "fclk_div3", "fclk_div5"
898 static struct clk_regmap gxbb_mali_0_sel = {
899 .data = &(struct clk_regmap_mux_data){
900 .offset = HHI_MALI_CLK_CNTL,
904 .hw.init = &(struct clk_init_data){
905 .name = "mali_0_sel",
906 .ops = &clk_regmap_mux_ops,
908 * bits 10:9 selects from 8 possible parents:
909 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
910 * fclk_div4, fclk_div3, fclk_div5
912 .parent_names = gxbb_mali_0_1_parent_names,
914 .flags = CLK_SET_RATE_NO_REPARENT,
918 static struct clk_regmap gxbb_mali_0_div = {
919 .data = &(struct clk_regmap_div_data){
920 .offset = HHI_MALI_CLK_CNTL,
924 .hw.init = &(struct clk_init_data){
925 .name = "mali_0_div",
926 .ops = &clk_regmap_divider_ops,
927 .parent_names = (const char *[]){ "mali_0_sel" },
929 .flags = CLK_SET_RATE_NO_REPARENT,
933 static struct clk_regmap gxbb_mali_0 = {
934 .data = &(struct clk_regmap_gate_data){
935 .offset = HHI_MALI_CLK_CNTL,
938 .hw.init = &(struct clk_init_data){
940 .ops = &clk_regmap_gate_ops,
941 .parent_names = (const char *[]){ "mali_0_div" },
943 .flags = CLK_SET_RATE_PARENT,
947 static struct clk_regmap gxbb_mali_1_sel = {
948 .data = &(struct clk_regmap_mux_data){
949 .offset = HHI_MALI_CLK_CNTL,
953 .hw.init = &(struct clk_init_data){
954 .name = "mali_1_sel",
955 .ops = &clk_regmap_mux_ops,
957 * bits 10:9 selects from 8 possible parents:
958 * xtal, gp0_pll, mpll2, mpll1, fclk_div7,
959 * fclk_div4, fclk_div3, fclk_div5
961 .parent_names = gxbb_mali_0_1_parent_names,
963 .flags = CLK_SET_RATE_NO_REPARENT,
967 static struct clk_regmap gxbb_mali_1_div = {
968 .data = &(struct clk_regmap_div_data){
969 .offset = HHI_MALI_CLK_CNTL,
973 .hw.init = &(struct clk_init_data){
974 .name = "mali_1_div",
975 .ops = &clk_regmap_divider_ops,
976 .parent_names = (const char *[]){ "mali_1_sel" },
978 .flags = CLK_SET_RATE_NO_REPARENT,
982 static struct clk_regmap gxbb_mali_1 = {
983 .data = &(struct clk_regmap_gate_data){
984 .offset = HHI_MALI_CLK_CNTL,
987 .hw.init = &(struct clk_init_data){
989 .ops = &clk_regmap_gate_ops,
990 .parent_names = (const char *[]){ "mali_1_div" },
992 .flags = CLK_SET_RATE_PARENT,
996 static const char * const gxbb_mali_parent_names[] = {
1000 static struct clk_regmap gxbb_mali = {
1001 .data = &(struct clk_regmap_mux_data){
1002 .offset = HHI_MALI_CLK_CNTL,
1006 .hw.init = &(struct clk_init_data){
1008 .ops = &clk_regmap_mux_ops,
1009 .parent_names = gxbb_mali_parent_names,
1011 .flags = CLK_SET_RATE_NO_REPARENT,
1015 static struct clk_regmap gxbb_cts_amclk_sel = {
1016 .data = &(struct clk_regmap_mux_data){
1017 .offset = HHI_AUD_CLK_CNTL,
1020 .table = (u32[]){ 1, 2, 3 },
1021 .flags = CLK_MUX_ROUND_CLOSEST,
1023 .hw.init = &(struct clk_init_data){
1024 .name = "cts_amclk_sel",
1025 .ops = &clk_regmap_mux_ops,
1026 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1031 static struct clk_regmap gxbb_cts_amclk_div = {
1032 .data = &(struct clk_regmap_div_data) {
1033 .offset = HHI_AUD_CLK_CNTL,
1036 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1038 .hw.init = &(struct clk_init_data){
1039 .name = "cts_amclk_div",
1040 .ops = &clk_regmap_divider_ops,
1041 .parent_names = (const char *[]){ "cts_amclk_sel" },
1043 .flags = CLK_SET_RATE_PARENT,
1047 static struct clk_regmap gxbb_cts_amclk = {
1048 .data = &(struct clk_regmap_gate_data){
1049 .offset = HHI_AUD_CLK_CNTL,
1052 .hw.init = &(struct clk_init_data){
1053 .name = "cts_amclk",
1054 .ops = &clk_regmap_gate_ops,
1055 .parent_names = (const char *[]){ "cts_amclk_div" },
1057 .flags = CLK_SET_RATE_PARENT,
1061 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1062 .data = &(struct clk_regmap_mux_data){
1063 .offset = HHI_AUD_CLK_CNTL2,
1066 .table = (u32[]){ 1, 2, 3 },
1067 .flags = CLK_MUX_ROUND_CLOSEST,
1069 .hw.init = &(struct clk_init_data) {
1070 .name = "cts_mclk_i958_sel",
1071 .ops = &clk_regmap_mux_ops,
1072 .parent_names = (const char *[]){ "mpll0", "mpll1", "mpll2" },
1077 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1078 .data = &(struct clk_regmap_div_data){
1079 .offset = HHI_AUD_CLK_CNTL2,
1082 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1084 .hw.init = &(struct clk_init_data) {
1085 .name = "cts_mclk_i958_div",
1086 .ops = &clk_regmap_divider_ops,
1087 .parent_names = (const char *[]){ "cts_mclk_i958_sel" },
1089 .flags = CLK_SET_RATE_PARENT,
1093 static struct clk_regmap gxbb_cts_mclk_i958 = {
1094 .data = &(struct clk_regmap_gate_data){
1095 .offset = HHI_AUD_CLK_CNTL2,
1098 .hw.init = &(struct clk_init_data){
1099 .name = "cts_mclk_i958",
1100 .ops = &clk_regmap_gate_ops,
1101 .parent_names = (const char *[]){ "cts_mclk_i958_div" },
1103 .flags = CLK_SET_RATE_PARENT,
1107 static struct clk_regmap gxbb_cts_i958 = {
1108 .data = &(struct clk_regmap_mux_data){
1109 .offset = HHI_AUD_CLK_CNTL2,
1113 .hw.init = &(struct clk_init_data){
1115 .ops = &clk_regmap_mux_ops,
1116 .parent_names = (const char *[]){ "cts_amclk", "cts_mclk_i958" },
1119 *The parent is specific to origin of the audio data. Let the
1120 * consumer choose the appropriate parent
1122 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1126 static struct clk_regmap gxbb_32k_clk_div = {
1127 .data = &(struct clk_regmap_div_data){
1128 .offset = HHI_32K_CLK_CNTL,
1132 .hw.init = &(struct clk_init_data){
1133 .name = "32k_clk_div",
1134 .ops = &clk_regmap_divider_ops,
1135 .parent_names = (const char *[]){ "32k_clk_sel" },
1137 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1141 static struct clk_regmap gxbb_32k_clk = {
1142 .data = &(struct clk_regmap_gate_data){
1143 .offset = HHI_32K_CLK_CNTL,
1146 .hw.init = &(struct clk_init_data){
1148 .ops = &clk_regmap_gate_ops,
1149 .parent_names = (const char *[]){ "32k_clk_div" },
1151 .flags = CLK_SET_RATE_PARENT,
1155 static const char * const gxbb_32k_clk_parent_names[] = {
1156 "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
1159 static struct clk_regmap gxbb_32k_clk_sel = {
1160 .data = &(struct clk_regmap_mux_data){
1161 .offset = HHI_32K_CLK_CNTL,
1165 .hw.init = &(struct clk_init_data){
1166 .name = "32k_clk_sel",
1167 .ops = &clk_regmap_mux_ops,
1168 .parent_names = gxbb_32k_clk_parent_names,
1170 .flags = CLK_SET_RATE_PARENT,
1174 static const char * const gxbb_sd_emmc_clk0_parent_names[] = {
1175 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
1178 * Following these parent clocks, we should also have had mpll2, mpll3
1179 * and gp0_pll but these clocks are too precious to be used here. All
1180 * the necessary rates for MMC and NAND operation can be acheived using
1181 * xtal or fclk_div clocks
1186 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1187 .data = &(struct clk_regmap_mux_data){
1188 .offset = HHI_SD_EMMC_CLK_CNTL,
1192 .hw.init = &(struct clk_init_data) {
1193 .name = "sd_emmc_a_clk0_sel",
1194 .ops = &clk_regmap_mux_ops,
1195 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1196 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1197 .flags = CLK_SET_RATE_PARENT,
1201 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1202 .data = &(struct clk_regmap_div_data){
1203 .offset = HHI_SD_EMMC_CLK_CNTL,
1206 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1208 .hw.init = &(struct clk_init_data) {
1209 .name = "sd_emmc_a_clk0_div",
1210 .ops = &clk_regmap_divider_ops,
1211 .parent_names = (const char *[]){ "sd_emmc_a_clk0_sel" },
1213 .flags = CLK_SET_RATE_PARENT,
1217 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1218 .data = &(struct clk_regmap_gate_data){
1219 .offset = HHI_SD_EMMC_CLK_CNTL,
1222 .hw.init = &(struct clk_init_data){
1223 .name = "sd_emmc_a_clk0",
1224 .ops = &clk_regmap_gate_ops,
1225 .parent_names = (const char *[]){ "sd_emmc_a_clk0_div" },
1227 .flags = CLK_SET_RATE_PARENT,
1232 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1233 .data = &(struct clk_regmap_mux_data){
1234 .offset = HHI_SD_EMMC_CLK_CNTL,
1238 .hw.init = &(struct clk_init_data) {
1239 .name = "sd_emmc_b_clk0_sel",
1240 .ops = &clk_regmap_mux_ops,
1241 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1242 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1243 .flags = CLK_SET_RATE_PARENT,
1247 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1248 .data = &(struct clk_regmap_div_data){
1249 .offset = HHI_SD_EMMC_CLK_CNTL,
1252 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1254 .hw.init = &(struct clk_init_data) {
1255 .name = "sd_emmc_b_clk0_div",
1256 .ops = &clk_regmap_divider_ops,
1257 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
1259 .flags = CLK_SET_RATE_PARENT,
1263 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1264 .data = &(struct clk_regmap_gate_data){
1265 .offset = HHI_SD_EMMC_CLK_CNTL,
1268 .hw.init = &(struct clk_init_data){
1269 .name = "sd_emmc_b_clk0",
1270 .ops = &clk_regmap_gate_ops,
1271 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
1273 .flags = CLK_SET_RATE_PARENT,
1277 /* EMMC/NAND clock */
1278 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1279 .data = &(struct clk_regmap_mux_data){
1280 .offset = HHI_NAND_CLK_CNTL,
1284 .hw.init = &(struct clk_init_data) {
1285 .name = "sd_emmc_c_clk0_sel",
1286 .ops = &clk_regmap_mux_ops,
1287 .parent_names = gxbb_sd_emmc_clk0_parent_names,
1288 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_names),
1289 .flags = CLK_SET_RATE_PARENT,
1293 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1294 .data = &(struct clk_regmap_div_data){
1295 .offset = HHI_NAND_CLK_CNTL,
1298 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1300 .hw.init = &(struct clk_init_data) {
1301 .name = "sd_emmc_c_clk0_div",
1302 .ops = &clk_regmap_divider_ops,
1303 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
1305 .flags = CLK_SET_RATE_PARENT,
1309 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1310 .data = &(struct clk_regmap_gate_data){
1311 .offset = HHI_NAND_CLK_CNTL,
1314 .hw.init = &(struct clk_init_data){
1315 .name = "sd_emmc_c_clk0",
1316 .ops = &clk_regmap_gate_ops,
1317 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
1319 .flags = CLK_SET_RATE_PARENT,
1325 static const char * const gxbb_vpu_parent_names[] = {
1326 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1329 static struct clk_regmap gxbb_vpu_0_sel = {
1330 .data = &(struct clk_regmap_mux_data){
1331 .offset = HHI_VPU_CLK_CNTL,
1335 .hw.init = &(struct clk_init_data){
1336 .name = "vpu_0_sel",
1337 .ops = &clk_regmap_mux_ops,
1339 * bits 9:10 selects from 4 possible parents:
1340 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1342 .parent_names = gxbb_vpu_parent_names,
1343 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1344 .flags = CLK_SET_RATE_NO_REPARENT,
1348 static struct clk_regmap gxbb_vpu_0_div = {
1349 .data = &(struct clk_regmap_div_data){
1350 .offset = HHI_VPU_CLK_CNTL,
1354 .hw.init = &(struct clk_init_data){
1355 .name = "vpu_0_div",
1356 .ops = &clk_regmap_divider_ops,
1357 .parent_names = (const char *[]){ "vpu_0_sel" },
1359 .flags = CLK_SET_RATE_PARENT,
1363 static struct clk_regmap gxbb_vpu_0 = {
1364 .data = &(struct clk_regmap_gate_data){
1365 .offset = HHI_VPU_CLK_CNTL,
1368 .hw.init = &(struct clk_init_data) {
1370 .ops = &clk_regmap_gate_ops,
1371 .parent_names = (const char *[]){ "vpu_0_div" },
1373 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1377 static struct clk_regmap gxbb_vpu_1_sel = {
1378 .data = &(struct clk_regmap_mux_data){
1379 .offset = HHI_VPU_CLK_CNTL,
1383 .hw.init = &(struct clk_init_data){
1384 .name = "vpu_1_sel",
1385 .ops = &clk_regmap_mux_ops,
1387 * bits 25:26 selects from 4 possible parents:
1388 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1390 .parent_names = gxbb_vpu_parent_names,
1391 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_names),
1392 .flags = CLK_SET_RATE_NO_REPARENT,
1396 static struct clk_regmap gxbb_vpu_1_div = {
1397 .data = &(struct clk_regmap_div_data){
1398 .offset = HHI_VPU_CLK_CNTL,
1402 .hw.init = &(struct clk_init_data){
1403 .name = "vpu_1_div",
1404 .ops = &clk_regmap_divider_ops,
1405 .parent_names = (const char *[]){ "vpu_1_sel" },
1407 .flags = CLK_SET_RATE_PARENT,
1411 static struct clk_regmap gxbb_vpu_1 = {
1412 .data = &(struct clk_regmap_gate_data){
1413 .offset = HHI_VPU_CLK_CNTL,
1416 .hw.init = &(struct clk_init_data) {
1418 .ops = &clk_regmap_gate_ops,
1419 .parent_names = (const char *[]){ "vpu_1_div" },
1421 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1425 static struct clk_regmap gxbb_vpu = {
1426 .data = &(struct clk_regmap_mux_data){
1427 .offset = HHI_VPU_CLK_CNTL,
1431 .hw.init = &(struct clk_init_data){
1433 .ops = &clk_regmap_mux_ops,
1435 * bit 31 selects from 2 possible parents:
1438 .parent_names = (const char *[]){ "vpu_0", "vpu_1" },
1440 .flags = CLK_SET_RATE_NO_REPARENT,
1446 static const char * const gxbb_vapb_parent_names[] = {
1447 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
1450 static struct clk_regmap gxbb_vapb_0_sel = {
1451 .data = &(struct clk_regmap_mux_data){
1452 .offset = HHI_VAPBCLK_CNTL,
1456 .hw.init = &(struct clk_init_data){
1457 .name = "vapb_0_sel",
1458 .ops = &clk_regmap_mux_ops,
1460 * bits 9:10 selects from 4 possible parents:
1461 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1463 .parent_names = gxbb_vapb_parent_names,
1464 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1465 .flags = CLK_SET_RATE_NO_REPARENT,
1469 static struct clk_regmap gxbb_vapb_0_div = {
1470 .data = &(struct clk_regmap_div_data){
1471 .offset = HHI_VAPBCLK_CNTL,
1475 .hw.init = &(struct clk_init_data){
1476 .name = "vapb_0_div",
1477 .ops = &clk_regmap_divider_ops,
1478 .parent_names = (const char *[]){ "vapb_0_sel" },
1480 .flags = CLK_SET_RATE_PARENT,
1484 static struct clk_regmap gxbb_vapb_0 = {
1485 .data = &(struct clk_regmap_gate_data){
1486 .offset = HHI_VAPBCLK_CNTL,
1489 .hw.init = &(struct clk_init_data) {
1491 .ops = &clk_regmap_gate_ops,
1492 .parent_names = (const char *[]){ "vapb_0_div" },
1494 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1498 static struct clk_regmap gxbb_vapb_1_sel = {
1499 .data = &(struct clk_regmap_mux_data){
1500 .offset = HHI_VAPBCLK_CNTL,
1504 .hw.init = &(struct clk_init_data){
1505 .name = "vapb_1_sel",
1506 .ops = &clk_regmap_mux_ops,
1508 * bits 25:26 selects from 4 possible parents:
1509 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1511 .parent_names = gxbb_vapb_parent_names,
1512 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_names),
1513 .flags = CLK_SET_RATE_NO_REPARENT,
1517 static struct clk_regmap gxbb_vapb_1_div = {
1518 .data = &(struct clk_regmap_div_data){
1519 .offset = HHI_VAPBCLK_CNTL,
1523 .hw.init = &(struct clk_init_data){
1524 .name = "vapb_1_div",
1525 .ops = &clk_regmap_divider_ops,
1526 .parent_names = (const char *[]){ "vapb_1_sel" },
1528 .flags = CLK_SET_RATE_PARENT,
1532 static struct clk_regmap gxbb_vapb_1 = {
1533 .data = &(struct clk_regmap_gate_data){
1534 .offset = HHI_VAPBCLK_CNTL,
1537 .hw.init = &(struct clk_init_data) {
1539 .ops = &clk_regmap_gate_ops,
1540 .parent_names = (const char *[]){ "vapb_1_div" },
1542 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1546 static struct clk_regmap gxbb_vapb_sel = {
1547 .data = &(struct clk_regmap_mux_data){
1548 .offset = HHI_VAPBCLK_CNTL,
1552 .hw.init = &(struct clk_init_data){
1554 .ops = &clk_regmap_mux_ops,
1556 * bit 31 selects from 2 possible parents:
1559 .parent_names = (const char *[]){ "vapb_0", "vapb_1" },
1561 .flags = CLK_SET_RATE_NO_REPARENT,
1565 static struct clk_regmap gxbb_vapb = {
1566 .data = &(struct clk_regmap_gate_data){
1567 .offset = HHI_VAPBCLK_CNTL,
1570 .hw.init = &(struct clk_init_data) {
1572 .ops = &clk_regmap_gate_ops,
1573 .parent_names = (const char *[]){ "vapb_sel" },
1575 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1581 static struct clk_regmap gxbb_vid_pll_div = {
1582 .data = &(struct meson_vid_pll_div_data){
1584 .reg_off = HHI_VID_PLL_CLK_DIV,
1589 .reg_off = HHI_VID_PLL_CLK_DIV,
1594 .hw.init = &(struct clk_init_data) {
1595 .name = "vid_pll_div",
1596 .ops = &meson_vid_pll_div_ro_ops,
1597 .parent_names = (const char *[]){ "hdmi_pll" },
1599 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1603 static const char * const gxbb_vid_pll_parent_names[] = { "vid_pll_div", "hdmi_pll" };
1605 static struct clk_regmap gxbb_vid_pll_sel = {
1606 .data = &(struct clk_regmap_mux_data){
1607 .offset = HHI_VID_PLL_CLK_DIV,
1611 .hw.init = &(struct clk_init_data){
1612 .name = "vid_pll_sel",
1613 .ops = &clk_regmap_mux_ops,
1615 * bit 18 selects from 2 possible parents:
1616 * vid_pll_div or hdmi_pll
1618 .parent_names = gxbb_vid_pll_parent_names,
1619 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_names),
1620 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1624 static struct clk_regmap gxbb_vid_pll = {
1625 .data = &(struct clk_regmap_gate_data){
1626 .offset = HHI_VID_PLL_CLK_DIV,
1629 .hw.init = &(struct clk_init_data) {
1631 .ops = &clk_regmap_gate_ops,
1632 .parent_names = (const char *[]){ "vid_pll_sel" },
1634 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1638 static const char * const gxbb_vclk_parent_names[] = {
1639 "vid_pll", "fclk_div4", "fclk_div3", "fclk_div5", "vid_pll",
1640 "fclk_div7", "mpll1",
1643 static struct clk_regmap gxbb_vclk_sel = {
1644 .data = &(struct clk_regmap_mux_data){
1645 .offset = HHI_VID_CLK_CNTL,
1649 .hw.init = &(struct clk_init_data){
1651 .ops = &clk_regmap_mux_ops,
1653 * bits 16:18 selects from 8 possible parents:
1654 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1655 * vid_pll, fclk_div7, mp1
1657 .parent_names = gxbb_vclk_parent_names,
1658 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
1659 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1663 static struct clk_regmap gxbb_vclk2_sel = {
1664 .data = &(struct clk_regmap_mux_data){
1665 .offset = HHI_VIID_CLK_CNTL,
1669 .hw.init = &(struct clk_init_data){
1670 .name = "vclk2_sel",
1671 .ops = &clk_regmap_mux_ops,
1673 * bits 16:18 selects from 8 possible parents:
1674 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1675 * vid_pll, fclk_div7, mp1
1677 .parent_names = gxbb_vclk_parent_names,
1678 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_names),
1679 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1683 static struct clk_regmap gxbb_vclk_input = {
1684 .data = &(struct clk_regmap_gate_data){
1685 .offset = HHI_VID_CLK_DIV,
1688 .hw.init = &(struct clk_init_data) {
1689 .name = "vclk_input",
1690 .ops = &clk_regmap_gate_ops,
1691 .parent_names = (const char *[]){ "vclk_sel" },
1693 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1697 static struct clk_regmap gxbb_vclk2_input = {
1698 .data = &(struct clk_regmap_gate_data){
1699 .offset = HHI_VIID_CLK_DIV,
1702 .hw.init = &(struct clk_init_data) {
1703 .name = "vclk2_input",
1704 .ops = &clk_regmap_gate_ops,
1705 .parent_names = (const char *[]){ "vclk2_sel" },
1707 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1711 static struct clk_regmap gxbb_vclk_div = {
1712 .data = &(struct clk_regmap_div_data){
1713 .offset = HHI_VID_CLK_DIV,
1717 .hw.init = &(struct clk_init_data){
1719 .ops = &clk_regmap_divider_ops,
1720 .parent_names = (const char *[]){ "vclk_input" },
1722 .flags = CLK_GET_RATE_NOCACHE,
1726 static struct clk_regmap gxbb_vclk2_div = {
1727 .data = &(struct clk_regmap_div_data){
1728 .offset = HHI_VIID_CLK_DIV,
1732 .hw.init = &(struct clk_init_data){
1733 .name = "vclk2_div",
1734 .ops = &clk_regmap_divider_ops,
1735 .parent_names = (const char *[]){ "vclk2_input" },
1737 .flags = CLK_GET_RATE_NOCACHE,
1741 static struct clk_regmap gxbb_vclk = {
1742 .data = &(struct clk_regmap_gate_data){
1743 .offset = HHI_VID_CLK_CNTL,
1746 .hw.init = &(struct clk_init_data) {
1748 .ops = &clk_regmap_gate_ops,
1749 .parent_names = (const char *[]){ "vclk_div" },
1751 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1755 static struct clk_regmap gxbb_vclk2 = {
1756 .data = &(struct clk_regmap_gate_data){
1757 .offset = HHI_VIID_CLK_CNTL,
1760 .hw.init = &(struct clk_init_data) {
1762 .ops = &clk_regmap_gate_ops,
1763 .parent_names = (const char *[]){ "vclk2_div" },
1765 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1769 static struct clk_regmap gxbb_vclk_div1 = {
1770 .data = &(struct clk_regmap_gate_data){
1771 .offset = HHI_VID_CLK_CNTL,
1774 .hw.init = &(struct clk_init_data) {
1775 .name = "vclk_div1",
1776 .ops = &clk_regmap_gate_ops,
1777 .parent_names = (const char *[]){ "vclk" },
1779 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1783 static struct clk_regmap gxbb_vclk_div2_en = {
1784 .data = &(struct clk_regmap_gate_data){
1785 .offset = HHI_VID_CLK_CNTL,
1788 .hw.init = &(struct clk_init_data) {
1789 .name = "vclk_div2_en",
1790 .ops = &clk_regmap_gate_ops,
1791 .parent_names = (const char *[]){ "vclk" },
1793 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1797 static struct clk_regmap gxbb_vclk_div4_en = {
1798 .data = &(struct clk_regmap_gate_data){
1799 .offset = HHI_VID_CLK_CNTL,
1802 .hw.init = &(struct clk_init_data) {
1803 .name = "vclk_div4_en",
1804 .ops = &clk_regmap_gate_ops,
1805 .parent_names = (const char *[]){ "vclk" },
1807 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1811 static struct clk_regmap gxbb_vclk_div6_en = {
1812 .data = &(struct clk_regmap_gate_data){
1813 .offset = HHI_VID_CLK_CNTL,
1816 .hw.init = &(struct clk_init_data) {
1817 .name = "vclk_div6_en",
1818 .ops = &clk_regmap_gate_ops,
1819 .parent_names = (const char *[]){ "vclk" },
1821 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1825 static struct clk_regmap gxbb_vclk_div12_en = {
1826 .data = &(struct clk_regmap_gate_data){
1827 .offset = HHI_VID_CLK_CNTL,
1830 .hw.init = &(struct clk_init_data) {
1831 .name = "vclk_div12_en",
1832 .ops = &clk_regmap_gate_ops,
1833 .parent_names = (const char *[]){ "vclk" },
1835 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1839 static struct clk_regmap gxbb_vclk2_div1 = {
1840 .data = &(struct clk_regmap_gate_data){
1841 .offset = HHI_VIID_CLK_CNTL,
1844 .hw.init = &(struct clk_init_data) {
1845 .name = "vclk2_div1",
1846 .ops = &clk_regmap_gate_ops,
1847 .parent_names = (const char *[]){ "vclk2" },
1849 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1853 static struct clk_regmap gxbb_vclk2_div2_en = {
1854 .data = &(struct clk_regmap_gate_data){
1855 .offset = HHI_VIID_CLK_CNTL,
1858 .hw.init = &(struct clk_init_data) {
1859 .name = "vclk2_div2_en",
1860 .ops = &clk_regmap_gate_ops,
1861 .parent_names = (const char *[]){ "vclk2" },
1863 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1867 static struct clk_regmap gxbb_vclk2_div4_en = {
1868 .data = &(struct clk_regmap_gate_data){
1869 .offset = HHI_VIID_CLK_CNTL,
1872 .hw.init = &(struct clk_init_data) {
1873 .name = "vclk2_div4_en",
1874 .ops = &clk_regmap_gate_ops,
1875 .parent_names = (const char *[]){ "vclk2" },
1877 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1881 static struct clk_regmap gxbb_vclk2_div6_en = {
1882 .data = &(struct clk_regmap_gate_data){
1883 .offset = HHI_VIID_CLK_CNTL,
1886 .hw.init = &(struct clk_init_data) {
1887 .name = "vclk2_div6_en",
1888 .ops = &clk_regmap_gate_ops,
1889 .parent_names = (const char *[]){ "vclk2" },
1891 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1895 static struct clk_regmap gxbb_vclk2_div12_en = {
1896 .data = &(struct clk_regmap_gate_data){
1897 .offset = HHI_VIID_CLK_CNTL,
1900 .hw.init = &(struct clk_init_data) {
1901 .name = "vclk2_div12_en",
1902 .ops = &clk_regmap_gate_ops,
1903 .parent_names = (const char *[]){ "vclk2" },
1905 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1909 static struct clk_fixed_factor gxbb_vclk_div2 = {
1912 .hw.init = &(struct clk_init_data){
1913 .name = "vclk_div2",
1914 .ops = &clk_fixed_factor_ops,
1915 .parent_names = (const char *[]){ "vclk_div2_en" },
1920 static struct clk_fixed_factor gxbb_vclk_div4 = {
1923 .hw.init = &(struct clk_init_data){
1924 .name = "vclk_div4",
1925 .ops = &clk_fixed_factor_ops,
1926 .parent_names = (const char *[]){ "vclk_div4_en" },
1931 static struct clk_fixed_factor gxbb_vclk_div6 = {
1934 .hw.init = &(struct clk_init_data){
1935 .name = "vclk_div6",
1936 .ops = &clk_fixed_factor_ops,
1937 .parent_names = (const char *[]){ "vclk_div6_en" },
1942 static struct clk_fixed_factor gxbb_vclk_div12 = {
1945 .hw.init = &(struct clk_init_data){
1946 .name = "vclk_div12",
1947 .ops = &clk_fixed_factor_ops,
1948 .parent_names = (const char *[]){ "vclk_div12_en" },
1953 static struct clk_fixed_factor gxbb_vclk2_div2 = {
1956 .hw.init = &(struct clk_init_data){
1957 .name = "vclk2_div2",
1958 .ops = &clk_fixed_factor_ops,
1959 .parent_names = (const char *[]){ "vclk2_div2_en" },
1964 static struct clk_fixed_factor gxbb_vclk2_div4 = {
1967 .hw.init = &(struct clk_init_data){
1968 .name = "vclk2_div4",
1969 .ops = &clk_fixed_factor_ops,
1970 .parent_names = (const char *[]){ "vclk2_div4_en" },
1975 static struct clk_fixed_factor gxbb_vclk2_div6 = {
1978 .hw.init = &(struct clk_init_data){
1979 .name = "vclk2_div6",
1980 .ops = &clk_fixed_factor_ops,
1981 .parent_names = (const char *[]){ "vclk2_div6_en" },
1986 static struct clk_fixed_factor gxbb_vclk2_div12 = {
1989 .hw.init = &(struct clk_init_data){
1990 .name = "vclk2_div12",
1991 .ops = &clk_fixed_factor_ops,
1992 .parent_names = (const char *[]){ "vclk2_div12_en" },
1997 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
1998 static const char * const gxbb_cts_parent_names[] = {
1999 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2000 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2001 "vclk2_div6", "vclk2_div12"
2004 static struct clk_regmap gxbb_cts_enci_sel = {
2005 .data = &(struct clk_regmap_mux_data){
2006 .offset = HHI_VID_CLK_DIV,
2009 .table = mux_table_cts_sel,
2011 .hw.init = &(struct clk_init_data){
2012 .name = "cts_enci_sel",
2013 .ops = &clk_regmap_mux_ops,
2014 .parent_names = gxbb_cts_parent_names,
2015 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2016 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2020 static struct clk_regmap gxbb_cts_encp_sel = {
2021 .data = &(struct clk_regmap_mux_data){
2022 .offset = HHI_VID_CLK_DIV,
2025 .table = mux_table_cts_sel,
2027 .hw.init = &(struct clk_init_data){
2028 .name = "cts_encp_sel",
2029 .ops = &clk_regmap_mux_ops,
2030 .parent_names = gxbb_cts_parent_names,
2031 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2032 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2036 static struct clk_regmap gxbb_cts_vdac_sel = {
2037 .data = &(struct clk_regmap_mux_data){
2038 .offset = HHI_VIID_CLK_DIV,
2041 .table = mux_table_cts_sel,
2043 .hw.init = &(struct clk_init_data){
2044 .name = "cts_vdac_sel",
2045 .ops = &clk_regmap_mux_ops,
2046 .parent_names = gxbb_cts_parent_names,
2047 .num_parents = ARRAY_SIZE(gxbb_cts_parent_names),
2048 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2052 /* TOFIX: add support for cts_tcon */
2053 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2054 static const char * const gxbb_cts_hdmi_tx_parent_names[] = {
2055 "vclk_div1", "vclk_div2", "vclk_div4", "vclk_div6",
2056 "vclk_div12", "vclk2_div1", "vclk2_div2", "vclk2_div4",
2057 "vclk2_div6", "vclk2_div12"
2060 static struct clk_regmap gxbb_hdmi_tx_sel = {
2061 .data = &(struct clk_regmap_mux_data){
2062 .offset = HHI_HDMI_CLK_CNTL,
2065 .table = mux_table_hdmi_tx_sel,
2067 .hw.init = &(struct clk_init_data){
2068 .name = "hdmi_tx_sel",
2069 .ops = &clk_regmap_mux_ops,
2071 * bits 31:28 selects from 12 possible parents:
2072 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2073 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2076 .parent_names = gxbb_cts_hdmi_tx_parent_names,
2077 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_names),
2078 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2082 static struct clk_regmap gxbb_cts_enci = {
2083 .data = &(struct clk_regmap_gate_data){
2084 .offset = HHI_VID_CLK_CNTL2,
2087 .hw.init = &(struct clk_init_data) {
2089 .ops = &clk_regmap_gate_ops,
2090 .parent_names = (const char *[]){ "cts_enci_sel" },
2092 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2096 static struct clk_regmap gxbb_cts_encp = {
2097 .data = &(struct clk_regmap_gate_data){
2098 .offset = HHI_VID_CLK_CNTL2,
2101 .hw.init = &(struct clk_init_data) {
2103 .ops = &clk_regmap_gate_ops,
2104 .parent_names = (const char *[]){ "cts_encp_sel" },
2106 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2110 static struct clk_regmap gxbb_cts_vdac = {
2111 .data = &(struct clk_regmap_gate_data){
2112 .offset = HHI_VID_CLK_CNTL2,
2115 .hw.init = &(struct clk_init_data) {
2117 .ops = &clk_regmap_gate_ops,
2118 .parent_names = (const char *[]){ "cts_vdac_sel" },
2120 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2124 static struct clk_regmap gxbb_hdmi_tx = {
2125 .data = &(struct clk_regmap_gate_data){
2126 .offset = HHI_VID_CLK_CNTL2,
2129 .hw.init = &(struct clk_init_data) {
2131 .ops = &clk_regmap_gate_ops,
2132 .parent_names = (const char *[]){ "hdmi_tx_sel" },
2134 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2140 static const char * const gxbb_hdmi_parent_names[] = {
2141 "xtal", "fclk_div4", "fclk_div3", "fclk_div5"
2144 static struct clk_regmap gxbb_hdmi_sel = {
2145 .data = &(struct clk_regmap_mux_data){
2146 .offset = HHI_HDMI_CLK_CNTL,
2149 .flags = CLK_MUX_ROUND_CLOSEST,
2151 .hw.init = &(struct clk_init_data){
2153 .ops = &clk_regmap_mux_ops,
2154 .parent_names = gxbb_hdmi_parent_names,
2155 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_names),
2156 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2160 static struct clk_regmap gxbb_hdmi_div = {
2161 .data = &(struct clk_regmap_div_data){
2162 .offset = HHI_HDMI_CLK_CNTL,
2166 .hw.init = &(struct clk_init_data){
2168 .ops = &clk_regmap_divider_ops,
2169 .parent_names = (const char *[]){ "hdmi_sel" },
2171 .flags = CLK_GET_RATE_NOCACHE,
2175 static struct clk_regmap gxbb_hdmi = {
2176 .data = &(struct clk_regmap_gate_data){
2177 .offset = HHI_HDMI_CLK_CNTL,
2180 .hw.init = &(struct clk_init_data) {
2182 .ops = &clk_regmap_gate_ops,
2183 .parent_names = (const char *[]){ "hdmi_div" },
2185 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2191 static const char * const gxbb_vdec_parent_names[] = {
2192 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7"
2195 static struct clk_regmap gxbb_vdec_1_sel = {
2196 .data = &(struct clk_regmap_mux_data){
2197 .offset = HHI_VDEC_CLK_CNTL,
2200 .flags = CLK_MUX_ROUND_CLOSEST,
2202 .hw.init = &(struct clk_init_data){
2203 .name = "vdec_1_sel",
2204 .ops = &clk_regmap_mux_ops,
2205 .parent_names = gxbb_vdec_parent_names,
2206 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
2207 .flags = CLK_SET_RATE_PARENT,
2211 static struct clk_regmap gxbb_vdec_1_div = {
2212 .data = &(struct clk_regmap_div_data){
2213 .offset = HHI_VDEC_CLK_CNTL,
2217 .hw.init = &(struct clk_init_data){
2218 .name = "vdec_1_div",
2219 .ops = &clk_regmap_divider_ops,
2220 .parent_names = (const char *[]){ "vdec_1_sel" },
2222 .flags = CLK_SET_RATE_PARENT,
2226 static struct clk_regmap gxbb_vdec_1 = {
2227 .data = &(struct clk_regmap_gate_data){
2228 .offset = HHI_VDEC_CLK_CNTL,
2231 .hw.init = &(struct clk_init_data) {
2233 .ops = &clk_regmap_gate_ops,
2234 .parent_names = (const char *[]){ "vdec_1_div" },
2236 .flags = CLK_SET_RATE_PARENT,
2240 static struct clk_regmap gxbb_vdec_hevc_sel = {
2241 .data = &(struct clk_regmap_mux_data){
2242 .offset = HHI_VDEC2_CLK_CNTL,
2245 .flags = CLK_MUX_ROUND_CLOSEST,
2247 .hw.init = &(struct clk_init_data){
2248 .name = "vdec_hevc_sel",
2249 .ops = &clk_regmap_mux_ops,
2250 .parent_names = gxbb_vdec_parent_names,
2251 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_names),
2252 .flags = CLK_SET_RATE_PARENT,
2256 static struct clk_regmap gxbb_vdec_hevc_div = {
2257 .data = &(struct clk_regmap_div_data){
2258 .offset = HHI_VDEC2_CLK_CNTL,
2262 .hw.init = &(struct clk_init_data){
2263 .name = "vdec_hevc_div",
2264 .ops = &clk_regmap_divider_ops,
2265 .parent_names = (const char *[]){ "vdec_hevc_sel" },
2267 .flags = CLK_SET_RATE_PARENT,
2271 static struct clk_regmap gxbb_vdec_hevc = {
2272 .data = &(struct clk_regmap_gate_data){
2273 .offset = HHI_VDEC2_CLK_CNTL,
2276 .hw.init = &(struct clk_init_data) {
2277 .name = "vdec_hevc",
2278 .ops = &clk_regmap_gate_ops,
2279 .parent_names = (const char *[]){ "vdec_hevc_div" },
2281 .flags = CLK_SET_RATE_PARENT,
2285 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2286 9, 10, 11, 13, 14, };
2287 static const char * const gen_clk_parent_names[] = {
2288 "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
2289 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
2292 static struct clk_regmap gxbb_gen_clk_sel = {
2293 .data = &(struct clk_regmap_mux_data){
2294 .offset = HHI_GEN_CLK_CNTL,
2297 .table = mux_table_gen_clk,
2299 .hw.init = &(struct clk_init_data){
2300 .name = "gen_clk_sel",
2301 .ops = &clk_regmap_mux_ops,
2303 * bits 15:12 selects from 14 possible parents:
2304 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2305 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2306 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2308 .parent_names = gen_clk_parent_names,
2309 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
2313 static struct clk_regmap gxbb_gen_clk_div = {
2314 .data = &(struct clk_regmap_div_data){
2315 .offset = HHI_GEN_CLK_CNTL,
2319 .hw.init = &(struct clk_init_data){
2320 .name = "gen_clk_div",
2321 .ops = &clk_regmap_divider_ops,
2322 .parent_names = (const char *[]){ "gen_clk_sel" },
2324 .flags = CLK_SET_RATE_PARENT,
2328 static struct clk_regmap gxbb_gen_clk = {
2329 .data = &(struct clk_regmap_gate_data){
2330 .offset = HHI_GEN_CLK_CNTL,
2333 .hw.init = &(struct clk_init_data){
2335 .ops = &clk_regmap_gate_ops,
2336 .parent_names = (const char *[]){ "gen_clk_div" },
2338 .flags = CLK_SET_RATE_PARENT,
2342 /* Everything Else (EE) domain gates */
2343 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2344 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2345 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2346 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2347 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2348 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2349 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2350 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2351 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2352 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2353 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2354 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2355 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2356 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2357 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2358 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2359 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2360 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2361 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2362 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2363 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2364 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2366 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2367 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2368 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2369 static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
2370 static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
2371 static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
2372 static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
2373 static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
2374 static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
2375 static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
2376 static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
2377 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2378 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2379 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2380 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2381 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2382 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2383 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2384 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2385 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2386 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2387 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2388 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2389 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2390 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2392 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2393 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2394 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2395 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2396 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2397 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2398 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2399 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2400 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2401 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2402 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2403 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2404 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2406 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2407 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2408 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2409 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2410 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2411 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2412 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2413 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2414 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2415 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2416 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2417 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2418 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2419 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2420 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2421 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2423 /* Always On (AO) domain gates */
2425 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2426 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2427 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2428 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2429 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2431 /* Array of all clocks provided by this provider */
2433 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2435 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2436 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
2437 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2438 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2439 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2440 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2441 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2442 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2443 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2444 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2445 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2446 [CLKID_CLK81] = &gxbb_clk81.hw,
2447 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2448 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2449 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2450 [CLKID_DDR] = &gxbb_ddr.hw,
2451 [CLKID_DOS] = &gxbb_dos.hw,
2452 [CLKID_ISA] = &gxbb_isa.hw,
2453 [CLKID_PL301] = &gxbb_pl301.hw,
2454 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2455 [CLKID_SPICC] = &gxbb_spicc.hw,
2456 [CLKID_I2C] = &gxbb_i2c.hw,
2457 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2458 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2459 [CLKID_RNG0] = &gxbb_rng0.hw,
2460 [CLKID_UART0] = &gxbb_uart0.hw,
2461 [CLKID_SDHC] = &gxbb_sdhc.hw,
2462 [CLKID_STREAM] = &gxbb_stream.hw,
2463 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2464 [CLKID_SDIO] = &gxbb_sdio.hw,
2465 [CLKID_ABUF] = &gxbb_abuf.hw,
2466 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2467 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2468 [CLKID_SPI] = &gxbb_spi.hw,
2469 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2470 [CLKID_ETH] = &gxbb_eth.hw,
2471 [CLKID_DEMUX] = &gxbb_demux.hw,
2472 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2473 [CLKID_IEC958] = &gxbb_iec958.hw,
2474 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2475 [CLKID_AMCLK] = &gxbb_amclk.hw,
2476 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2477 [CLKID_MIXER] = &gxbb_mixer.hw,
2478 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2479 [CLKID_ADC] = &gxbb_adc.hw,
2480 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2481 [CLKID_AIU] = &gxbb_aiu.hw,
2482 [CLKID_UART1] = &gxbb_uart1.hw,
2483 [CLKID_G2D] = &gxbb_g2d.hw,
2484 [CLKID_USB0] = &gxbb_usb0.hw,
2485 [CLKID_USB1] = &gxbb_usb1.hw,
2486 [CLKID_RESET] = &gxbb_reset.hw,
2487 [CLKID_NAND] = &gxbb_nand.hw,
2488 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2489 [CLKID_USB] = &gxbb_usb.hw,
2490 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2491 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2492 [CLKID_EFUSE] = &gxbb_efuse.hw,
2493 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2494 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2495 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2496 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2497 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2498 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
2499 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
2500 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
2501 [CLKID_DVIN] = &gxbb_dvin.hw,
2502 [CLKID_UART2] = &gxbb_uart2.hw,
2503 [CLKID_SANA] = &gxbb_sana.hw,
2504 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2505 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2506 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2507 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2508 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2509 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2510 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2511 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2512 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2513 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2514 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2515 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2516 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2517 [CLKID_RNG1] = &gxbb_rng1.hw,
2518 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2519 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2520 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2521 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2522 [CLKID_EDP] = &gxbb_edp.hw,
2523 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2524 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2525 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2526 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2527 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2528 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2529 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2530 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2531 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2532 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2533 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2534 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2535 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2536 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2537 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2538 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2539 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2540 [CLKID_MALI] = &gxbb_mali.hw,
2541 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2542 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2543 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2544 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2545 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2546 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2547 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2548 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2549 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2550 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2551 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2552 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2553 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2554 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2555 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2556 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2557 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2558 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2559 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2560 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2561 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2562 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2563 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2564 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2565 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2566 [CLKID_VPU] = &gxbb_vpu.hw,
2567 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2568 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2569 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2570 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2571 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2572 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2573 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2574 [CLKID_VAPB] = &gxbb_vapb.hw,
2575 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
2576 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2577 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2578 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2579 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2580 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2581 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2582 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2583 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2584 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2585 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2586 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2587 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2588 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2589 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2590 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2591 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2592 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2593 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2594 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2595 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2596 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
2597 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
2598 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2599 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
2600 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
2601 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
2602 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
2603 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
2604 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
2605 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
2606 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
2607 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
2608 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
2609 [CLKID_VCLK] = &gxbb_vclk.hw,
2610 [CLKID_VCLK2] = &gxbb_vclk2.hw,
2611 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
2612 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
2613 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
2614 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
2615 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
2616 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
2617 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
2618 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
2619 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
2620 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
2621 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
2622 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
2623 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
2624 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
2625 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
2626 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
2627 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
2628 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
2629 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
2630 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
2631 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
2632 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
2633 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
2634 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
2635 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
2636 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
2637 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
2638 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
2639 [CLKID_HDMI] = &gxbb_hdmi.hw,
2645 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2647 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2648 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
2649 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2650 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2651 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2652 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2653 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2654 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2655 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2656 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2657 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2658 [CLKID_CLK81] = &gxbb_clk81.hw,
2659 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2660 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2661 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2662 [CLKID_DDR] = &gxbb_ddr.hw,
2663 [CLKID_DOS] = &gxbb_dos.hw,
2664 [CLKID_ISA] = &gxbb_isa.hw,
2665 [CLKID_PL301] = &gxbb_pl301.hw,
2666 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2667 [CLKID_SPICC] = &gxbb_spicc.hw,
2668 [CLKID_I2C] = &gxbb_i2c.hw,
2669 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2670 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2671 [CLKID_RNG0] = &gxbb_rng0.hw,
2672 [CLKID_UART0] = &gxbb_uart0.hw,
2673 [CLKID_SDHC] = &gxbb_sdhc.hw,
2674 [CLKID_STREAM] = &gxbb_stream.hw,
2675 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2676 [CLKID_SDIO] = &gxbb_sdio.hw,
2677 [CLKID_ABUF] = &gxbb_abuf.hw,
2678 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2679 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2680 [CLKID_SPI] = &gxbb_spi.hw,
2681 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2682 [CLKID_ETH] = &gxbb_eth.hw,
2683 [CLKID_DEMUX] = &gxbb_demux.hw,
2684 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2685 [CLKID_IEC958] = &gxbb_iec958.hw,
2686 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2687 [CLKID_AMCLK] = &gxbb_amclk.hw,
2688 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2689 [CLKID_MIXER] = &gxbb_mixer.hw,
2690 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2691 [CLKID_ADC] = &gxbb_adc.hw,
2692 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2693 [CLKID_AIU] = &gxbb_aiu.hw,
2694 [CLKID_UART1] = &gxbb_uart1.hw,
2695 [CLKID_G2D] = &gxbb_g2d.hw,
2696 [CLKID_USB0] = &gxbb_usb0.hw,
2697 [CLKID_USB1] = &gxbb_usb1.hw,
2698 [CLKID_RESET] = &gxbb_reset.hw,
2699 [CLKID_NAND] = &gxbb_nand.hw,
2700 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2701 [CLKID_USB] = &gxbb_usb.hw,
2702 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2703 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2704 [CLKID_EFUSE] = &gxbb_efuse.hw,
2705 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2706 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2707 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2708 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2709 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2710 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
2711 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
2712 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
2713 [CLKID_DVIN] = &gxbb_dvin.hw,
2714 [CLKID_UART2] = &gxbb_uart2.hw,
2715 [CLKID_SANA] = &gxbb_sana.hw,
2716 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2717 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2718 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2719 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2720 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2721 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2722 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2723 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2724 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2725 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2726 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2727 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2728 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2729 [CLKID_RNG1] = &gxbb_rng1.hw,
2730 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2731 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2732 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2733 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2734 [CLKID_EDP] = &gxbb_edp.hw,
2735 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2736 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2737 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2738 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2739 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2740 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2741 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2742 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2743 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2744 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2745 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2746 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2747 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2748 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2749 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2750 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2751 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2752 [CLKID_MALI] = &gxbb_mali.hw,
2753 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2754 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2755 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2756 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2757 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2758 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2759 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2760 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2761 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2762 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2763 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2764 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2765 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2766 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2767 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2768 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2769 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2770 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2771 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2772 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2773 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2774 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2775 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2776 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2777 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2778 [CLKID_VPU] = &gxbb_vpu.hw,
2779 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2780 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2781 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2782 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2783 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2784 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2785 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2786 [CLKID_VAPB] = &gxbb_vapb.hw,
2787 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2788 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2789 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2790 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2791 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2792 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2793 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2794 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2795 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2796 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2797 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2798 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2799 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2800 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2801 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2802 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2803 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2804 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2805 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2806 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
2807 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
2808 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
2809 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2810 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
2811 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
2812 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
2813 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
2814 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
2815 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
2816 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
2817 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
2818 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
2819 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
2820 [CLKID_VCLK] = &gxbb_vclk.hw,
2821 [CLKID_VCLK2] = &gxbb_vclk2.hw,
2822 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
2823 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
2824 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
2825 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
2826 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
2827 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
2828 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
2829 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
2830 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
2831 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
2832 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
2833 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
2834 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
2835 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
2836 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
2837 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
2838 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
2839 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
2840 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
2841 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
2842 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
2843 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
2844 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
2845 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
2846 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
2847 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
2848 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
2849 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
2850 [CLKID_HDMI] = &gxbb_hdmi.hw,
2856 static struct clk_regmap *const gxbb_clk_regmaps[] = {
2864 static struct clk_regmap *const gxl_clk_regmaps[] = {
2872 static struct clk_regmap *const gx_clk_regmaps[] = {
2920 &gxbb_hdmi_intr_sync,
2922 &gxbb_usb1_ddr_bridge,
2923 &gxbb_usb0_ddr_bridge,
2929 &gxbb_sec_ahb_ahb3_bridge,
2935 &gxbb_gclk_venci_int0,
2936 &gxbb_gclk_vencp_int,
2942 &gxbb_gclk_venci_int1,
2943 &gxbb_vclk2_venclmcc,
2959 &gxbb_cts_mclk_i958,
2961 &gxbb_sd_emmc_a_clk0,
2962 &gxbb_sd_emmc_b_clk0,
2963 &gxbb_sd_emmc_c_clk0,
2970 &gxbb_sar_adc_clk_div,
2973 &gxbb_cts_mclk_i958_div,
2975 &gxbb_sd_emmc_a_clk0_div,
2976 &gxbb_sd_emmc_b_clk0_div,
2977 &gxbb_sd_emmc_c_clk0_div,
2983 &gxbb_sar_adc_clk_sel,
2987 &gxbb_cts_amclk_sel,
2988 &gxbb_cts_mclk_i958_sel,
2991 &gxbb_sd_emmc_a_clk0_sel,
2992 &gxbb_sd_emmc_b_clk0_sel,
2993 &gxbb_sd_emmc_c_clk0_sel,
3006 &gxbb_cts_amclk_div,
3018 &gxbb_vdec_hevc_sel,
3019 &gxbb_vdec_hevc_div,
3024 &gxbb_fixed_pll_dco,
3038 &gxbb_vclk_div12_en,
3044 &gxbb_vclk2_div2_en,
3045 &gxbb_vclk2_div4_en,
3046 &gxbb_vclk2_div6_en,
3047 &gxbb_vclk2_div12_en,
3062 struct clk_regmap *const *regmap_clks;
3063 unsigned int regmap_clks_count;
3064 struct clk_hw_onecell_data *hw_onecell_data;
3067 static const struct clkc_data gxbb_clkc_data = {
3068 .regmap_clks = gxbb_clk_regmaps,
3069 .regmap_clks_count = ARRAY_SIZE(gxbb_clk_regmaps),
3070 .hw_onecell_data = &gxbb_hw_onecell_data,
3073 static const struct clkc_data gxl_clkc_data = {
3074 .regmap_clks = gxl_clk_regmaps,
3075 .regmap_clks_count = ARRAY_SIZE(gxl_clk_regmaps),
3076 .hw_onecell_data = &gxl_hw_onecell_data,
3079 static const struct of_device_id clkc_match_table[] = {
3080 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3081 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3085 static int gxbb_clkc_probe(struct platform_device *pdev)
3087 const struct clkc_data *clkc_data;
3090 struct device *dev = &pdev->dev;
3092 clkc_data = of_device_get_match_data(dev);
3096 /* Get the hhi system controller node if available */
3097 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
3099 dev_err(dev, "failed to get HHI regmap\n");
3100 return PTR_ERR(map);
3103 /* Populate regmap for the common regmap backed clocks */
3104 for (i = 0; i < ARRAY_SIZE(gx_clk_regmaps); i++)
3105 gx_clk_regmaps[i]->map = map;
3107 /* Populate regmap for soc specific clocks */
3108 for (i = 0; i < clkc_data->regmap_clks_count; i++)
3109 clkc_data->regmap_clks[i]->map = map;
3111 /* Register all clks */
3112 for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
3113 /* array might be sparse */
3114 if (!clkc_data->hw_onecell_data->hws[i])
3117 ret = devm_clk_hw_register(dev,
3118 clkc_data->hw_onecell_data->hws[i]);
3120 dev_err(dev, "Clock registration failed\n");
3125 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
3126 clkc_data->hw_onecell_data);
3129 static struct platform_driver gxbb_driver = {
3130 .probe = gxbb_clkc_probe,
3132 .name = "gxbb-clkc",
3133 .of_match_table = clkc_match_table,
3137 builtin_platform_driver(gxbb_driver);