drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/init.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11 #include <linux/module.h>
  12
  13 #include "gxbb.h"
  14 #include "clk-regmap.h"
  15 #include "clk-pll.h"
  16 #include "clk-mpll.h"
  17 #include "meson-eeclk.h"
  18 #include "vid-pll-div.h"
  19
  20 static DEFINE_SPINLOCK(meson_clk_lock);
  21
  22 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  23         PLL_PARAMS(32, 1),
  24         PLL_PARAMS(33, 1),
  25         PLL_PARAMS(34, 1),
  26         PLL_PARAMS(35, 1),
  27         PLL_PARAMS(36, 1),
  28         PLL_PARAMS(37, 1),
  29         PLL_PARAMS(38, 1),
  30         PLL_PARAMS(39, 1),
  31         PLL_PARAMS(40, 1),
  32         PLL_PARAMS(41, 1),
  33         PLL_PARAMS(42, 1),
  34         PLL_PARAMS(43, 1),
  35         PLL_PARAMS(44, 1),
  36         PLL_PARAMS(45, 1),
  37         PLL_PARAMS(46, 1),
  38         PLL_PARAMS(47, 1),
  39         PLL_PARAMS(48, 1),
  40         PLL_PARAMS(49, 1),
  41         PLL_PARAMS(50, 1),
  42         PLL_PARAMS(51, 1),
  43         PLL_PARAMS(52, 1),
  44         PLL_PARAMS(53, 1),
  45         PLL_PARAMS(54, 1),
  46         PLL_PARAMS(55, 1),
  47         PLL_PARAMS(56, 1),
  48         PLL_PARAMS(57, 1),
  49         PLL_PARAMS(58, 1),
  50         PLL_PARAMS(59, 1),
  51         PLL_PARAMS(60, 1),
  52         PLL_PARAMS(61, 1),
  53         PLL_PARAMS(62, 1),
  54         { /* sentinel */ },
  55 };
  56
  57 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  58         PLL_PARAMS(42, 1),
  59         PLL_PARAMS(43, 1),
  60         PLL_PARAMS(44, 1),
  61         PLL_PARAMS(45, 1),
  62         PLL_PARAMS(46, 1),
  63         PLL_PARAMS(47, 1),
  64         PLL_PARAMS(48, 1),
  65         PLL_PARAMS(49, 1),
  66         PLL_PARAMS(50, 1),
  67         PLL_PARAMS(51, 1),
  68         PLL_PARAMS(52, 1),
  69         PLL_PARAMS(53, 1),
  70         PLL_PARAMS(54, 1),
  71         PLL_PARAMS(55, 1),
  72         PLL_PARAMS(56, 1),
  73         PLL_PARAMS(57, 1),
  74         PLL_PARAMS(58, 1),
  75         PLL_PARAMS(59, 1),
  76         PLL_PARAMS(60, 1),
  77         PLL_PARAMS(61, 1),
  78         PLL_PARAMS(62, 1),
  79         PLL_PARAMS(63, 1),
  80         PLL_PARAMS(64, 1),
  81         PLL_PARAMS(65, 1),
  82         PLL_PARAMS(66, 1),
  83         { /* sentinel */ },
  84 };
  85
  86 static struct clk_regmap gxbb_fixed_pll_dco = {
  87         .data = &(struct meson_clk_pll_data){
  88                 .en = {
  89                         .reg_off = HHI_MPLL_CNTL,
  90                         .shift   = 30,
  91                         .width   = 1,
  92                 },
  93                 .m = {
  94                         .reg_off = HHI_MPLL_CNTL,
  95                         .shift   = 0,
  96                         .width   = 9,
  97                 },
  98                 .n = {
  99                         .reg_off = HHI_MPLL_CNTL,
 100                         .shift   = 9,
 101                         .width   = 5,
 102                 },
 103                 .frac = {
 104                         .reg_off = HHI_MPLL_CNTL2,
 105                         .shift   = 0,
 106                         .width   = 12,
 107                 },
 108                 .l = {
 109                         .reg_off = HHI_MPLL_CNTL,
 110                         .shift   = 31,
 111                         .width   = 1,
 112                 },
 113                 .rst = {
 114                         .reg_off = HHI_MPLL_CNTL,
 115                         .shift   = 29,
 116                         .width   = 1,
 117                 },
 118         },
 119         .hw.init = &(struct clk_init_data){
 120                 .name = "fixed_pll_dco",
 121                 .ops = &meson_clk_pll_ro_ops,
 122                 .parent_data = &(const struct clk_parent_data) {
 123                         .fw_name = "xtal",
 124                 },
 125                 .num_parents = 1,
 126         },
 127 };
 128
 129 static struct clk_regmap gxbb_fixed_pll = {
 130         .data = &(struct clk_regmap_div_data){
 131                 .offset = HHI_MPLL_CNTL,
 132                 .shift = 16,
 133                 .width = 2,
 134                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 135         },
 136         .hw.init = &(struct clk_init_data){
 137                 .name = "fixed_pll",
 138                 .ops = &clk_regmap_divider_ro_ops,
 139                 .parent_hws = (const struct clk_hw *[]) {
 140                         &gxbb_fixed_pll_dco.hw
 141                 },
 142                 .num_parents = 1,
 143                 /*
 144                  * This clock won't ever change at runtime so
 145                  * CLK_SET_RATE_PARENT is not required
 146                  */
 147         },
 148 };
 149
 150 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 151         .mult = 2,
 152         .div = 1,
 153         .hw.init = &(struct clk_init_data){
 154                 .name = "hdmi_pll_pre_mult",
 155                 .ops = &clk_fixed_factor_ops,
 156                 .parent_data = &(const struct clk_parent_data) {
 157                         .fw_name = "xtal",
 158                 },
 159                 .num_parents = 1,
 160         },
 161 };
 162
 163 static struct clk_regmap gxbb_hdmi_pll_dco = {
 164         .data = &(struct meson_clk_pll_data){
 165                 .en = {
 166                         .reg_off = HHI_HDMI_PLL_CNTL,
 167                         .shift   = 30,
 168                         .width   = 1,
 169                 },
 170                 .m = {
 171                         .reg_off = HHI_HDMI_PLL_CNTL,
 172                         .shift   = 0,
 173                         .width   = 9,
 174                 },
 175                 .n = {
 176                         .reg_off = HHI_HDMI_PLL_CNTL,
 177                         .shift   = 9,
 178                         .width   = 5,
 179                 },
 180                 .frac = {
 181                         .reg_off = HHI_HDMI_PLL_CNTL2,
 182                         .shift   = 0,
 183                         .width   = 12,
 184                 },
 185                 .l = {
 186                         .reg_off = HHI_HDMI_PLL_CNTL,
 187                         .shift   = 31,
 188                         .width   = 1,
 189                 },
 190                 .rst = {
 191                         .reg_off = HHI_HDMI_PLL_CNTL,
 192                         .shift   = 28,
 193                         .width   = 1,
 194                 },
 195         },
 196         .hw.init = &(struct clk_init_data){
 197                 .name = "hdmi_pll_dco",
 198                 .ops = &meson_clk_pll_ro_ops,
 199                 .parent_hws = (const struct clk_hw *[]) {
 200                         &gxbb_hdmi_pll_pre_mult.hw
 201                 },
 202                 .num_parents = 1,
 203                 /*
 204                  * Display directly handle hdmi pll registers ATM, we need
 205                  * NOCACHE to keep our view of the clock as accurate as possible
 206                  */
 207                 .flags = CLK_GET_RATE_NOCACHE,
 208         },
 209 };
 210
 211 static struct clk_regmap gxl_hdmi_pll_dco = {
 212         .data = &(struct meson_clk_pll_data){
 213                 .en = {
 214                         .reg_off = HHI_HDMI_PLL_CNTL,
 215                         .shift   = 30,
 216                         .width   = 1,
 217                 },
 218                 .m = {
 219                         .reg_off = HHI_HDMI_PLL_CNTL,
 220                         .shift   = 0,
 221                         .width   = 9,
 222                 },
 223                 .n = {
 224                         .reg_off = HHI_HDMI_PLL_CNTL,
 225                         .shift   = 9,
 226                         .width   = 5,
 227                 },
 228                 /*
 229                  * On gxl, there is a register shift due to
 230                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 231                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 232                  * instead which is defined at the same offset.
 233                  */
 234                 .frac = {
 235                         .reg_off = HHI_HDMI_PLL_CNTL2,
 236                         .shift   = 0,
 237                         .width   = 10,
 238                 },
 239                 .l = {
 240                         .reg_off = HHI_HDMI_PLL_CNTL,
 241                         .shift   = 31,
 242                         .width   = 1,
 243                 },
 244                 .rst = {
 245                         .reg_off = HHI_HDMI_PLL_CNTL,
 246                         .shift   = 28,
 247                         .width   = 1,
 248                 },
 249         },
 250         .hw.init = &(struct clk_init_data){
 251                 .name = "hdmi_pll_dco",
 252                 .ops = &meson_clk_pll_ro_ops,
 253                 .parent_data = &(const struct clk_parent_data) {
 254                         .fw_name = "xtal",
 255                 },
 256                 .num_parents = 1,
 257                 /*
 258                  * Display directly handle hdmi pll registers ATM, we need
 259                  * NOCACHE to keep our view of the clock as accurate as possible
 260                  */
 261                 .flags = CLK_GET_RATE_NOCACHE,
 262         },
 263 };
 264
 265 static struct clk_regmap gxbb_hdmi_pll_od = {
 266         .data = &(struct clk_regmap_div_data){
 267                 .offset = HHI_HDMI_PLL_CNTL2,
 268                 .shift = 16,
 269                 .width = 2,
 270                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 271         },
 272         .hw.init = &(struct clk_init_data){
 273                 .name = "hdmi_pll_od",
 274                 .ops = &clk_regmap_divider_ro_ops,
 275                 .parent_hws = (const struct clk_hw *[]) {
 276                         &gxbb_hdmi_pll_dco.hw
 277                 },
 278                 .num_parents = 1,
 279                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 280         },
 281 };
 282
 283 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 284         .data = &(struct clk_regmap_div_data){
 285                 .offset = HHI_HDMI_PLL_CNTL2,
 286                 .shift = 22,
 287                 .width = 2,
 288                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 289         },
 290         .hw.init = &(struct clk_init_data){
 291                 .name = "hdmi_pll_od2",
 292                 .ops = &clk_regmap_divider_ro_ops,
 293                 .parent_hws = (const struct clk_hw *[]) {
 294                         &gxbb_hdmi_pll_od.hw
 295                 },
 296                 .num_parents = 1,
 297                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 298         },
 299 };
 300
 301 static struct clk_regmap gxbb_hdmi_pll = {
 302         .data = &(struct clk_regmap_div_data){
 303                 .offset = HHI_HDMI_PLL_CNTL2,
 304                 .shift = 18,
 305                 .width = 2,
 306                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 307         },
 308         .hw.init = &(struct clk_init_data){
 309                 .name = "hdmi_pll",
 310                 .ops = &clk_regmap_divider_ro_ops,
 311                 .parent_hws = (const struct clk_hw *[]) {
 312                         &gxbb_hdmi_pll_od2.hw
 313                 },
 314                 .num_parents = 1,
 315                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 316         },
 317 };
 318
 319 static struct clk_regmap gxl_hdmi_pll_od = {
 320         .data = &(struct clk_regmap_div_data){
 321                 .offset = HHI_HDMI_PLL_CNTL + 8,
 322                 .shift = 21,
 323                 .width = 2,
 324                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 325         },
 326         .hw.init = &(struct clk_init_data){
 327                 .name = "hdmi_pll_od",
 328                 .ops = &clk_regmap_divider_ro_ops,
 329                 .parent_hws = (const struct clk_hw *[]) {
 330                         &gxl_hdmi_pll_dco.hw
 331                 },
 332                 .num_parents = 1,
 333                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 334         },
 335 };
 336
 337 static struct clk_regmap gxl_hdmi_pll_od2 = {
 338         .data = &(struct clk_regmap_div_data){
 339                 .offset = HHI_HDMI_PLL_CNTL + 8,
 340                 .shift = 23,
 341                 .width = 2,
 342                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 343         },
 344         .hw.init = &(struct clk_init_data){
 345                 .name = "hdmi_pll_od2",
 346                 .ops = &clk_regmap_divider_ro_ops,
 347                 .parent_hws = (const struct clk_hw *[]) {
 348                         &gxl_hdmi_pll_od.hw
 349                 },
 350                 .num_parents = 1,
 351                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 352         },
 353 };
 354
 355 static struct clk_regmap gxl_hdmi_pll = {
 356         .data = &(struct clk_regmap_div_data){
 357                 .offset = HHI_HDMI_PLL_CNTL + 8,
 358                 .shift = 19,
 359                 .width = 2,
 360                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 361         },
 362         .hw.init = &(struct clk_init_data){
 363                 .name = "hdmi_pll",
 364                 .ops = &clk_regmap_divider_ro_ops,
 365                 .parent_hws = (const struct clk_hw *[]) {
 366                         &gxl_hdmi_pll_od2.hw
 367                 },
 368                 .num_parents = 1,
 369                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 370         },
 371 };
 372
 373 static struct clk_regmap gxbb_sys_pll_dco = {
 374         .data = &(struct meson_clk_pll_data){
 375                 .en = {
 376                         .reg_off = HHI_SYS_PLL_CNTL,
 377                         .shift   = 30,
 378                         .width   = 1,
 379                 },
 380                 .m = {
 381                         .reg_off = HHI_SYS_PLL_CNTL,
 382                         .shift   = 0,
 383                         .width   = 9,
 384                 },
 385                 .n = {
 386                         .reg_off = HHI_SYS_PLL_CNTL,
 387                         .shift   = 9,
 388                         .width   = 5,
 389                 },
 390                 .l = {
 391                         .reg_off = HHI_SYS_PLL_CNTL,
 392                         .shift   = 31,
 393                         .width   = 1,
 394                 },
 395                 .rst = {
 396                         .reg_off = HHI_SYS_PLL_CNTL,
 397                         .shift   = 29,
 398                         .width   = 1,
 399                 },
 400         },
 401         .hw.init = &(struct clk_init_data){
 402                 .name = "sys_pll_dco",
 403                 .ops = &meson_clk_pll_ro_ops,
 404                 .parent_data = &(const struct clk_parent_data) {
 405                         .fw_name = "xtal",
 406                 },
 407                 .num_parents = 1,
 408         },
 409 };
 410
 411 static struct clk_regmap gxbb_sys_pll = {
 412         .data = &(struct clk_regmap_div_data){
 413                 .offset = HHI_SYS_PLL_CNTL,
 414                 .shift = 10,
 415                 .width = 2,
 416                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 417         },
 418         .hw.init = &(struct clk_init_data){
 419                 .name = "sys_pll",
 420                 .ops = &clk_regmap_divider_ro_ops,
 421                 .parent_hws = (const struct clk_hw *[]) {
 422                         &gxbb_sys_pll_dco.hw
 423                 },
 424                 .num_parents = 1,
 425                 .flags = CLK_SET_RATE_PARENT,
 426         },
 427 };
 428
 429 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 430         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 431         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 432         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 433 };
 434
 435 static struct clk_regmap gxbb_gp0_pll_dco = {
 436         .data = &(struct meson_clk_pll_data){
 437                 .en = {
 438                         .reg_off = HHI_GP0_PLL_CNTL,
 439                         .shift   = 30,
 440                         .width   = 1,
 441                 },
 442                 .m = {
 443                         .reg_off = HHI_GP0_PLL_CNTL,
 444                         .shift   = 0,
 445                         .width   = 9,
 446                 },
 447                 .n = {
 448                         .reg_off = HHI_GP0_PLL_CNTL,
 449                         .shift   = 9,
 450                         .width   = 5,
 451                 },
 452                 .l = {
 453                         .reg_off = HHI_GP0_PLL_CNTL,
 454                         .shift   = 31,
 455                         .width   = 1,
 456                 },
 457                 .rst = {
 458                         .reg_off = HHI_GP0_PLL_CNTL,
 459                         .shift   = 29,
 460                         .width   = 1,
 461                 },
 462                 .table = gxbb_gp0_pll_params_table,
 463                 .init_regs = gxbb_gp0_init_regs,
 464                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 465         },
 466         .hw.init = &(struct clk_init_data){
 467                 .name = "gp0_pll_dco",
 468                 .ops = &meson_clk_pll_ops,
 469                 .parent_data = &(const struct clk_parent_data) {
 470                         .fw_name = "xtal",
 471                 },
 472                 .num_parents = 1,
 473         },
 474 };
 475
 476 static const struct reg_sequence gxl_gp0_init_regs[] = {
 477         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 478         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 479         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 480         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 481         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 482 };
 483
 484 static struct clk_regmap gxl_gp0_pll_dco = {
 485         .data = &(struct meson_clk_pll_data){
 486                 .en = {
 487                         .reg_off = HHI_GP0_PLL_CNTL,
 488                         .shift   = 30,
 489                         .width   = 1,
 490                 },
 491                 .m = {
 492                         .reg_off = HHI_GP0_PLL_CNTL,
 493                         .shift   = 0,
 494                         .width   = 9,
 495                 },
 496                 .n = {
 497                         .reg_off = HHI_GP0_PLL_CNTL,
 498                         .shift   = 9,
 499                         .width   = 5,
 500                 },
 501                 .frac = {
 502                         .reg_off = HHI_GP0_PLL_CNTL1,
 503                         .shift   = 0,
 504                         .width   = 10,
 505                 },
 506                 .l = {
 507                         .reg_off = HHI_GP0_PLL_CNTL,
 508                         .shift   = 31,
 509                         .width   = 1,
 510                 },
 511                 .rst = {
 512                         .reg_off = HHI_GP0_PLL_CNTL,
 513                         .shift   = 29,
 514                         .width   = 1,
 515                 },
 516                 .table = gxl_gp0_pll_params_table,
 517                 .init_regs = gxl_gp0_init_regs,
 518                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 519         },
 520         .hw.init = &(struct clk_init_data){
 521                 .name = "gp0_pll_dco",
 522                 .ops = &meson_clk_pll_ops,
 523                 .parent_data = &(const struct clk_parent_data) {
 524                         .fw_name = "xtal",
 525                 },
 526                 .num_parents = 1,
 527         },
 528 };
 529
 530 static struct clk_regmap gxbb_gp0_pll = {
 531         .data = &(struct clk_regmap_div_data){
 532                 .offset = HHI_GP0_PLL_CNTL,
 533                 .shift = 16,
 534                 .width = 2,
 535                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 536         },
 537         .hw.init = &(struct clk_init_data){
 538                 .name = "gp0_pll",
 539                 .ops = &clk_regmap_divider_ops,
 540                 .parent_data = &(const struct clk_parent_data) {
 541                         /*
 542                          * Note:
 543                          * GXL and GXBB have different gp0_pll_dco (with
 544                          * different struct clk_hw). We fallback to the global
 545                          * naming string mechanism so gp0_pll picks up the
 546                          * appropriate one.
 547                          */
 548                         .name = "gp0_pll_dco",
 549                         .index = -1,
 550                 },
 551                 .num_parents = 1,
 552                 .flags = CLK_SET_RATE_PARENT,
 553         },
 554 };
 555
 556 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 557         .mult = 1,
 558         .div = 2,
 559         .hw.init = &(struct clk_init_data){
 560                 .name = "fclk_div2_div",
 561                 .ops = &clk_fixed_factor_ops,
 562                 .parent_hws = (const struct clk_hw *[]) {
 563                         &gxbb_fixed_pll.hw
 564                 },
 565                 .num_parents = 1,
 566         },
 567 };
 568
 569 static struct clk_regmap gxbb_fclk_div2 = {
 570         .data = &(struct clk_regmap_gate_data){
 571                 .offset = HHI_MPLL_CNTL6,
 572                 .bit_idx = 27,
 573         },
 574         .hw.init = &(struct clk_init_data){
 575                 .name = "fclk_div2",
 576                 .ops = &clk_regmap_gate_ops,
 577                 .parent_hws = (const struct clk_hw *[]) {
 578                         &gxbb_fclk_div2_div.hw
 579                 },
 580                 .num_parents = 1,
 581                 .flags = CLK_IS_CRITICAL,
 582         },
 583 };
 584
 585 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 586         .mult = 1,
 587         .div = 3,
 588         .hw.init = &(struct clk_init_data){
 589                 .name = "fclk_div3_div",
 590                 .ops = &clk_fixed_factor_ops,
 591                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 592                 .num_parents = 1,
 593         },
 594 };
 595
 596 static struct clk_regmap gxbb_fclk_div3 = {
 597         .data = &(struct clk_regmap_gate_data){
 598                 .offset = HHI_MPLL_CNTL6,
 599                 .bit_idx = 28,
 600         },
 601         .hw.init = &(struct clk_init_data){
 602                 .name = "fclk_div3",
 603                 .ops = &clk_regmap_gate_ops,
 604                 .parent_hws = (const struct clk_hw *[]) {
 605                         &gxbb_fclk_div3_div.hw
 606                 },
 607                 .num_parents = 1,
 608                 /*
 609                  * FIXME:
 610                  * This clock, as fdiv2, is used by the SCPI FW and is required
 611                  * by the platform to operate correctly.
 612                  * Until the following condition are met, we need this clock to
 613                  * be marked as critical:
 614                  * a) The SCPI generic driver claims and enable all the clocks
 615                  *    it needs
 616                  * b) CCF has a clock hand-off mechanism to make the sure the
 617                  *    clock stays on until the proper driver comes along
 618                  */
 619                 .flags = CLK_IS_CRITICAL,
 620         },
 621 };
 622
 623 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 624         .mult = 1,
 625         .div = 4,
 626         .hw.init = &(struct clk_init_data){
 627                 .name = "fclk_div4_div",
 628                 .ops = &clk_fixed_factor_ops,
 629                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 630                 .num_parents = 1,
 631         },
 632 };
 633
 634 static struct clk_regmap gxbb_fclk_div4 = {
 635         .data = &(struct clk_regmap_gate_data){
 636                 .offset = HHI_MPLL_CNTL6,
 637                 .bit_idx = 29,
 638         },
 639         .hw.init = &(struct clk_init_data){
 640                 .name = "fclk_div4",
 641                 .ops = &clk_regmap_gate_ops,
 642                 .parent_hws = (const struct clk_hw *[]) {
 643                         &gxbb_fclk_div4_div.hw
 644                 },
 645                 .num_parents = 1,
 646         },
 647 };
 648
 649 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 650         .mult = 1,
 651         .div = 5,
 652         .hw.init = &(struct clk_init_data){
 653                 .name = "fclk_div5_div",
 654                 .ops = &clk_fixed_factor_ops,
 655                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 656                 .num_parents = 1,
 657         },
 658 };
 659
 660 static struct clk_regmap gxbb_fclk_div5 = {
 661         .data = &(struct clk_regmap_gate_data){
 662                 .offset = HHI_MPLL_CNTL6,
 663                 .bit_idx = 30,
 664         },
 665         .hw.init = &(struct clk_init_data){
 666                 .name = "fclk_div5",
 667                 .ops = &clk_regmap_gate_ops,
 668                 .parent_hws = (const struct clk_hw *[]) {
 669                         &gxbb_fclk_div5_div.hw
 670                 },
 671                 .num_parents = 1,
 672         },
 673 };
 674
 675 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 676         .mult = 1,
 677         .div = 7,
 678         .hw.init = &(struct clk_init_data){
 679                 .name = "fclk_div7_div",
 680                 .ops = &clk_fixed_factor_ops,
 681                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 682                 .num_parents = 1,
 683         },
 684 };
 685
 686 static struct clk_regmap gxbb_fclk_div7 = {
 687         .data = &(struct clk_regmap_gate_data){
 688                 .offset = HHI_MPLL_CNTL6,
 689                 .bit_idx = 31,
 690         },
 691         .hw.init = &(struct clk_init_data){
 692                 .name = "fclk_div7",
 693                 .ops = &clk_regmap_gate_ops,
 694                 .parent_hws = (const struct clk_hw *[]) {
 695                         &gxbb_fclk_div7_div.hw
 696                 },
 697                 .num_parents = 1,
 698         },
 699 };
 700
 701 static struct clk_regmap gxbb_mpll_prediv = {
 702         .data = &(struct clk_regmap_div_data){
 703                 .offset = HHI_MPLL_CNTL5,
 704                 .shift = 12,
 705                 .width = 1,
 706         },
 707         .hw.init = &(struct clk_init_data){
 708                 .name = "mpll_prediv",
 709                 .ops = &clk_regmap_divider_ro_ops,
 710                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 711                 .num_parents = 1,
 712         },
 713 };
 714
 715 static struct clk_regmap gxbb_mpll0_div = {
 716         .data = &(struct meson_clk_mpll_data){
 717                 .sdm = {
 718                         .reg_off = HHI_MPLL_CNTL7,
 719                         .shift   = 0,
 720                         .width   = 14,
 721                 },
 722                 .sdm_en = {
 723                         .reg_off = HHI_MPLL_CNTL7,
 724                         .shift   = 15,
 725                         .width   = 1,
 726                 },
 727                 .n2 = {
 728                         .reg_off = HHI_MPLL_CNTL7,
 729                         .shift   = 16,
 730                         .width   = 9,
 731                 },
 732                 .lock = &meson_clk_lock,
 733         },
 734         .hw.init = &(struct clk_init_data){
 735                 .name = "mpll0_div",
 736                 .ops = &meson_clk_mpll_ops,
 737                 .parent_hws = (const struct clk_hw *[]) {
 738                         &gxbb_mpll_prediv.hw
 739                 },
 740                 .num_parents = 1,
 741         },
 742 };
 743
 744 static struct clk_regmap gxbb_mpll0 = {
 745         .data = &(struct clk_regmap_gate_data){
 746                 .offset = HHI_MPLL_CNTL7,
 747                 .bit_idx = 14,
 748         },
 749         .hw.init = &(struct clk_init_data){
 750                 .name = "mpll0",
 751                 .ops = &clk_regmap_gate_ops,
 752                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
 753                 .num_parents = 1,
 754                 .flags = CLK_SET_RATE_PARENT,
 755         },
 756 };
 757
 758 static struct clk_regmap gxbb_mpll1_div = {
 759         .data = &(struct meson_clk_mpll_data){
 760                 .sdm = {
 761                         .reg_off = HHI_MPLL_CNTL8,
 762                         .shift   = 0,
 763                         .width   = 14,
 764                 },
 765                 .sdm_en = {
 766                         .reg_off = HHI_MPLL_CNTL8,
 767                         .shift   = 15,
 768                         .width   = 1,
 769                 },
 770                 .n2 = {
 771                         .reg_off = HHI_MPLL_CNTL8,
 772                         .shift   = 16,
 773                         .width   = 9,
 774                 },
 775                 .lock = &meson_clk_lock,
 776         },
 777         .hw.init = &(struct clk_init_data){
 778                 .name = "mpll1_div",
 779                 .ops = &meson_clk_mpll_ops,
 780                 .parent_hws = (const struct clk_hw *[]) {
 781                         &gxbb_mpll_prediv.hw
 782                 },
 783                 .num_parents = 1,
 784         },
 785 };
 786
 787 static struct clk_regmap gxbb_mpll1 = {
 788         .data = &(struct clk_regmap_gate_data){
 789                 .offset = HHI_MPLL_CNTL8,
 790                 .bit_idx = 14,
 791         },
 792         .hw.init = &(struct clk_init_data){
 793                 .name = "mpll1",
 794                 .ops = &clk_regmap_gate_ops,
 795                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
 796                 .num_parents = 1,
 797                 .flags = CLK_SET_RATE_PARENT,
 798         },
 799 };
 800
 801 static struct clk_regmap gxbb_mpll2_div = {
 802         .data = &(struct meson_clk_mpll_data){
 803                 .sdm = {
 804                         .reg_off = HHI_MPLL_CNTL9,
 805                         .shift   = 0,
 806                         .width   = 14,
 807                 },
 808                 .sdm_en = {
 809                         .reg_off = HHI_MPLL_CNTL9,
 810                         .shift   = 15,
 811                         .width   = 1,
 812                 },
 813                 .n2 = {
 814                         .reg_off = HHI_MPLL_CNTL9,
 815                         .shift   = 16,
 816                         .width   = 9,
 817                 },
 818                 .lock = &meson_clk_lock,
 819         },
 820         .hw.init = &(struct clk_init_data){
 821                 .name = "mpll2_div",
 822                 .ops = &meson_clk_mpll_ops,
 823                 .parent_hws = (const struct clk_hw *[]) {
 824                         &gxbb_mpll_prediv.hw
 825                 },
 826                 .num_parents = 1,
 827         },
 828 };
 829
 830 static struct clk_regmap gxbb_mpll2 = {
 831         .data = &(struct clk_regmap_gate_data){
 832                 .offset = HHI_MPLL_CNTL9,
 833                 .bit_idx = 14,
 834         },
 835         .hw.init = &(struct clk_init_data){
 836                 .name = "mpll2",
 837                 .ops = &clk_regmap_gate_ops,
 838                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
 839                 .num_parents = 1,
 840                 .flags = CLK_SET_RATE_PARENT,
 841         },
 842 };
 843
 844 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 845 static const struct clk_parent_data clk81_parent_data[] = {
 846         { .fw_name = "xtal", },
 847         { .hw = &gxbb_fclk_div7.hw },
 848         { .hw = &gxbb_mpll1.hw },
 849         { .hw = &gxbb_mpll2.hw },
 850         { .hw = &gxbb_fclk_div4.hw },
 851         { .hw = &gxbb_fclk_div3.hw },
 852         { .hw = &gxbb_fclk_div5.hw },
 853 };
 854
 855 static struct clk_regmap gxbb_mpeg_clk_sel = {
 856         .data = &(struct clk_regmap_mux_data){
 857                 .offset = HHI_MPEG_CLK_CNTL,
 858                 .mask = 0x7,
 859                 .shift = 12,
 860                 .table = mux_table_clk81,
 861         },
 862         .hw.init = &(struct clk_init_data){
 863                 .name = "mpeg_clk_sel",
 864                 .ops = &clk_regmap_mux_ro_ops,
 865                 /*
 866                  * bits 14:12 selects from 8 possible parents:
 867                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 868                  * fclk_div4, fclk_div3, fclk_div5
 869                  */
 870                 .parent_data = clk81_parent_data,
 871                 .num_parents = ARRAY_SIZE(clk81_parent_data),
 872         },
 873 };
 874
 875 static struct clk_regmap gxbb_mpeg_clk_div = {
 876         .data = &(struct clk_regmap_div_data){
 877                 .offset = HHI_MPEG_CLK_CNTL,
 878                 .shift = 0,
 879                 .width = 7,
 880         },
 881         .hw.init = &(struct clk_init_data){
 882                 .name = "mpeg_clk_div",
 883                 .ops = &clk_regmap_divider_ro_ops,
 884                 .parent_hws = (const struct clk_hw *[]) {
 885                         &gxbb_mpeg_clk_sel.hw
 886                 },
 887                 .num_parents = 1,
 888         },
 889 };
 890
 891 /* the mother of dragons gates */
 892 static struct clk_regmap gxbb_clk81 = {
 893         .data = &(struct clk_regmap_gate_data){
 894                 .offset = HHI_MPEG_CLK_CNTL,
 895                 .bit_idx = 7,
 896         },
 897         .hw.init = &(struct clk_init_data){
 898                 .name = "clk81",
 899                 .ops = &clk_regmap_gate_ops,
 900                 .parent_hws = (const struct clk_hw *[]) {
 901                         &gxbb_mpeg_clk_div.hw
 902                 },
 903                 .num_parents = 1,
 904                 .flags = CLK_IS_CRITICAL,
 905         },
 906 };
 907
 908 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 909         .data = &(struct clk_regmap_mux_data){
 910                 .offset = HHI_SAR_CLK_CNTL,
 911                 .mask = 0x3,
 912                 .shift = 9,
 913         },
 914         .hw.init = &(struct clk_init_data){
 915                 .name = "sar_adc_clk_sel",
 916                 .ops = &clk_regmap_mux_ops,
 917                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 918                 .parent_data = (const struct clk_parent_data []) {
 919                         { .fw_name = "xtal", },
 920                         { .hw = &gxbb_clk81.hw },
 921                 },
 922                 .num_parents = 2,
 923         },
 924 };
 925
 926 static struct clk_regmap gxbb_sar_adc_clk_div = {
 927         .data = &(struct clk_regmap_div_data){
 928                 .offset = HHI_SAR_CLK_CNTL,
 929                 .shift = 0,
 930                 .width = 8,
 931         },
 932         .hw.init = &(struct clk_init_data){
 933                 .name = "sar_adc_clk_div",
 934                 .ops = &clk_regmap_divider_ops,
 935                 .parent_hws = (const struct clk_hw *[]) {
 936                         &gxbb_sar_adc_clk_sel.hw
 937                 },
 938                 .num_parents = 1,
 939                 .flags = CLK_SET_RATE_PARENT,
 940         },
 941 };
 942
 943 static struct clk_regmap gxbb_sar_adc_clk = {
 944         .data = &(struct clk_regmap_gate_data){
 945                 .offset = HHI_SAR_CLK_CNTL,
 946                 .bit_idx = 8,
 947         },
 948         .hw.init = &(struct clk_init_data){
 949                 .name = "sar_adc_clk",
 950                 .ops = &clk_regmap_gate_ops,
 951                 .parent_hws = (const struct clk_hw *[]) {
 952                         &gxbb_sar_adc_clk_div.hw
 953                 },
 954                 .num_parents = 1,
 955                 .flags = CLK_SET_RATE_PARENT,
 956         },
 957 };
 958
 959 /*
 960  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 961  * muxed by a glitch-free switch. The CCF can manage this glitch-free
 962  * mux because it does top-to-bottom updates the each clock tree and
 963  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
 964  */
 965
 966 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
 967         { .fw_name = "xtal", },
 968         { .hw = &gxbb_gp0_pll.hw },
 969         { .hw = &gxbb_mpll2.hw },
 970         { .hw = &gxbb_mpll1.hw },
 971         { .hw = &gxbb_fclk_div7.hw },
 972         { .hw = &gxbb_fclk_div4.hw },
 973         { .hw = &gxbb_fclk_div3.hw },
 974         { .hw = &gxbb_fclk_div5.hw },
 975 };
 976
 977 static struct clk_regmap gxbb_mali_0_sel = {
 978         .data = &(struct clk_regmap_mux_data){
 979                 .offset = HHI_MALI_CLK_CNTL,
 980                 .mask = 0x7,
 981                 .shift = 9,
 982         },
 983         .hw.init = &(struct clk_init_data){
 984                 .name = "mali_0_sel",
 985                 .ops = &clk_regmap_mux_ops,
 986                 .parent_data = gxbb_mali_0_1_parent_data,
 987                 .num_parents = 8,
 988                 /*
 989                  * Don't request the parent to change the rate because
 990                  * all GPU frequencies can be derived from the fclk_*
 991                  * clocks and one special GP0_PLL setting. This is
 992                  * important because we need the MPLL clocks for audio.
 993                  */
 994                 .flags = 0,
 995         },
 996 };
 997
 998 static struct clk_regmap gxbb_mali_0_div = {
 999         .data = &(struct clk_regmap_div_data){
1000                 .offset = HHI_MALI_CLK_CNTL,
1001                 .shift = 0,
1002                 .width = 7,
1003         },
1004         .hw.init = &(struct clk_init_data){
1005                 .name = "mali_0_div",
1006                 .ops = &clk_regmap_divider_ops,
1007                 .parent_hws = (const struct clk_hw *[]) {
1008                         &gxbb_mali_0_sel.hw
1009                 },
1010                 .num_parents = 1,
1011                 .flags = CLK_SET_RATE_PARENT,
1012         },
1013 };
1014
1015 static struct clk_regmap gxbb_mali_0 = {
1016         .data = &(struct clk_regmap_gate_data){
1017                 .offset = HHI_MALI_CLK_CNTL,
1018                 .bit_idx = 8,
1019         },
1020         .hw.init = &(struct clk_init_data){
1021                 .name = "mali_0",
1022                 .ops = &clk_regmap_gate_ops,
1023                 .parent_hws = (const struct clk_hw *[]) {
1024                         &gxbb_mali_0_div.hw
1025                 },
1026                 .num_parents = 1,
1027                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1028         },
1029 };
1030
1031 static struct clk_regmap gxbb_mali_1_sel = {
1032         .data = &(struct clk_regmap_mux_data){
1033                 .offset = HHI_MALI_CLK_CNTL,
1034                 .mask = 0x7,
1035                 .shift = 25,
1036         },
1037         .hw.init = &(struct clk_init_data){
1038                 .name = "mali_1_sel",
1039                 .ops = &clk_regmap_mux_ops,
1040                 .parent_data = gxbb_mali_0_1_parent_data,
1041                 .num_parents = 8,
1042                 /*
1043                  * Don't request the parent to change the rate because
1044                  * all GPU frequencies can be derived from the fclk_*
1045                  * clocks and one special GP0_PLL setting. This is
1046                  * important because we need the MPLL clocks for audio.
1047                  */
1048                 .flags = 0,
1049         },
1050 };
1051
1052 static struct clk_regmap gxbb_mali_1_div = {
1053         .data = &(struct clk_regmap_div_data){
1054                 .offset = HHI_MALI_CLK_CNTL,
1055                 .shift = 16,
1056                 .width = 7,
1057         },
1058         .hw.init = &(struct clk_init_data){
1059                 .name = "mali_1_div",
1060                 .ops = &clk_regmap_divider_ops,
1061                 .parent_hws = (const struct clk_hw *[]) {
1062                         &gxbb_mali_1_sel.hw
1063                 },
1064                 .num_parents = 1,
1065                 .flags = CLK_SET_RATE_PARENT,
1066         },
1067 };
1068
1069 static struct clk_regmap gxbb_mali_1 = {
1070         .data = &(struct clk_regmap_gate_data){
1071                 .offset = HHI_MALI_CLK_CNTL,
1072                 .bit_idx = 24,
1073         },
1074         .hw.init = &(struct clk_init_data){
1075                 .name = "mali_1",
1076                 .ops = &clk_regmap_gate_ops,
1077                 .parent_hws = (const struct clk_hw *[]) {
1078                         &gxbb_mali_1_div.hw
1079                 },
1080                 .num_parents = 1,
1081                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1082         },
1083 };
1084
1085 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1086         &gxbb_mali_0.hw,
1087         &gxbb_mali_1.hw,
1088 };
1089
1090 static struct clk_regmap gxbb_mali = {
1091         .data = &(struct clk_regmap_mux_data){
1092                 .offset = HHI_MALI_CLK_CNTL,
1093                 .mask = 1,
1094                 .shift = 31,
1095         },
1096         .hw.init = &(struct clk_init_data){
1097                 .name = "mali",
1098                 .ops = &clk_regmap_mux_ops,
1099                 .parent_hws = gxbb_mali_parent_hws,
1100                 .num_parents = 2,
1101                 .flags = CLK_SET_RATE_PARENT,
1102         },
1103 };
1104
1105 static struct clk_regmap gxbb_cts_amclk_sel = {
1106         .data = &(struct clk_regmap_mux_data){
1107                 .offset = HHI_AUD_CLK_CNTL,
1108                 .mask = 0x3,
1109                 .shift = 9,
1110                 .table = (u32[]){ 1, 2, 3 },
1111                 .flags = CLK_MUX_ROUND_CLOSEST,
1112         },
1113         .hw.init = &(struct clk_init_data){
1114                 .name = "cts_amclk_sel",
1115                 .ops = &clk_regmap_mux_ops,
1116                 .parent_hws = (const struct clk_hw *[]) {
1117                         &gxbb_mpll0.hw,
1118                         &gxbb_mpll1.hw,
1119                         &gxbb_mpll2.hw,
1120                 },
1121                 .num_parents = 3,
1122         },
1123 };
1124
1125 static struct clk_regmap gxbb_cts_amclk_div = {
1126         .data = &(struct clk_regmap_div_data) {
1127                 .offset = HHI_AUD_CLK_CNTL,
1128                 .shift = 0,
1129                 .width = 8,
1130                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1131         },
1132         .hw.init = &(struct clk_init_data){
1133                 .name = "cts_amclk_div",
1134                 .ops = &clk_regmap_divider_ops,
1135                 .parent_hws = (const struct clk_hw *[]) {
1136                         &gxbb_cts_amclk_sel.hw
1137                 },
1138                 .num_parents = 1,
1139                 .flags = CLK_SET_RATE_PARENT,
1140         },
1141 };
1142
1143 static struct clk_regmap gxbb_cts_amclk = {
1144         .data = &(struct clk_regmap_gate_data){
1145                 .offset = HHI_AUD_CLK_CNTL,
1146                 .bit_idx = 8,
1147         },
1148         .hw.init = &(struct clk_init_data){
1149                 .name = "cts_amclk",
1150                 .ops = &clk_regmap_gate_ops,
1151                 .parent_hws = (const struct clk_hw *[]) {
1152                         &gxbb_cts_amclk_div.hw
1153                 },
1154                 .num_parents = 1,
1155                 .flags = CLK_SET_RATE_PARENT,
1156         },
1157 };
1158
1159 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1160         .data = &(struct clk_regmap_mux_data){
1161                 .offset = HHI_AUD_CLK_CNTL2,
1162                 .mask = 0x3,
1163                 .shift = 25,
1164                 .table = (u32[]){ 1, 2, 3 },
1165                 .flags = CLK_MUX_ROUND_CLOSEST,
1166         },
1167         .hw.init = &(struct clk_init_data) {
1168                 .name = "cts_mclk_i958_sel",
1169                 .ops = &clk_regmap_mux_ops,
1170                 .parent_hws = (const struct clk_hw *[]) {
1171                         &gxbb_mpll0.hw,
1172                         &gxbb_mpll1.hw,
1173                         &gxbb_mpll2.hw,
1174                 },
1175                 .num_parents = 3,
1176         },
1177 };
1178
1179 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1180         .data = &(struct clk_regmap_div_data){
1181                 .offset = HHI_AUD_CLK_CNTL2,
1182                 .shift = 16,
1183                 .width = 8,
1184                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1185         },
1186         .hw.init = &(struct clk_init_data) {
1187                 .name = "cts_mclk_i958_div",
1188                 .ops = &clk_regmap_divider_ops,
1189                 .parent_hws = (const struct clk_hw *[]) {
1190                         &gxbb_cts_mclk_i958_sel.hw
1191                 },
1192                 .num_parents = 1,
1193                 .flags = CLK_SET_RATE_PARENT,
1194         },
1195 };
1196
1197 static struct clk_regmap gxbb_cts_mclk_i958 = {
1198         .data = &(struct clk_regmap_gate_data){
1199                 .offset = HHI_AUD_CLK_CNTL2,
1200                 .bit_idx = 24,
1201         },
1202         .hw.init = &(struct clk_init_data){
1203                 .name = "cts_mclk_i958",
1204                 .ops = &clk_regmap_gate_ops,
1205                 .parent_hws = (const struct clk_hw *[]) {
1206                         &gxbb_cts_mclk_i958_div.hw
1207                 },
1208                 .num_parents = 1,
1209                 .flags = CLK_SET_RATE_PARENT,
1210         },
1211 };
1212
1213 static struct clk_regmap gxbb_cts_i958 = {
1214         .data = &(struct clk_regmap_mux_data){
1215                 .offset = HHI_AUD_CLK_CNTL2,
1216                 .mask = 0x1,
1217                 .shift = 27,
1218                 },
1219         .hw.init = &(struct clk_init_data){
1220                 .name = "cts_i958",
1221                 .ops = &clk_regmap_mux_ops,
1222                 .parent_hws = (const struct clk_hw *[]) {
1223                         &gxbb_cts_amclk.hw,
1224                         &gxbb_cts_mclk_i958.hw
1225                 },
1226                 .num_parents = 2,
1227                 /*
1228                  *The parent is specific to origin of the audio data. Let the
1229                  * consumer choose the appropriate parent
1230                  */
1231                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1232         },
1233 };
1234
1235 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1236         { .fw_name = "xtal", },
1237         /*
1238          * FIXME: This clock is provided by the ao clock controller but the
1239          * clock is not yet part of the binding of this controller, so string
1240          * name must be use to set this parent.
1241          */
1242         { .name = "cts_slow_oscin", .index = -1 },
1243         { .hw = &gxbb_fclk_div3.hw },
1244         { .hw = &gxbb_fclk_div5.hw },
1245 };
1246
1247 static struct clk_regmap gxbb_32k_clk_sel = {
1248         .data = &(struct clk_regmap_mux_data){
1249                 .offset = HHI_32K_CLK_CNTL,
1250                 .mask = 0x3,
1251                 .shift = 16,
1252                 },
1253         .hw.init = &(struct clk_init_data){
1254                 .name = "32k_clk_sel",
1255                 .ops = &clk_regmap_mux_ops,
1256                 .parent_data = gxbb_32k_clk_parent_data,
1257                 .num_parents = 4,
1258                 .flags = CLK_SET_RATE_PARENT,
1259         },
1260 };
1261
1262 static struct clk_regmap gxbb_32k_clk_div = {
1263         .data = &(struct clk_regmap_div_data){
1264                 .offset = HHI_32K_CLK_CNTL,
1265                 .shift = 0,
1266                 .width = 14,
1267         },
1268         .hw.init = &(struct clk_init_data){
1269                 .name = "32k_clk_div",
1270                 .ops = &clk_regmap_divider_ops,
1271                 .parent_hws = (const struct clk_hw *[]) {
1272                         &gxbb_32k_clk_sel.hw
1273                 },
1274                 .num_parents = 1,
1275                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1276         },
1277 };
1278
1279 static struct clk_regmap gxbb_32k_clk = {
1280         .data = &(struct clk_regmap_gate_data){
1281                 .offset = HHI_32K_CLK_CNTL,
1282                 .bit_idx = 15,
1283         },
1284         .hw.init = &(struct clk_init_data){
1285                 .name = "32k_clk",
1286                 .ops = &clk_regmap_gate_ops,
1287                 .parent_hws = (const struct clk_hw *[]) {
1288                         &gxbb_32k_clk_div.hw
1289                 },
1290                 .num_parents = 1,
1291                 .flags = CLK_SET_RATE_PARENT,
1292         },
1293 };
1294
1295 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1296         { .fw_name = "xtal", },
1297         { .hw = &gxbb_fclk_div2.hw },
1298         { .hw = &gxbb_fclk_div3.hw },
1299         { .hw = &gxbb_fclk_div5.hw },
1300         { .hw = &gxbb_fclk_div7.hw },
1301         /*
1302          * Following these parent clocks, we should also have had mpll2, mpll3
1303          * and gp0_pll but these clocks are too precious to be used here. All
1304          * the necessary rates for MMC and NAND operation can be acheived using
1305          * xtal or fclk_div clocks
1306          */
1307 };
1308
1309 /* SDIO clock */
1310 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1311         .data = &(struct clk_regmap_mux_data){
1312                 .offset = HHI_SD_EMMC_CLK_CNTL,
1313                 .mask = 0x7,
1314                 .shift = 9,
1315         },
1316         .hw.init = &(struct clk_init_data) {
1317                 .name = "sd_emmc_a_clk0_sel",
1318                 .ops = &clk_regmap_mux_ops,
1319                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1320                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1321                 .flags = CLK_SET_RATE_PARENT,
1322         },
1323 };
1324
1325 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1326         .data = &(struct clk_regmap_div_data){
1327                 .offset = HHI_SD_EMMC_CLK_CNTL,
1328                 .shift = 0,
1329                 .width = 7,
1330                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1331         },
1332         .hw.init = &(struct clk_init_data) {
1333                 .name = "sd_emmc_a_clk0_div",
1334                 .ops = &clk_regmap_divider_ops,
1335                 .parent_hws = (const struct clk_hw *[]) {
1336                         &gxbb_sd_emmc_a_clk0_sel.hw
1337                 },
1338                 .num_parents = 1,
1339                 .flags = CLK_SET_RATE_PARENT,
1340         },
1341 };
1342
1343 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1344         .data = &(struct clk_regmap_gate_data){
1345                 .offset = HHI_SD_EMMC_CLK_CNTL,
1346                 .bit_idx = 7,
1347         },
1348         .hw.init = &(struct clk_init_data){
1349                 .name = "sd_emmc_a_clk0",
1350                 .ops = &clk_regmap_gate_ops,
1351                 .parent_hws = (const struct clk_hw *[]) {
1352                         &gxbb_sd_emmc_a_clk0_div.hw
1353                 },
1354                 .num_parents = 1,
1355                 .flags = CLK_SET_RATE_PARENT,
1356         },
1357 };
1358
1359 /* SDcard clock */
1360 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1361         .data = &(struct clk_regmap_mux_data){
1362                 .offset = HHI_SD_EMMC_CLK_CNTL,
1363                 .mask = 0x7,
1364                 .shift = 25,
1365         },
1366         .hw.init = &(struct clk_init_data) {
1367                 .name = "sd_emmc_b_clk0_sel",
1368                 .ops = &clk_regmap_mux_ops,
1369                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1370                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1371                 .flags = CLK_SET_RATE_PARENT,
1372         },
1373 };
1374
1375 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1376         .data = &(struct clk_regmap_div_data){
1377                 .offset = HHI_SD_EMMC_CLK_CNTL,
1378                 .shift = 16,
1379                 .width = 7,
1380                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1381         },
1382         .hw.init = &(struct clk_init_data) {
1383                 .name = "sd_emmc_b_clk0_div",
1384                 .ops = &clk_regmap_divider_ops,
1385                 .parent_hws = (const struct clk_hw *[]) {
1386                         &gxbb_sd_emmc_b_clk0_sel.hw
1387                 },
1388                 .num_parents = 1,
1389                 .flags = CLK_SET_RATE_PARENT,
1390         },
1391 };
1392
1393 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1394         .data = &(struct clk_regmap_gate_data){
1395                 .offset = HHI_SD_EMMC_CLK_CNTL,
1396                 .bit_idx = 23,
1397         },
1398         .hw.init = &(struct clk_init_data){
1399                 .name = "sd_emmc_b_clk0",
1400                 .ops = &clk_regmap_gate_ops,
1401                 .parent_hws = (const struct clk_hw *[]) {
1402                         &gxbb_sd_emmc_b_clk0_div.hw
1403                 },
1404                 .num_parents = 1,
1405                 .flags = CLK_SET_RATE_PARENT,
1406         },
1407 };
1408
1409 /* EMMC/NAND clock */
1410 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1411         .data = &(struct clk_regmap_mux_data){
1412                 .offset = HHI_NAND_CLK_CNTL,
1413                 .mask = 0x7,
1414                 .shift = 9,
1415         },
1416         .hw.init = &(struct clk_init_data) {
1417                 .name = "sd_emmc_c_clk0_sel",
1418                 .ops = &clk_regmap_mux_ops,
1419                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1420                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1421                 .flags = CLK_SET_RATE_PARENT,
1422         },
1423 };
1424
1425 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1426         .data = &(struct clk_regmap_div_data){
1427                 .offset = HHI_NAND_CLK_CNTL,
1428                 .shift = 0,
1429                 .width = 7,
1430                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1431         },
1432         .hw.init = &(struct clk_init_data) {
1433                 .name = "sd_emmc_c_clk0_div",
1434                 .ops = &clk_regmap_divider_ops,
1435                 .parent_hws = (const struct clk_hw *[]) {
1436                         &gxbb_sd_emmc_c_clk0_sel.hw
1437                 },
1438                 .num_parents = 1,
1439                 .flags = CLK_SET_RATE_PARENT,
1440         },
1441 };
1442
1443 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1444         .data = &(struct clk_regmap_gate_data){
1445                 .offset = HHI_NAND_CLK_CNTL,
1446                 .bit_idx = 7,
1447         },
1448         .hw.init = &(struct clk_init_data){
1449                 .name = "sd_emmc_c_clk0",
1450                 .ops = &clk_regmap_gate_ops,
1451                 .parent_hws = (const struct clk_hw *[]) {
1452                         &gxbb_sd_emmc_c_clk0_div.hw
1453                 },
1454                 .num_parents = 1,
1455                 .flags = CLK_SET_RATE_PARENT,
1456         },
1457 };
1458
1459 /* VPU Clock */
1460
1461 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1462         &gxbb_fclk_div4.hw,
1463         &gxbb_fclk_div3.hw,
1464         &gxbb_fclk_div5.hw,
1465         &gxbb_fclk_div7.hw,
1466 };
1467
1468 static struct clk_regmap gxbb_vpu_0_sel = {
1469         .data = &(struct clk_regmap_mux_data){
1470                 .offset = HHI_VPU_CLK_CNTL,
1471                 .mask = 0x3,
1472                 .shift = 9,
1473         },
1474         .hw.init = &(struct clk_init_data){
1475                 .name = "vpu_0_sel",
1476                 .ops = &clk_regmap_mux_ops,
1477                 /*
1478                  * bits 9:10 selects from 4 possible parents:
1479                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1480                  */
1481                 .parent_hws = gxbb_vpu_parent_hws,
1482                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1483                 .flags = CLK_SET_RATE_NO_REPARENT,
1484         },
1485 };
1486
1487 static struct clk_regmap gxbb_vpu_0_div = {
1488         .data = &(struct clk_regmap_div_data){
1489                 .offset = HHI_VPU_CLK_CNTL,
1490                 .shift = 0,
1491                 .width = 7,
1492         },
1493         .hw.init = &(struct clk_init_data){
1494                 .name = "vpu_0_div",
1495                 .ops = &clk_regmap_divider_ops,
1496                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1497                 .num_parents = 1,
1498                 .flags = CLK_SET_RATE_PARENT,
1499         },
1500 };
1501
1502 static struct clk_regmap gxbb_vpu_0 = {
1503         .data = &(struct clk_regmap_gate_data){
1504                 .offset = HHI_VPU_CLK_CNTL,
1505                 .bit_idx = 8,
1506         },
1507         .hw.init = &(struct clk_init_data) {
1508                 .name = "vpu_0",
1509                 .ops = &clk_regmap_gate_ops,
1510                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1511                 .num_parents = 1,
1512                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1513         },
1514 };
1515
1516 static struct clk_regmap gxbb_vpu_1_sel = {
1517         .data = &(struct clk_regmap_mux_data){
1518                 .offset = HHI_VPU_CLK_CNTL,
1519                 .mask = 0x3,
1520                 .shift = 25,
1521         },
1522         .hw.init = &(struct clk_init_data){
1523                 .name = "vpu_1_sel",
1524                 .ops = &clk_regmap_mux_ops,
1525                 /*
1526                  * bits 25:26 selects from 4 possible parents:
1527                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1528                  */
1529                 .parent_hws = gxbb_vpu_parent_hws,
1530                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1531                 .flags = CLK_SET_RATE_NO_REPARENT,
1532         },
1533 };
1534
1535 static struct clk_regmap gxbb_vpu_1_div = {
1536         .data = &(struct clk_regmap_div_data){
1537                 .offset = HHI_VPU_CLK_CNTL,
1538                 .shift = 16,
1539                 .width = 7,
1540         },
1541         .hw.init = &(struct clk_init_data){
1542                 .name = "vpu_1_div",
1543                 .ops = &clk_regmap_divider_ops,
1544                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1545                 .num_parents = 1,
1546                 .flags = CLK_SET_RATE_PARENT,
1547         },
1548 };
1549
1550 static struct clk_regmap gxbb_vpu_1 = {
1551         .data = &(struct clk_regmap_gate_data){
1552                 .offset = HHI_VPU_CLK_CNTL,
1553                 .bit_idx = 24,
1554         },
1555         .hw.init = &(struct clk_init_data) {
1556                 .name = "vpu_1",
1557                 .ops = &clk_regmap_gate_ops,
1558                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1559                 .num_parents = 1,
1560                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1561         },
1562 };
1563
1564 static struct clk_regmap gxbb_vpu = {
1565         .data = &(struct clk_regmap_mux_data){
1566                 .offset = HHI_VPU_CLK_CNTL,
1567                 .mask = 1,
1568                 .shift = 31,
1569         },
1570         .hw.init = &(struct clk_init_data){
1571                 .name = "vpu",
1572                 .ops = &clk_regmap_mux_ops,
1573                 /*
1574                  * bit 31 selects from 2 possible parents:
1575                  * vpu_0 or vpu_1
1576                  */
1577                 .parent_hws = (const struct clk_hw *[]) {
1578                         &gxbb_vpu_0.hw,
1579                         &gxbb_vpu_1.hw
1580                 },
1581                 .num_parents = 2,
1582                 .flags = CLK_SET_RATE_NO_REPARENT,
1583         },
1584 };
1585
1586 /* VAPB Clock */
1587
1588 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1589         &gxbb_fclk_div4.hw,
1590         &gxbb_fclk_div3.hw,
1591         &gxbb_fclk_div5.hw,
1592         &gxbb_fclk_div7.hw,
1593 };
1594
1595 static struct clk_regmap gxbb_vapb_0_sel = {
1596         .data = &(struct clk_regmap_mux_data){
1597                 .offset = HHI_VAPBCLK_CNTL,
1598                 .mask = 0x3,
1599                 .shift = 9,
1600         },
1601         .hw.init = &(struct clk_init_data){
1602                 .name = "vapb_0_sel",
1603                 .ops = &clk_regmap_mux_ops,
1604                 /*
1605                  * bits 9:10 selects from 4 possible parents:
1606                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1607                  */
1608                 .parent_hws = gxbb_vapb_parent_hws,
1609                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1610                 .flags = CLK_SET_RATE_NO_REPARENT,
1611         },
1612 };
1613
1614 static struct clk_regmap gxbb_vapb_0_div = {
1615         .data = &(struct clk_regmap_div_data){
1616                 .offset = HHI_VAPBCLK_CNTL,
1617                 .shift = 0,
1618                 .width = 7,
1619         },
1620         .hw.init = &(struct clk_init_data){
1621                 .name = "vapb_0_div",
1622                 .ops = &clk_regmap_divider_ops,
1623                 .parent_hws = (const struct clk_hw *[]) {
1624                         &gxbb_vapb_0_sel.hw
1625                 },
1626                 .num_parents = 1,
1627                 .flags = CLK_SET_RATE_PARENT,
1628         },
1629 };
1630
1631 static struct clk_regmap gxbb_vapb_0 = {
1632         .data = &(struct clk_regmap_gate_data){
1633                 .offset = HHI_VAPBCLK_CNTL,
1634                 .bit_idx = 8,
1635         },
1636         .hw.init = &(struct clk_init_data) {
1637                 .name = "vapb_0",
1638                 .ops = &clk_regmap_gate_ops,
1639                 .parent_hws = (const struct clk_hw *[]) {
1640                         &gxbb_vapb_0_div.hw
1641                 },
1642                 .num_parents = 1,
1643                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1644         },
1645 };
1646
1647 static struct clk_regmap gxbb_vapb_1_sel = {
1648         .data = &(struct clk_regmap_mux_data){
1649                 .offset = HHI_VAPBCLK_CNTL,
1650                 .mask = 0x3,
1651                 .shift = 25,
1652         },
1653         .hw.init = &(struct clk_init_data){
1654                 .name = "vapb_1_sel",
1655                 .ops = &clk_regmap_mux_ops,
1656                 /*
1657                  * bits 25:26 selects from 4 possible parents:
1658                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1659                  */
1660                 .parent_hws = gxbb_vapb_parent_hws,
1661                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1662                 .flags = CLK_SET_RATE_NO_REPARENT,
1663         },
1664 };
1665
1666 static struct clk_regmap gxbb_vapb_1_div = {
1667         .data = &(struct clk_regmap_div_data){
1668                 .offset = HHI_VAPBCLK_CNTL,
1669                 .shift = 16,
1670                 .width = 7,
1671         },
1672         .hw.init = &(struct clk_init_data){
1673                 .name = "vapb_1_div",
1674                 .ops = &clk_regmap_divider_ops,
1675                 .parent_hws = (const struct clk_hw *[]) {
1676                         &gxbb_vapb_1_sel.hw
1677                 },
1678                 .num_parents = 1,
1679                 .flags = CLK_SET_RATE_PARENT,
1680         },
1681 };
1682
1683 static struct clk_regmap gxbb_vapb_1 = {
1684         .data = &(struct clk_regmap_gate_data){
1685                 .offset = HHI_VAPBCLK_CNTL,
1686                 .bit_idx = 24,
1687         },
1688         .hw.init = &(struct clk_init_data) {
1689                 .name = "vapb_1",
1690                 .ops = &clk_regmap_gate_ops,
1691                 .parent_hws = (const struct clk_hw *[]) {
1692                         &gxbb_vapb_1_div.hw
1693                 },
1694                 .num_parents = 1,
1695                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1696         },
1697 };
1698
1699 static struct clk_regmap gxbb_vapb_sel = {
1700         .data = &(struct clk_regmap_mux_data){
1701                 .offset = HHI_VAPBCLK_CNTL,
1702                 .mask = 1,
1703                 .shift = 31,
1704         },
1705         .hw.init = &(struct clk_init_data){
1706                 .name = "vapb_sel",
1707                 .ops = &clk_regmap_mux_ops,
1708                 /*
1709                  * bit 31 selects from 2 possible parents:
1710                  * vapb_0 or vapb_1
1711                  */
1712                 .parent_hws = (const struct clk_hw *[]) {
1713                         &gxbb_vapb_0.hw,
1714                         &gxbb_vapb_1.hw
1715                 },
1716                 .num_parents = 2,
1717                 .flags = CLK_SET_RATE_NO_REPARENT,
1718         },
1719 };
1720
1721 static struct clk_regmap gxbb_vapb = {
1722         .data = &(struct clk_regmap_gate_data){
1723                 .offset = HHI_VAPBCLK_CNTL,
1724                 .bit_idx = 30,
1725         },
1726         .hw.init = &(struct clk_init_data) {
1727                 .name = "vapb",
1728                 .ops = &clk_regmap_gate_ops,
1729                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1730                 .num_parents = 1,
1731                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1732         },
1733 };
1734
1735 /* Video Clocks */
1736
1737 static struct clk_regmap gxbb_vid_pll_div = {
1738         .data = &(struct meson_vid_pll_div_data){
1739                 .val = {
1740                         .reg_off = HHI_VID_PLL_CLK_DIV,
1741                         .shift   = 0,
1742                         .width   = 15,
1743                 },
1744                 .sel = {
1745                         .reg_off = HHI_VID_PLL_CLK_DIV,
1746                         .shift   = 16,
1747                         .width   = 2,
1748                 },
1749         },
1750         .hw.init = &(struct clk_init_data) {
1751                 .name = "vid_pll_div",
1752                 .ops = &meson_vid_pll_div_ro_ops,
1753                 .parent_data = &(const struct clk_parent_data) {
1754                         /*
1755                          * Note:
1756                          * GXL and GXBB have different hdmi_plls (with
1757                          * different struct clk_hw). We fallback to the global
1758                          * naming string mechanism so vid_pll_div picks up the
1759                          * appropriate one.
1760                          */
1761                         .name = "hdmi_pll",
1762                         .index = -1,
1763                 },
1764                 .num_parents = 1,
1765                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1766         },
1767 };
1768
1769 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1770         { .hw = &gxbb_vid_pll_div.hw },
1771         /*
1772          * Note:
1773          * GXL and GXBB have different hdmi_plls (with
1774          * different struct clk_hw). We fallback to the global
1775          * naming string mechanism so vid_pll_div picks up the
1776          * appropriate one.
1777          */
1778         { .name = "hdmi_pll", .index = -1 },
1779 };
1780
1781 static struct clk_regmap gxbb_vid_pll_sel = {
1782         .data = &(struct clk_regmap_mux_data){
1783                 .offset = HHI_VID_PLL_CLK_DIV,
1784                 .mask = 0x1,
1785                 .shift = 18,
1786         },
1787         .hw.init = &(struct clk_init_data){
1788                 .name = "vid_pll_sel",
1789                 .ops = &clk_regmap_mux_ops,
1790                 /*
1791                  * bit 18 selects from 2 possible parents:
1792                  * vid_pll_div or hdmi_pll
1793                  */
1794                 .parent_data = gxbb_vid_pll_parent_data,
1795                 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1796                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1797         },
1798 };
1799
1800 static struct clk_regmap gxbb_vid_pll = {
1801         .data = &(struct clk_regmap_gate_data){
1802                 .offset = HHI_VID_PLL_CLK_DIV,
1803                 .bit_idx = 19,
1804         },
1805         .hw.init = &(struct clk_init_data) {
1806                 .name = "vid_pll",
1807                 .ops = &clk_regmap_gate_ops,
1808                 .parent_hws = (const struct clk_hw *[]) {
1809                         &gxbb_vid_pll_sel.hw
1810                 },
1811                 .num_parents = 1,
1812                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1813         },
1814 };
1815
1816 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1817         &gxbb_vid_pll.hw,
1818         &gxbb_fclk_div4.hw,
1819         &gxbb_fclk_div3.hw,
1820         &gxbb_fclk_div5.hw,
1821         &gxbb_vid_pll.hw,
1822         &gxbb_fclk_div7.hw,
1823         &gxbb_mpll1.hw,
1824 };
1825
1826 static struct clk_regmap gxbb_vclk_sel = {
1827         .data = &(struct clk_regmap_mux_data){
1828                 .offset = HHI_VID_CLK_CNTL,
1829                 .mask = 0x7,
1830                 .shift = 16,
1831         },
1832         .hw.init = &(struct clk_init_data){
1833                 .name = "vclk_sel",
1834                 .ops = &clk_regmap_mux_ops,
1835                 /*
1836                  * bits 16:18 selects from 8 possible parents:
1837                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1838                  * vid_pll, fclk_div7, mp1
1839                  */
1840                 .parent_hws = gxbb_vclk_parent_hws,
1841                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1842                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1843         },
1844 };
1845
1846 static struct clk_regmap gxbb_vclk2_sel = {
1847         .data = &(struct clk_regmap_mux_data){
1848                 .offset = HHI_VIID_CLK_CNTL,
1849                 .mask = 0x7,
1850                 .shift = 16,
1851         },
1852         .hw.init = &(struct clk_init_data){
1853                 .name = "vclk2_sel",
1854                 .ops = &clk_regmap_mux_ops,
1855                 /*
1856                  * bits 16:18 selects from 8 possible parents:
1857                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1858                  * vid_pll, fclk_div7, mp1
1859                  */
1860                 .parent_hws = gxbb_vclk_parent_hws,
1861                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1862                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1863         },
1864 };
1865
1866 static struct clk_regmap gxbb_vclk_input = {
1867         .data = &(struct clk_regmap_gate_data){
1868                 .offset = HHI_VID_CLK_DIV,
1869                 .bit_idx = 16,
1870         },
1871         .hw.init = &(struct clk_init_data) {
1872                 .name = "vclk_input",
1873                 .ops = &clk_regmap_gate_ops,
1874                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1875                 .num_parents = 1,
1876                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1877         },
1878 };
1879
1880 static struct clk_regmap gxbb_vclk2_input = {
1881         .data = &(struct clk_regmap_gate_data){
1882                 .offset = HHI_VIID_CLK_DIV,
1883                 .bit_idx = 16,
1884         },
1885         .hw.init = &(struct clk_init_data) {
1886                 .name = "vclk2_input",
1887                 .ops = &clk_regmap_gate_ops,
1888                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1889                 .num_parents = 1,
1890                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1891         },
1892 };
1893
1894 static struct clk_regmap gxbb_vclk_div = {
1895         .data = &(struct clk_regmap_div_data){
1896                 .offset = HHI_VID_CLK_DIV,
1897                 .shift = 0,
1898                 .width = 8,
1899         },
1900         .hw.init = &(struct clk_init_data){
1901                 .name = "vclk_div",
1902                 .ops = &clk_regmap_divider_ops,
1903                 .parent_hws = (const struct clk_hw *[]) {
1904                         &gxbb_vclk_input.hw
1905                 },
1906                 .num_parents = 1,
1907                 .flags = CLK_GET_RATE_NOCACHE,
1908         },
1909 };
1910
1911 static struct clk_regmap gxbb_vclk2_div = {
1912         .data = &(struct clk_regmap_div_data){
1913                 .offset = HHI_VIID_CLK_DIV,
1914                 .shift = 0,
1915                 .width = 8,
1916         },
1917         .hw.init = &(struct clk_init_data){
1918                 .name = "vclk2_div",
1919                 .ops = &clk_regmap_divider_ops,
1920                 .parent_hws = (const struct clk_hw *[]) {
1921                         &gxbb_vclk2_input.hw
1922                 },
1923                 .num_parents = 1,
1924                 .flags = CLK_GET_RATE_NOCACHE,
1925         },
1926 };
1927
1928 static struct clk_regmap gxbb_vclk = {
1929         .data = &(struct clk_regmap_gate_data){
1930                 .offset = HHI_VID_CLK_CNTL,
1931                 .bit_idx = 19,
1932         },
1933         .hw.init = &(struct clk_init_data) {
1934                 .name = "vclk",
1935                 .ops = &clk_regmap_gate_ops,
1936                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1937                 .num_parents = 1,
1938                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1939         },
1940 };
1941
1942 static struct clk_regmap gxbb_vclk2 = {
1943         .data = &(struct clk_regmap_gate_data){
1944                 .offset = HHI_VIID_CLK_CNTL,
1945                 .bit_idx = 19,
1946         },
1947         .hw.init = &(struct clk_init_data) {
1948                 .name = "vclk2",
1949                 .ops = &clk_regmap_gate_ops,
1950                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1951                 .num_parents = 1,
1952                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1953         },
1954 };
1955
1956 static struct clk_regmap gxbb_vclk_div1 = {
1957         .data = &(struct clk_regmap_gate_data){
1958                 .offset = HHI_VID_CLK_CNTL,
1959                 .bit_idx = 0,
1960         },
1961         .hw.init = &(struct clk_init_data) {
1962                 .name = "vclk_div1",
1963                 .ops = &clk_regmap_gate_ops,
1964                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1965                 .num_parents = 1,
1966                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1967         },
1968 };
1969
1970 static struct clk_regmap gxbb_vclk_div2_en = {
1971         .data = &(struct clk_regmap_gate_data){
1972                 .offset = HHI_VID_CLK_CNTL,
1973                 .bit_idx = 1,
1974         },
1975         .hw.init = &(struct clk_init_data) {
1976                 .name = "vclk_div2_en",
1977                 .ops = &clk_regmap_gate_ops,
1978                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1979                 .num_parents = 1,
1980                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1981         },
1982 };
1983
1984 static struct clk_regmap gxbb_vclk_div4_en = {
1985         .data = &(struct clk_regmap_gate_data){
1986                 .offset = HHI_VID_CLK_CNTL,
1987                 .bit_idx = 2,
1988         },
1989         .hw.init = &(struct clk_init_data) {
1990                 .name = "vclk_div4_en",
1991                 .ops = &clk_regmap_gate_ops,
1992                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1993                 .num_parents = 1,
1994                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1995         },
1996 };
1997
1998 static struct clk_regmap gxbb_vclk_div6_en = {
1999         .data = &(struct clk_regmap_gate_data){
2000                 .offset = HHI_VID_CLK_CNTL,
2001                 .bit_idx = 3,
2002         },
2003         .hw.init = &(struct clk_init_data) {
2004                 .name = "vclk_div6_en",
2005                 .ops = &clk_regmap_gate_ops,
2006                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2007                 .num_parents = 1,
2008                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2009         },
2010 };
2011
2012 static struct clk_regmap gxbb_vclk_div12_en = {
2013         .data = &(struct clk_regmap_gate_data){
2014                 .offset = HHI_VID_CLK_CNTL,
2015                 .bit_idx = 4,
2016         },
2017         .hw.init = &(struct clk_init_data) {
2018                 .name = "vclk_div12_en",
2019                 .ops = &clk_regmap_gate_ops,
2020                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2021                 .num_parents = 1,
2022                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2023         },
2024 };
2025
2026 static struct clk_regmap gxbb_vclk2_div1 = {
2027         .data = &(struct clk_regmap_gate_data){
2028                 .offset = HHI_VIID_CLK_CNTL,
2029                 .bit_idx = 0,
2030         },
2031         .hw.init = &(struct clk_init_data) {
2032                 .name = "vclk2_div1",
2033                 .ops = &clk_regmap_gate_ops,
2034                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2035                 .num_parents = 1,
2036                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2037         },
2038 };
2039
2040 static struct clk_regmap gxbb_vclk2_div2_en = {
2041         .data = &(struct clk_regmap_gate_data){
2042                 .offset = HHI_VIID_CLK_CNTL,
2043                 .bit_idx = 1,
2044         },
2045         .hw.init = &(struct clk_init_data) {
2046                 .name = "vclk2_div2_en",
2047                 .ops = &clk_regmap_gate_ops,
2048                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2049                 .num_parents = 1,
2050                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2051         },
2052 };
2053
2054 static struct clk_regmap gxbb_vclk2_div4_en = {
2055         .data = &(struct clk_regmap_gate_data){
2056                 .offset = HHI_VIID_CLK_CNTL,
2057                 .bit_idx = 2,
2058         },
2059         .hw.init = &(struct clk_init_data) {
2060                 .name = "vclk2_div4_en",
2061                 .ops = &clk_regmap_gate_ops,
2062                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2063                 .num_parents = 1,
2064                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2065         },
2066 };
2067
2068 static struct clk_regmap gxbb_vclk2_div6_en = {
2069         .data = &(struct clk_regmap_gate_data){
2070                 .offset = HHI_VIID_CLK_CNTL,
2071                 .bit_idx = 3,
2072         },
2073         .hw.init = &(struct clk_init_data) {
2074                 .name = "vclk2_div6_en",
2075                 .ops = &clk_regmap_gate_ops,
2076                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2077                 .num_parents = 1,
2078                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2079         },
2080 };
2081
2082 static struct clk_regmap gxbb_vclk2_div12_en = {
2083         .data = &(struct clk_regmap_gate_data){
2084                 .offset = HHI_VIID_CLK_CNTL,
2085                 .bit_idx = 4,
2086         },
2087         .hw.init = &(struct clk_init_data) {
2088                 .name = "vclk2_div12_en",
2089                 .ops = &clk_regmap_gate_ops,
2090                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2091                 .num_parents = 1,
2092                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2093         },
2094 };
2095
2096 static struct clk_fixed_factor gxbb_vclk_div2 = {
2097         .mult = 1,
2098         .div = 2,
2099         .hw.init = &(struct clk_init_data){
2100                 .name = "vclk_div2",
2101                 .ops = &clk_fixed_factor_ops,
2102                 .parent_hws = (const struct clk_hw *[]) {
2103                         &gxbb_vclk_div2_en.hw
2104                 },
2105                 .num_parents = 1,
2106         },
2107 };
2108
2109 static struct clk_fixed_factor gxbb_vclk_div4 = {
2110         .mult = 1,
2111         .div = 4,
2112         .hw.init = &(struct clk_init_data){
2113                 .name = "vclk_div4",
2114                 .ops = &clk_fixed_factor_ops,
2115                 .parent_hws = (const struct clk_hw *[]) {
2116                         &gxbb_vclk_div4_en.hw
2117                 },
2118                 .num_parents = 1,
2119         },
2120 };
2121
2122 static struct clk_fixed_factor gxbb_vclk_div6 = {
2123         .mult = 1,
2124         .div = 6,
2125         .hw.init = &(struct clk_init_data){
2126                 .name = "vclk_div6",
2127                 .ops = &clk_fixed_factor_ops,
2128                 .parent_hws = (const struct clk_hw *[]) {
2129                         &gxbb_vclk_div6_en.hw
2130                 },
2131                 .num_parents = 1,
2132         },
2133 };
2134
2135 static struct clk_fixed_factor gxbb_vclk_div12 = {
2136         .mult = 1,
2137         .div = 12,
2138         .hw.init = &(struct clk_init_data){
2139                 .name = "vclk_div12",
2140                 .ops = &clk_fixed_factor_ops,
2141                 .parent_hws = (const struct clk_hw *[]) {
2142                         &gxbb_vclk_div12_en.hw
2143                 },
2144                 .num_parents = 1,
2145         },
2146 };
2147
2148 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2149         .mult = 1,
2150         .div = 2,
2151         .hw.init = &(struct clk_init_data){
2152                 .name = "vclk2_div2",
2153                 .ops = &clk_fixed_factor_ops,
2154                 .parent_hws = (const struct clk_hw *[]) {
2155                         &gxbb_vclk2_div2_en.hw
2156                 },
2157                 .num_parents = 1,
2158         },
2159 };
2160
2161 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2162         .mult = 1,
2163         .div = 4,
2164         .hw.init = &(struct clk_init_data){
2165                 .name = "vclk2_div4",
2166                 .ops = &clk_fixed_factor_ops,
2167                 .parent_hws = (const struct clk_hw *[]) {
2168                         &gxbb_vclk2_div4_en.hw
2169                 },
2170                 .num_parents = 1,
2171         },
2172 };
2173
2174 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2175         .mult = 1,
2176         .div = 6,
2177         .hw.init = &(struct clk_init_data){
2178                 .name = "vclk2_div6",
2179                 .ops = &clk_fixed_factor_ops,
2180                 .parent_hws = (const struct clk_hw *[]) {
2181                         &gxbb_vclk2_div6_en.hw
2182                 },
2183                 .num_parents = 1,
2184         },
2185 };
2186
2187 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2188         .mult = 1,
2189         .div = 12,
2190         .hw.init = &(struct clk_init_data){
2191                 .name = "vclk2_div12",
2192                 .ops = &clk_fixed_factor_ops,
2193                 .parent_hws = (const struct clk_hw *[]) {
2194                         &gxbb_vclk2_div12_en.hw
2195                 },
2196                 .num_parents = 1,
2197         },
2198 };
2199
2200 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2201 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2202         &gxbb_vclk_div1.hw,
2203         &gxbb_vclk_div2.hw,
2204         &gxbb_vclk_div4.hw,
2205         &gxbb_vclk_div6.hw,
2206         &gxbb_vclk_div12.hw,
2207         &gxbb_vclk2_div1.hw,
2208         &gxbb_vclk2_div2.hw,
2209         &gxbb_vclk2_div4.hw,
2210         &gxbb_vclk2_div6.hw,
2211         &gxbb_vclk2_div12.hw,
2212 };
2213
2214 static struct clk_regmap gxbb_cts_enci_sel = {
2215         .data = &(struct clk_regmap_mux_data){
2216                 .offset = HHI_VID_CLK_DIV,
2217                 .mask = 0xf,
2218                 .shift = 28,
2219                 .table = mux_table_cts_sel,
2220         },
2221         .hw.init = &(struct clk_init_data){
2222                 .name = "cts_enci_sel",
2223                 .ops = &clk_regmap_mux_ops,
2224                 .parent_hws = gxbb_cts_parent_hws,
2225                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2226                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2227         },
2228 };
2229
2230 static struct clk_regmap gxbb_cts_encp_sel = {
2231         .data = &(struct clk_regmap_mux_data){
2232                 .offset = HHI_VID_CLK_DIV,
2233                 .mask = 0xf,
2234                 .shift = 20,
2235                 .table = mux_table_cts_sel,
2236         },
2237         .hw.init = &(struct clk_init_data){
2238                 .name = "cts_encp_sel",
2239                 .ops = &clk_regmap_mux_ops,
2240                 .parent_hws = gxbb_cts_parent_hws,
2241                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2242                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2243         },
2244 };
2245
2246 static struct clk_regmap gxbb_cts_vdac_sel = {
2247         .data = &(struct clk_regmap_mux_data){
2248                 .offset = HHI_VIID_CLK_DIV,
2249                 .mask = 0xf,
2250                 .shift = 28,
2251                 .table = mux_table_cts_sel,
2252         },
2253         .hw.init = &(struct clk_init_data){
2254                 .name = "cts_vdac_sel",
2255                 .ops = &clk_regmap_mux_ops,
2256                 .parent_hws = gxbb_cts_parent_hws,
2257                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2258                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2259         },
2260 };
2261
2262 /* TOFIX: add support for cts_tcon */
2263 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2264 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2265         &gxbb_vclk_div1.hw,
2266         &gxbb_vclk_div2.hw,
2267         &gxbb_vclk_div4.hw,
2268         &gxbb_vclk_div6.hw,
2269         &gxbb_vclk_div12.hw,
2270         &gxbb_vclk2_div1.hw,
2271         &gxbb_vclk2_div2.hw,
2272         &gxbb_vclk2_div4.hw,
2273         &gxbb_vclk2_div6.hw,
2274         &gxbb_vclk2_div12.hw,
2275 };
2276
2277 static struct clk_regmap gxbb_hdmi_tx_sel = {
2278         .data = &(struct clk_regmap_mux_data){
2279                 .offset = HHI_HDMI_CLK_CNTL,
2280                 .mask = 0xf,
2281                 .shift = 16,
2282                 .table = mux_table_hdmi_tx_sel,
2283         },
2284         .hw.init = &(struct clk_init_data){
2285                 .name = "hdmi_tx_sel",
2286                 .ops = &clk_regmap_mux_ops,
2287                 /*
2288                  * bits 31:28 selects from 12 possible parents:
2289                  * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2290                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2291                  * cts_tcon
2292                  */
2293                 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2294                 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2295                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2296         },
2297 };
2298
2299 static struct clk_regmap gxbb_cts_enci = {
2300         .data = &(struct clk_regmap_gate_data){
2301                 .offset = HHI_VID_CLK_CNTL2,
2302                 .bit_idx = 0,
2303         },
2304         .hw.init = &(struct clk_init_data) {
2305                 .name = "cts_enci",
2306                 .ops = &clk_regmap_gate_ops,
2307                 .parent_hws = (const struct clk_hw *[]) {
2308                         &gxbb_cts_enci_sel.hw
2309                 },
2310                 .num_parents = 1,
2311                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2312         },
2313 };
2314
2315 static struct clk_regmap gxbb_cts_encp = {
2316         .data = &(struct clk_regmap_gate_data){
2317                 .offset = HHI_VID_CLK_CNTL2,
2318                 .bit_idx = 2,
2319         },
2320         .hw.init = &(struct clk_init_data) {
2321                 .name = "cts_encp",
2322                 .ops = &clk_regmap_gate_ops,
2323                 .parent_hws = (const struct clk_hw *[]) {
2324                         &gxbb_cts_encp_sel.hw
2325                 },
2326                 .num_parents = 1,
2327                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2328         },
2329 };
2330
2331 static struct clk_regmap gxbb_cts_vdac = {
2332         .data = &(struct clk_regmap_gate_data){
2333                 .offset = HHI_VID_CLK_CNTL2,
2334                 .bit_idx = 4,
2335         },
2336         .hw.init = &(struct clk_init_data) {
2337                 .name = "cts_vdac",
2338                 .ops = &clk_regmap_gate_ops,
2339                 .parent_hws = (const struct clk_hw *[]) {
2340                         &gxbb_cts_vdac_sel.hw
2341                 },
2342                 .num_parents = 1,
2343                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2344         },
2345 };
2346
2347 static struct clk_regmap gxbb_hdmi_tx = {
2348         .data = &(struct clk_regmap_gate_data){
2349                 .offset = HHI_VID_CLK_CNTL2,
2350                 .bit_idx = 5,
2351         },
2352         .hw.init = &(struct clk_init_data) {
2353                 .name = "hdmi_tx",
2354                 .ops = &clk_regmap_gate_ops,
2355                 .parent_hws = (const struct clk_hw *[]) {
2356                         &gxbb_hdmi_tx_sel.hw
2357                 },
2358                 .num_parents = 1,
2359                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2360         },
2361 };
2362
2363 /* HDMI Clocks */
2364
2365 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2366         { .fw_name = "xtal", },
2367         { .hw = &gxbb_fclk_div4.hw },
2368         { .hw = &gxbb_fclk_div3.hw },
2369         { .hw = &gxbb_fclk_div5.hw },
2370 };
2371
2372 static struct clk_regmap gxbb_hdmi_sel = {
2373         .data = &(struct clk_regmap_mux_data){
2374                 .offset = HHI_HDMI_CLK_CNTL,
2375                 .mask = 0x3,
2376                 .shift = 9,
2377                 .flags = CLK_MUX_ROUND_CLOSEST,
2378         },
2379         .hw.init = &(struct clk_init_data){
2380                 .name = "hdmi_sel",
2381                 .ops = &clk_regmap_mux_ops,
2382                 .parent_data = gxbb_hdmi_parent_data,
2383                 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2384                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2385         },
2386 };
2387
2388 static struct clk_regmap gxbb_hdmi_div = {
2389         .data = &(struct clk_regmap_div_data){
2390                 .offset = HHI_HDMI_CLK_CNTL,
2391                 .shift = 0,
2392                 .width = 7,
2393         },
2394         .hw.init = &(struct clk_init_data){
2395                 .name = "hdmi_div",
2396                 .ops = &clk_regmap_divider_ops,
2397                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2398                 .num_parents = 1,
2399                 .flags = CLK_GET_RATE_NOCACHE,
2400         },
2401 };
2402
2403 static struct clk_regmap gxbb_hdmi = {
2404         .data = &(struct clk_regmap_gate_data){
2405                 .offset = HHI_HDMI_CLK_CNTL,
2406                 .bit_idx = 8,
2407         },
2408         .hw.init = &(struct clk_init_data) {
2409                 .name = "hdmi",
2410                 .ops = &clk_regmap_gate_ops,
2411                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2412                 .num_parents = 1,
2413                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2414         },
2415 };
2416
2417 /* VDEC clocks */
2418
2419 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2420         &gxbb_fclk_div4.hw,
2421         &gxbb_fclk_div3.hw,
2422         &gxbb_fclk_div5.hw,
2423         &gxbb_fclk_div7.hw,
2424 };
2425
2426 static struct clk_regmap gxbb_vdec_1_sel = {
2427         .data = &(struct clk_regmap_mux_data){
2428                 .offset = HHI_VDEC_CLK_CNTL,
2429                 .mask = 0x3,
2430                 .shift = 9,
2431                 .flags = CLK_MUX_ROUND_CLOSEST,
2432         },
2433         .hw.init = &(struct clk_init_data){
2434                 .name = "vdec_1_sel",
2435                 .ops = &clk_regmap_mux_ops,
2436                 .parent_hws = gxbb_vdec_parent_hws,
2437                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2438                 .flags = CLK_SET_RATE_PARENT,
2439         },
2440 };
2441
2442 static struct clk_regmap gxbb_vdec_1_div = {
2443         .data = &(struct clk_regmap_div_data){
2444                 .offset = HHI_VDEC_CLK_CNTL,
2445                 .shift = 0,
2446                 .width = 7,
2447                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2448         },
2449         .hw.init = &(struct clk_init_data){
2450                 .name = "vdec_1_div",
2451                 .ops = &clk_regmap_divider_ops,
2452                 .parent_hws = (const struct clk_hw *[]) {
2453                         &gxbb_vdec_1_sel.hw
2454                 },
2455                 .num_parents = 1,
2456                 .flags = CLK_SET_RATE_PARENT,
2457         },
2458 };
2459
2460 static struct clk_regmap gxbb_vdec_1 = {
2461         .data = &(struct clk_regmap_gate_data){
2462                 .offset = HHI_VDEC_CLK_CNTL,
2463                 .bit_idx = 8,
2464         },
2465         .hw.init = &(struct clk_init_data) {
2466                 .name = "vdec_1",
2467                 .ops = &clk_regmap_gate_ops,
2468                 .parent_hws = (const struct clk_hw *[]) {
2469                         &gxbb_vdec_1_div.hw
2470                 },
2471                 .num_parents = 1,
2472                 .flags = CLK_SET_RATE_PARENT,
2473         },
2474 };
2475
2476 static struct clk_regmap gxbb_vdec_hevc_sel = {
2477         .data = &(struct clk_regmap_mux_data){
2478                 .offset = HHI_VDEC2_CLK_CNTL,
2479                 .mask = 0x3,
2480                 .shift = 25,
2481                 .flags = CLK_MUX_ROUND_CLOSEST,
2482         },
2483         .hw.init = &(struct clk_init_data){
2484                 .name = "vdec_hevc_sel",
2485                 .ops = &clk_regmap_mux_ops,
2486                 .parent_hws = gxbb_vdec_parent_hws,
2487                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2488                 .flags = CLK_SET_RATE_PARENT,
2489         },
2490 };
2491
2492 static struct clk_regmap gxbb_vdec_hevc_div = {
2493         .data = &(struct clk_regmap_div_data){
2494                 .offset = HHI_VDEC2_CLK_CNTL,
2495                 .shift = 16,
2496                 .width = 7,
2497                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2498         },
2499         .hw.init = &(struct clk_init_data){
2500                 .name = "vdec_hevc_div",
2501                 .ops = &clk_regmap_divider_ops,
2502                 .parent_hws = (const struct clk_hw *[]) {
2503                         &gxbb_vdec_hevc_sel.hw
2504                 },
2505                 .num_parents = 1,
2506                 .flags = CLK_SET_RATE_PARENT,
2507         },
2508 };
2509
2510 static struct clk_regmap gxbb_vdec_hevc = {
2511         .data = &(struct clk_regmap_gate_data){
2512                 .offset = HHI_VDEC2_CLK_CNTL,
2513                 .bit_idx = 24,
2514         },
2515         .hw.init = &(struct clk_init_data) {
2516                 .name = "vdec_hevc",
2517                 .ops = &clk_regmap_gate_ops,
2518                 .parent_hws = (const struct clk_hw *[]) {
2519                         &gxbb_vdec_hevc_div.hw
2520                 },
2521                 .num_parents = 1,
2522                 .flags = CLK_SET_RATE_PARENT,
2523         },
2524 };
2525
2526 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
2527                                     9, 10, 11, 13, 14, };
2528 static const struct clk_parent_data gen_clk_parent_data[] = {
2529         { .fw_name = "xtal", },
2530         { .hw = &gxbb_vdec_1.hw },
2531         { .hw = &gxbb_vdec_hevc.hw },
2532         { .hw = &gxbb_mpll0.hw },
2533         { .hw = &gxbb_mpll1.hw },
2534         { .hw = &gxbb_mpll2.hw },
2535         { .hw = &gxbb_fclk_div4.hw },
2536         { .hw = &gxbb_fclk_div3.hw },
2537         { .hw = &gxbb_fclk_div5.hw },
2538         { .hw = &gxbb_fclk_div7.hw },
2539         { .hw = &gxbb_gp0_pll.hw },
2540 };
2541
2542 static struct clk_regmap gxbb_gen_clk_sel = {
2543         .data = &(struct clk_regmap_mux_data){
2544                 .offset = HHI_GEN_CLK_CNTL,
2545                 .mask = 0xf,
2546                 .shift = 12,
2547                 .table = mux_table_gen_clk,
2548         },
2549         .hw.init = &(struct clk_init_data){
2550                 .name = "gen_clk_sel",
2551                 .ops = &clk_regmap_mux_ops,
2552                 /*
2553                  * bits 15:12 selects from 14 possible parents:
2554                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2555                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2556                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2557                  */
2558                 .parent_data = gen_clk_parent_data,
2559                 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2560         },
2561 };
2562
2563 static struct clk_regmap gxbb_gen_clk_div = {
2564         .data = &(struct clk_regmap_div_data){
2565                 .offset = HHI_GEN_CLK_CNTL,
2566                 .shift = 0,
2567                 .width = 11,
2568         },
2569         .hw.init = &(struct clk_init_data){
2570                 .name = "gen_clk_div",
2571                 .ops = &clk_regmap_divider_ops,
2572                 .parent_hws = (const struct clk_hw *[]) {
2573                         &gxbb_gen_clk_sel.hw
2574                 },
2575                 .num_parents = 1,
2576                 .flags = CLK_SET_RATE_PARENT,
2577         },
2578 };
2579
2580 static struct clk_regmap gxbb_gen_clk = {
2581         .data = &(struct clk_regmap_gate_data){
2582                 .offset = HHI_GEN_CLK_CNTL,
2583                 .bit_idx = 7,
2584         },
2585         .hw.init = &(struct clk_init_data){
2586                 .name = "gen_clk",
2587                 .ops = &clk_regmap_gate_ops,
2588                 .parent_hws = (const struct clk_hw *[]) {
2589                         &gxbb_gen_clk_div.hw
2590                 },
2591                 .num_parents = 1,
2592                 .flags = CLK_SET_RATE_PARENT,
2593         },
2594 };
2595
2596 #define MESON_GATE(_name, _reg, _bit) \
2597         MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2598
2599 /* Everything Else (EE) domain gates */
2600 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2601 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2602 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2603 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2604 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2605 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2606 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2607 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2608 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2609 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2610 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2611 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2612 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2613 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2614 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2615 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2616 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2617 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2618 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2619 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2620 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2621 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2622 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2623
2624 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2625 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2626 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2627 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2628 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2629 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2630 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2631 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2632 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2633 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2634 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2635 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2636 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2637 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2638 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2639 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2640 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2641
2642 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2643 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2644 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2645 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2646 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2647 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2648 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2649 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2650 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2651 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2652 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2653 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2654 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2655
2656 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2657 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2658 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2659 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2660 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2661 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2662 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2663 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2664 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2665 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2666 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2667 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2668 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2669 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2670 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2671 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2672
2673 /* Always On (AO) domain gates */
2674
2675 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2676 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2677 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2678 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2679 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2680
2681 /* AIU gates */
2682 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2683 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2684 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2685 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2686 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2687 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2688 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2689 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2690
2691 /* Array of all clocks provided by this provider */
2692
2693 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2694         .hws = {
2695                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2696                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
2697                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2698                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2699                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2700                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2701                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2702                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2703                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2704                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2705                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2706                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2707                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2708                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2709                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2710                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2711                 [CLKID_DOS]                 = &gxbb_dos.hw,
2712                 [CLKID_ISA]                 = &gxbb_isa.hw,
2713                 [CLKID_PL301]               = &gxbb_pl301.hw,
2714                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2715                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2716                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2717                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2718                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2719                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2720                 [CLKID_UART0]               = &gxbb_uart0.hw,
2721                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2722                 [CLKID_STREAM]              = &gxbb_stream.hw,
2723                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2724                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2725                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2726                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2727                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2728                 [CLKID_SPI]                 = &gxbb_spi.hw,
2729                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2730                 [CLKID_ETH]                 = &gxbb_eth.hw,
2731                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2732                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2733                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2734                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2735                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2736                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2737                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2738                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2739                 [CLKID_ADC]                 = &gxbb_adc.hw,
2740                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2741                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2742                 [CLKID_UART1]               = &gxbb_uart1.hw,
2743                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2744                 [CLKID_USB0]                = &gxbb_usb0.hw,
2745                 [CLKID_USB1]                = &gxbb_usb1.hw,
2746                 [CLKID_RESET]               = &gxbb_reset.hw,
2747                 [CLKID_NAND]                = &gxbb_nand.hw,
2748                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2749                 [CLKID_USB]                 = &gxbb_usb.hw,
2750                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2751                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2752                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2753                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2754                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2755                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2756                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2757                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2758                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2759                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2760                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2761                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2762                 [CLKID_UART2]               = &gxbb_uart2.hw,
2763                 [CLKID_SANA]                = &gxbb_sana.hw,
2764                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2765                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2766                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2767                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2768                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2769                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2770                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2771                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2772                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2773                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2774                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2775                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2776                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2777                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2778                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2779                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2780                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2781                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2782                 [CLKID_EDP]                 = &gxbb_edp.hw,
2783                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2784                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2785                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2786                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2787                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2788                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2789                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2790                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2791                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2792                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2793                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2794                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2795                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2796                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2797                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2798                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2799                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2800                 [CLKID_MALI]                = &gxbb_mali.hw,
2801                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2802                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2803                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2804                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2805                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2806                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2807                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2808                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2809                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2810                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2811                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2812                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2813                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2814                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2815                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2816                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2817                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2818                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2819                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2820                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2821                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2822                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2823                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2824                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2825                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2826                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2827                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2828                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2829                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2830                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2831                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2832                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2833                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2834                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2835                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2836                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2837                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2838                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2839                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2840                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2841                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2842                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2843                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2844                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2845                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2846                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2847                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2848                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2849                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2850                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2851                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2852                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2853                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2854                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2855                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2856                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
2857                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
2858                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2859                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
2860                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
2861                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
2862                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
2863                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
2864                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
2865                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
2866                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
2867                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
2868                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
2869                 [CLKID_VCLK]                = &gxbb_vclk.hw,
2870                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
2871                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
2872                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
2873                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
2874                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
2875                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
2876                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
2877                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
2878                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
2879                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
2880                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
2881                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
2882                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
2883                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
2884                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
2885                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
2886                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
2887                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
2888                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
2889                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
2890                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
2891                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
2892                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
2893                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
2894                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
2895                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
2896                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
2897                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
2898                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
2899                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
2900                 [NR_CLKS]                   = NULL,
2901         },
2902         .num = NR_CLKS,
2903 };
2904
2905 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2906         .hws = {
2907                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2908                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
2909                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2910                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2911                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2912                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2913                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2914                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2915                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2916                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2917                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2918                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2919                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2920                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2921                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2922                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2923                 [CLKID_DOS]                 = &gxbb_dos.hw,
2924                 [CLKID_ISA]                 = &gxbb_isa.hw,
2925                 [CLKID_PL301]               = &gxbb_pl301.hw,
2926                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2927                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2928                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2929                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2930                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2931                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2932                 [CLKID_UART0]               = &gxbb_uart0.hw,
2933                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2934                 [CLKID_STREAM]              = &gxbb_stream.hw,
2935                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2936                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2937                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2938                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2939                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2940                 [CLKID_SPI]                 = &gxbb_spi.hw,
2941                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2942                 [CLKID_ETH]                 = &gxbb_eth.hw,
2943                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2944                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2945                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2946                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2947                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2948                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2949                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2950                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2951                 [CLKID_ADC]                 = &gxbb_adc.hw,
2952                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2953                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2954                 [CLKID_UART1]               = &gxbb_uart1.hw,
2955                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2956                 [CLKID_USB0]                = &gxbb_usb0.hw,
2957                 [CLKID_USB1]                = &gxbb_usb1.hw,
2958                 [CLKID_RESET]               = &gxbb_reset.hw,
2959                 [CLKID_NAND]                = &gxbb_nand.hw,
2960                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2961                 [CLKID_USB]                 = &gxbb_usb.hw,
2962                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2963                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2964                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2965                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2966                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2967                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2968                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2969                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2970                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2971                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2972                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2973                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2974                 [CLKID_UART2]               = &gxbb_uart2.hw,
2975                 [CLKID_SANA]                = &gxbb_sana.hw,
2976                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2977                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2978                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2979                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2980                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2981                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2982                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2983                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2984                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2985                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2986                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2987                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2988                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2989                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2990                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2991                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2992                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2993                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2994                 [CLKID_EDP]                 = &gxbb_edp.hw,
2995                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2996                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2997                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2998                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2999                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
3000                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
3001                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
3002                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
3003                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
3004                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
3005                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
3006                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
3007                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
3008                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
3009                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
3010                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
3011                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
3012                 [CLKID_MALI]                = &gxbb_mali.hw,
3013                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
3014                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
3015                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
3016                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
3017                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3018                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3019                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
3020                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
3021                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
3022                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
3023                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3024                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3025                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
3026                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3027                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3028                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
3029                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3030                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3031                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
3032                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
3033                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
3034                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
3035                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
3036                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
3037                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
3038                 [CLKID_VPU]                 = &gxbb_vpu.hw,
3039                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
3040                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
3041                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
3042                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
3043                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
3044                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
3045                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
3046                 [CLKID_VAPB]                = &gxbb_vapb.hw,
3047                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
3048                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
3049                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
3050                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
3051                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
3052                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
3053                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
3054                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
3055                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
3056                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
3057                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
3058                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
3059                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
3060                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
3061                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
3062                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
3063                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
3064                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
3065                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
3066                 [CLKID_HDMI_PLL_DCO]        = &gxl_hdmi_pll_dco.hw,
3067                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
3068                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
3069                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
3070                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
3071                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
3072                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
3073                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
3074                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
3075                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
3076                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
3077                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
3078                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
3079                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
3080                 [CLKID_VCLK]                = &gxbb_vclk.hw,
3081                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
3082                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
3083                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
3084                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
3085                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
3086                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
3087                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
3088                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
3089                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
3090                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
3091                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
3092                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
3093                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
3094                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
3095                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
3096                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
3097                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
3098                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
3099                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
3100                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
3101                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
3102                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
3103                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
3104                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
3105                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
3106                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
3107                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
3108                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
3109                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
3110                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
3111                 [CLKID_ACODEC]              = &gxl_acodec.hw,
3112                 [NR_CLKS]                   = NULL,
3113         },
3114         .num = NR_CLKS,
3115 };
3116
3117 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3118         &gxbb_clk81,
3119         &gxbb_ddr,
3120         &gxbb_dos,
3121         &gxbb_isa,
3122         &gxbb_pl301,
3123         &gxbb_periphs,
3124         &gxbb_spicc,
3125         &gxbb_i2c,
3126         &gxbb_sar_adc,
3127         &gxbb_smart_card,
3128         &gxbb_rng0,
3129         &gxbb_uart0,
3130         &gxbb_sdhc,
3131         &gxbb_stream,
3132         &gxbb_async_fifo,
3133         &gxbb_sdio,
3134         &gxbb_abuf,
3135         &gxbb_hiu_iface,
3136         &gxbb_assist_misc,
3137         &gxbb_spi,
3138         &gxbb_i2s_spdif,
3139         &gxbb_eth,
3140         &gxbb_demux,
3141         &gxbb_aiu_glue,
3142         &gxbb_iec958,
3143         &gxbb_i2s_out,
3144         &gxbb_amclk,
3145         &gxbb_aififo2,
3146         &gxbb_mixer,
3147         &gxbb_mixer_iface,
3148         &gxbb_adc,
3149         &gxbb_blkmv,
3150         &gxbb_aiu,
3151         &gxbb_uart1,
3152         &gxbb_g2d,
3153         &gxbb_usb0,
3154         &gxbb_usb1,
3155         &gxbb_reset,
3156         &gxbb_nand,
3157         &gxbb_dos_parser,
3158         &gxbb_usb,
3159         &gxbb_vdin1,
3160         &gxbb_ahb_arb0,
3161         &gxbb_efuse,
3162         &gxbb_boot_rom,
3163         &gxbb_ahb_data_bus,
3164         &gxbb_ahb_ctrl_bus,
3165         &gxbb_hdmi_intr_sync,
3166         &gxbb_hdmi_pclk,
3167         &gxbb_usb1_ddr_bridge,
3168         &gxbb_usb0_ddr_bridge,
3169         &gxbb_mmc_pclk,
3170         &gxbb_dvin,
3171         &gxbb_uart2,
3172         &gxbb_sana,
3173         &gxbb_vpu_intr,
3174         &gxbb_sec_ahb_ahb3_bridge,
3175         &gxbb_clk81_a53,
3176         &gxbb_vclk2_venci0,
3177         &gxbb_vclk2_venci1,
3178         &gxbb_vclk2_vencp0,
3179         &gxbb_vclk2_vencp1,
3180         &gxbb_gclk_venci_int0,
3181         &gxbb_gclk_vencp_int,
3182         &gxbb_dac_clk,
3183         &gxbb_aoclk_gate,
3184         &gxbb_iec958_gate,
3185         &gxbb_enc480p,
3186         &gxbb_rng1,
3187         &gxbb_gclk_venci_int1,
3188         &gxbb_vclk2_venclmcc,
3189         &gxbb_vclk2_vencl,
3190         &gxbb_vclk_other,
3191         &gxbb_edp,
3192         &gxbb_ao_media_cpu,
3193         &gxbb_ao_ahb_sram,
3194         &gxbb_ao_ahb_bus,
3195         &gxbb_ao_iface,
3196         &gxbb_ao_i2c,
3197         &gxbb_emmc_a,
3198         &gxbb_emmc_b,
3199         &gxbb_emmc_c,
3200         &gxbb_sar_adc_clk,
3201         &gxbb_mali_0,
3202         &gxbb_mali_1,
3203         &gxbb_cts_amclk,
3204         &gxbb_cts_mclk_i958,
3205         &gxbb_32k_clk,
3206         &gxbb_sd_emmc_a_clk0,
3207         &gxbb_sd_emmc_b_clk0,
3208         &gxbb_sd_emmc_c_clk0,
3209         &gxbb_vpu_0,
3210         &gxbb_vpu_1,
3211         &gxbb_vapb_0,
3212         &gxbb_vapb_1,
3213         &gxbb_vapb,
3214         &gxbb_mpeg_clk_div,
3215         &gxbb_sar_adc_clk_div,
3216         &gxbb_mali_0_div,
3217         &gxbb_mali_1_div,
3218         &gxbb_cts_mclk_i958_div,
3219         &gxbb_32k_clk_div,
3220         &gxbb_sd_emmc_a_clk0_div,
3221         &gxbb_sd_emmc_b_clk0_div,
3222         &gxbb_sd_emmc_c_clk0_div,
3223         &gxbb_vpu_0_div,
3224         &gxbb_vpu_1_div,
3225         &gxbb_vapb_0_div,
3226         &gxbb_vapb_1_div,
3227         &gxbb_mpeg_clk_sel,
3228         &gxbb_sar_adc_clk_sel,
3229         &gxbb_mali_0_sel,
3230         &gxbb_mali_1_sel,
3231         &gxbb_mali,
3232         &gxbb_cts_amclk_sel,
3233         &gxbb_cts_mclk_i958_sel,
3234         &gxbb_cts_i958,
3235         &gxbb_32k_clk_sel,
3236         &gxbb_sd_emmc_a_clk0_sel,
3237         &gxbb_sd_emmc_b_clk0_sel,
3238         &gxbb_sd_emmc_c_clk0_sel,
3239         &gxbb_vpu_0_sel,
3240         &gxbb_vpu_1_sel,
3241         &gxbb_vpu,
3242         &gxbb_vapb_0_sel,
3243         &gxbb_vapb_1_sel,
3244         &gxbb_vapb_sel,
3245         &gxbb_mpll0,
3246         &gxbb_mpll1,
3247         &gxbb_mpll2,
3248         &gxbb_mpll0_div,
3249         &gxbb_mpll1_div,
3250         &gxbb_mpll2_div,
3251         &gxbb_cts_amclk_div,
3252         &gxbb_fixed_pll,
3253         &gxbb_sys_pll,
3254         &gxbb_mpll_prediv,
3255         &gxbb_fclk_div2,
3256         &gxbb_fclk_div3,
3257         &gxbb_fclk_div4,
3258         &gxbb_fclk_div5,
3259         &gxbb_fclk_div7,
3260         &gxbb_vdec_1_sel,
3261         &gxbb_vdec_1_div,
3262         &gxbb_vdec_1,
3263         &gxbb_vdec_hevc_sel,
3264         &gxbb_vdec_hevc_div,
3265         &gxbb_vdec_hevc,
3266         &gxbb_gen_clk_sel,
3267         &gxbb_gen_clk_div,
3268         &gxbb_gen_clk,
3269         &gxbb_fixed_pll_dco,
3270         &gxbb_sys_pll_dco,
3271         &gxbb_gp0_pll,
3272         &gxbb_vid_pll,
3273         &gxbb_vid_pll_sel,
3274         &gxbb_vid_pll_div,
3275         &gxbb_vclk,
3276         &gxbb_vclk_sel,
3277         &gxbb_vclk_div,
3278         &gxbb_vclk_input,
3279         &gxbb_vclk_div1,
3280         &gxbb_vclk_div2_en,
3281         &gxbb_vclk_div4_en,
3282         &gxbb_vclk_div6_en,
3283         &gxbb_vclk_div12_en,
3284         &gxbb_vclk2,
3285         &gxbb_vclk2_sel,
3286         &gxbb_vclk2_div,
3287         &gxbb_vclk2_input,
3288         &gxbb_vclk2_div1,
3289         &gxbb_vclk2_div2_en,
3290         &gxbb_vclk2_div4_en,
3291         &gxbb_vclk2_div6_en,
3292         &gxbb_vclk2_div12_en,
3293         &gxbb_cts_enci,
3294         &gxbb_cts_enci_sel,
3295         &gxbb_cts_encp,
3296         &gxbb_cts_encp_sel,
3297         &gxbb_cts_vdac,
3298         &gxbb_cts_vdac_sel,
3299         &gxbb_hdmi_tx,
3300         &gxbb_hdmi_tx_sel,
3301         &gxbb_hdmi_sel,
3302         &gxbb_hdmi_div,
3303         &gxbb_hdmi,
3304         &gxbb_gp0_pll_dco,
3305         &gxbb_hdmi_pll,
3306         &gxbb_hdmi_pll_od,
3307         &gxbb_hdmi_pll_od2,
3308         &gxbb_hdmi_pll_dco,
3309 };
3310
3311 static struct clk_regmap *const gxl_clk_regmaps[] = {
3312         &gxbb_clk81,
3313         &gxbb_ddr,
3314         &gxbb_dos,
3315         &gxbb_isa,
3316         &gxbb_pl301,
3317         &gxbb_periphs,
3318         &gxbb_spicc,
3319         &gxbb_i2c,
3320         &gxbb_sar_adc,
3321         &gxbb_smart_card,
3322         &gxbb_rng0,
3323         &gxbb_uart0,
3324         &gxbb_sdhc,
3325         &gxbb_stream,
3326         &gxbb_async_fifo,
3327         &gxbb_sdio,
3328         &gxbb_abuf,
3329         &gxbb_hiu_iface,
3330         &gxbb_assist_misc,
3331         &gxbb_spi,
3332         &gxbb_i2s_spdif,
3333         &gxbb_eth,
3334         &gxbb_demux,
3335         &gxbb_aiu_glue,
3336         &gxbb_iec958,
3337         &gxbb_i2s_out,
3338         &gxbb_amclk,
3339         &gxbb_aififo2,
3340         &gxbb_mixer,
3341         &gxbb_mixer_iface,
3342         &gxbb_adc,
3343         &gxbb_blkmv,
3344         &gxbb_aiu,
3345         &gxbb_uart1,
3346         &gxbb_g2d,
3347         &gxbb_usb0,
3348         &gxbb_usb1,
3349         &gxbb_reset,
3350         &gxbb_nand,
3351         &gxbb_dos_parser,
3352         &gxbb_usb,
3353         &gxbb_vdin1,
3354         &gxbb_ahb_arb0,
3355         &gxbb_efuse,
3356         &gxbb_boot_rom,
3357         &gxbb_ahb_data_bus,
3358         &gxbb_ahb_ctrl_bus,
3359         &gxbb_hdmi_intr_sync,
3360         &gxbb_hdmi_pclk,
3361         &gxbb_usb1_ddr_bridge,
3362         &gxbb_usb0_ddr_bridge,
3363         &gxbb_mmc_pclk,
3364         &gxbb_dvin,
3365         &gxbb_uart2,
3366         &gxbb_sana,
3367         &gxbb_vpu_intr,
3368         &gxbb_sec_ahb_ahb3_bridge,
3369         &gxbb_clk81_a53,
3370         &gxbb_vclk2_venci0,
3371         &gxbb_vclk2_venci1,
3372         &gxbb_vclk2_vencp0,
3373         &gxbb_vclk2_vencp1,
3374         &gxbb_gclk_venci_int0,
3375         &gxbb_gclk_vencp_int,
3376         &gxbb_dac_clk,
3377         &gxbb_aoclk_gate,
3378         &gxbb_iec958_gate,
3379         &gxbb_enc480p,
3380         &gxbb_rng1,
3381         &gxbb_gclk_venci_int1,
3382         &gxbb_vclk2_venclmcc,
3383         &gxbb_vclk2_vencl,
3384         &gxbb_vclk_other,
3385         &gxbb_edp,
3386         &gxbb_ao_media_cpu,
3387         &gxbb_ao_ahb_sram,
3388         &gxbb_ao_ahb_bus,
3389         &gxbb_ao_iface,
3390         &gxbb_ao_i2c,
3391         &gxbb_emmc_a,
3392         &gxbb_emmc_b,
3393         &gxbb_emmc_c,
3394         &gxbb_sar_adc_clk,
3395         &gxbb_mali_0,
3396         &gxbb_mali_1,
3397         &gxbb_cts_amclk,
3398         &gxbb_cts_mclk_i958,
3399         &gxbb_32k_clk,
3400         &gxbb_sd_emmc_a_clk0,
3401         &gxbb_sd_emmc_b_clk0,
3402         &gxbb_sd_emmc_c_clk0,
3403         &gxbb_vpu_0,
3404         &gxbb_vpu_1,
3405         &gxbb_vapb_0,
3406         &gxbb_vapb_1,
3407         &gxbb_vapb,
3408         &gxbb_mpeg_clk_div,
3409         &gxbb_sar_adc_clk_div,
3410         &gxbb_mali_0_div,
3411         &gxbb_mali_1_div,
3412         &gxbb_cts_mclk_i958_div,
3413         &gxbb_32k_clk_div,
3414         &gxbb_sd_emmc_a_clk0_div,
3415         &gxbb_sd_emmc_b_clk0_div,
3416         &gxbb_sd_emmc_c_clk0_div,
3417         &gxbb_vpu_0_div,
3418         &gxbb_vpu_1_div,
3419         &gxbb_vapb_0_div,
3420         &gxbb_vapb_1_div,
3421         &gxbb_mpeg_clk_sel,
3422         &gxbb_sar_adc_clk_sel,
3423         &gxbb_mali_0_sel,
3424         &gxbb_mali_1_sel,
3425         &gxbb_mali,
3426         &gxbb_cts_amclk_sel,
3427         &gxbb_cts_mclk_i958_sel,
3428         &gxbb_cts_i958,
3429         &gxbb_32k_clk_sel,
3430         &gxbb_sd_emmc_a_clk0_sel,
3431         &gxbb_sd_emmc_b_clk0_sel,
3432         &gxbb_sd_emmc_c_clk0_sel,
3433         &gxbb_vpu_0_sel,
3434         &gxbb_vpu_1_sel,
3435         &gxbb_vpu,
3436         &gxbb_vapb_0_sel,
3437         &gxbb_vapb_1_sel,
3438         &gxbb_vapb_sel,
3439         &gxbb_mpll0,
3440         &gxbb_mpll1,
3441         &gxbb_mpll2,
3442         &gxbb_mpll0_div,
3443         &gxbb_mpll1_div,
3444         &gxbb_mpll2_div,
3445         &gxbb_cts_amclk_div,
3446         &gxbb_fixed_pll,
3447         &gxbb_sys_pll,
3448         &gxbb_mpll_prediv,
3449         &gxbb_fclk_div2,
3450         &gxbb_fclk_div3,
3451         &gxbb_fclk_div4,
3452         &gxbb_fclk_div5,
3453         &gxbb_fclk_div7,
3454         &gxbb_vdec_1_sel,
3455         &gxbb_vdec_1_div,
3456         &gxbb_vdec_1,
3457         &gxbb_vdec_hevc_sel,
3458         &gxbb_vdec_hevc_div,
3459         &gxbb_vdec_hevc,
3460         &gxbb_gen_clk_sel,
3461         &gxbb_gen_clk_div,
3462         &gxbb_gen_clk,
3463         &gxbb_fixed_pll_dco,
3464         &gxbb_sys_pll_dco,
3465         &gxbb_gp0_pll,
3466         &gxbb_vid_pll,
3467         &gxbb_vid_pll_sel,
3468         &gxbb_vid_pll_div,
3469         &gxbb_vclk,
3470         &gxbb_vclk_sel,
3471         &gxbb_vclk_div,
3472         &gxbb_vclk_input,
3473         &gxbb_vclk_div1,
3474         &gxbb_vclk_div2_en,
3475         &gxbb_vclk_div4_en,
3476         &gxbb_vclk_div6_en,
3477         &gxbb_vclk_div12_en,
3478         &gxbb_vclk2,
3479         &gxbb_vclk2_sel,
3480         &gxbb_vclk2_div,
3481         &gxbb_vclk2_input,
3482         &gxbb_vclk2_div1,
3483         &gxbb_vclk2_div2_en,
3484         &gxbb_vclk2_div4_en,
3485         &gxbb_vclk2_div6_en,
3486         &gxbb_vclk2_div12_en,
3487         &gxbb_cts_enci,
3488         &gxbb_cts_enci_sel,
3489         &gxbb_cts_encp,
3490         &gxbb_cts_encp_sel,
3491         &gxbb_cts_vdac,
3492         &gxbb_cts_vdac_sel,
3493         &gxbb_hdmi_tx,
3494         &gxbb_hdmi_tx_sel,
3495         &gxbb_hdmi_sel,
3496         &gxbb_hdmi_div,
3497         &gxbb_hdmi,
3498         &gxl_gp0_pll_dco,
3499         &gxl_hdmi_pll,
3500         &gxl_hdmi_pll_od,
3501         &gxl_hdmi_pll_od2,
3502         &gxl_hdmi_pll_dco,
3503         &gxl_acodec,
3504 };
3505
3506 static const struct meson_eeclkc_data gxbb_clkc_data = {
3507         .regmap_clks = gxbb_clk_regmaps,
3508         .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3509         .hw_onecell_data = &gxbb_hw_onecell_data,
3510 };
3511
3512 static const struct meson_eeclkc_data gxl_clkc_data = {
3513         .regmap_clks = gxl_clk_regmaps,
3514         .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3515         .hw_onecell_data = &gxl_hw_onecell_data,
3516 };
3517
3518 static const struct of_device_id clkc_match_table[] = {
3519         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3520         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3521         {},
3522 };
3523 MODULE_DEVICE_TABLE(of, clkc_match_table);
3524
3525 static struct platform_driver gxbb_driver = {
3526         .probe          = meson_eeclkc_probe,
3527         .driver         = {
3528                 .name   = "gxbb-clkc",
3529                 .of_match_table = clkc_match_table,
3530         },
3531 };
3532
3533 module_platform_driver(gxbb_driver);
3534 MODULE_LICENSE("GPL v2");