drivers/clk/meson/gxbb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2016 AmLogic, Inc.
   4  * Michael Turquette <mturquette@baylibre.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/init.h>
   9 #include <linux/of_device.h>
  10 #include <linux/platform_device.h>
  11
  12 #include "gxbb.h"
  13 #include "clk-regmap.h"
  14 #include "clk-pll.h"
  15 #include "clk-mpll.h"
  16 #include "meson-eeclk.h"
  17 #include "vid-pll-div.h"
  18
  19 static DEFINE_SPINLOCK(meson_clk_lock);
  20
  21 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
  22         PLL_PARAMS(32, 1),
  23         PLL_PARAMS(33, 1),
  24         PLL_PARAMS(34, 1),
  25         PLL_PARAMS(35, 1),
  26         PLL_PARAMS(36, 1),
  27         PLL_PARAMS(37, 1),
  28         PLL_PARAMS(38, 1),
  29         PLL_PARAMS(39, 1),
  30         PLL_PARAMS(40, 1),
  31         PLL_PARAMS(41, 1),
  32         PLL_PARAMS(42, 1),
  33         PLL_PARAMS(43, 1),
  34         PLL_PARAMS(44, 1),
  35         PLL_PARAMS(45, 1),
  36         PLL_PARAMS(46, 1),
  37         PLL_PARAMS(47, 1),
  38         PLL_PARAMS(48, 1),
  39         PLL_PARAMS(49, 1),
  40         PLL_PARAMS(50, 1),
  41         PLL_PARAMS(51, 1),
  42         PLL_PARAMS(52, 1),
  43         PLL_PARAMS(53, 1),
  44         PLL_PARAMS(54, 1),
  45         PLL_PARAMS(55, 1),
  46         PLL_PARAMS(56, 1),
  47         PLL_PARAMS(57, 1),
  48         PLL_PARAMS(58, 1),
  49         PLL_PARAMS(59, 1),
  50         PLL_PARAMS(60, 1),
  51         PLL_PARAMS(61, 1),
  52         PLL_PARAMS(62, 1),
  53         { /* sentinel */ },
  54 };
  55
  56 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
  57         PLL_PARAMS(42, 1),
  58         PLL_PARAMS(43, 1),
  59         PLL_PARAMS(44, 1),
  60         PLL_PARAMS(45, 1),
  61         PLL_PARAMS(46, 1),
  62         PLL_PARAMS(47, 1),
  63         PLL_PARAMS(48, 1),
  64         PLL_PARAMS(49, 1),
  65         PLL_PARAMS(50, 1),
  66         PLL_PARAMS(51, 1),
  67         PLL_PARAMS(52, 1),
  68         PLL_PARAMS(53, 1),
  69         PLL_PARAMS(54, 1),
  70         PLL_PARAMS(55, 1),
  71         PLL_PARAMS(56, 1),
  72         PLL_PARAMS(57, 1),
  73         PLL_PARAMS(58, 1),
  74         PLL_PARAMS(59, 1),
  75         PLL_PARAMS(60, 1),
  76         PLL_PARAMS(61, 1),
  77         PLL_PARAMS(62, 1),
  78         PLL_PARAMS(63, 1),
  79         PLL_PARAMS(64, 1),
  80         PLL_PARAMS(65, 1),
  81         PLL_PARAMS(66, 1),
  82         { /* sentinel */ },
  83 };
  84
  85 static struct clk_regmap gxbb_fixed_pll_dco = {
  86         .data = &(struct meson_clk_pll_data){
  87                 .en = {
  88                         .reg_off = HHI_MPLL_CNTL,
  89                         .shift   = 30,
  90                         .width   = 1,
  91                 },
  92                 .m = {
  93                         .reg_off = HHI_MPLL_CNTL,
  94                         .shift   = 0,
  95                         .width   = 9,
  96                 },
  97                 .n = {
  98                         .reg_off = HHI_MPLL_CNTL,
  99                         .shift   = 9,
 100                         .width   = 5,
 101                 },
 102                 .frac = {
 103                         .reg_off = HHI_MPLL_CNTL2,
 104                         .shift   = 0,
 105                         .width   = 12,
 106                 },
 107                 .l = {
 108                         .reg_off = HHI_MPLL_CNTL,
 109                         .shift   = 31,
 110                         .width   = 1,
 111                 },
 112                 .rst = {
 113                         .reg_off = HHI_MPLL_CNTL,
 114                         .shift   = 29,
 115                         .width   = 1,
 116                 },
 117         },
 118         .hw.init = &(struct clk_init_data){
 119                 .name = "fixed_pll_dco",
 120                 .ops = &meson_clk_pll_ro_ops,
 121                 .parent_data = &(const struct clk_parent_data) {
 122                         .fw_name = "xtal",
 123                 },
 124                 .num_parents = 1,
 125         },
 126 };
 127
 128 static struct clk_regmap gxbb_fixed_pll = {
 129         .data = &(struct clk_regmap_div_data){
 130                 .offset = HHI_MPLL_CNTL,
 131                 .shift = 16,
 132                 .width = 2,
 133                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 134         },
 135         .hw.init = &(struct clk_init_data){
 136                 .name = "fixed_pll",
 137                 .ops = &clk_regmap_divider_ro_ops,
 138                 .parent_hws = (const struct clk_hw *[]) {
 139                         &gxbb_fixed_pll_dco.hw
 140                 },
 141                 .num_parents = 1,
 142                 /*
 143                  * This clock won't ever change at runtime so
 144                  * CLK_SET_RATE_PARENT is not required
 145                  */
 146         },
 147 };
 148
 149 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
 150         .mult = 2,
 151         .div = 1,
 152         .hw.init = &(struct clk_init_data){
 153                 .name = "hdmi_pll_pre_mult",
 154                 .ops = &clk_fixed_factor_ops,
 155                 .parent_data = &(const struct clk_parent_data) {
 156                         .fw_name = "xtal",
 157                 },
 158                 .num_parents = 1,
 159         },
 160 };
 161
 162 static struct clk_regmap gxbb_hdmi_pll_dco = {
 163         .data = &(struct meson_clk_pll_data){
 164                 .en = {
 165                         .reg_off = HHI_HDMI_PLL_CNTL,
 166                         .shift   = 30,
 167                         .width   = 1,
 168                 },
 169                 .m = {
 170                         .reg_off = HHI_HDMI_PLL_CNTL,
 171                         .shift   = 0,
 172                         .width   = 9,
 173                 },
 174                 .n = {
 175                         .reg_off = HHI_HDMI_PLL_CNTL,
 176                         .shift   = 9,
 177                         .width   = 5,
 178                 },
 179                 .frac = {
 180                         .reg_off = HHI_HDMI_PLL_CNTL2,
 181                         .shift   = 0,
 182                         .width   = 12,
 183                 },
 184                 .l = {
 185                         .reg_off = HHI_HDMI_PLL_CNTL,
 186                         .shift   = 31,
 187                         .width   = 1,
 188                 },
 189                 .rst = {
 190                         .reg_off = HHI_HDMI_PLL_CNTL,
 191                         .shift   = 28,
 192                         .width   = 1,
 193                 },
 194         },
 195         .hw.init = &(struct clk_init_data){
 196                 .name = "hdmi_pll_dco",
 197                 .ops = &meson_clk_pll_ro_ops,
 198                 .parent_hws = (const struct clk_hw *[]) {
 199                         &gxbb_hdmi_pll_pre_mult.hw
 200                 },
 201                 .num_parents = 1,
 202                 /*
 203                  * Display directly handle hdmi pll registers ATM, we need
 204                  * NOCACHE to keep our view of the clock as accurate as possible
 205                  */
 206                 .flags = CLK_GET_RATE_NOCACHE,
 207         },
 208 };
 209
 210 static struct clk_regmap gxl_hdmi_pll_dco = {
 211         .data = &(struct meson_clk_pll_data){
 212                 .en = {
 213                         .reg_off = HHI_HDMI_PLL_CNTL,
 214                         .shift   = 30,
 215                         .width   = 1,
 216                 },
 217                 .m = {
 218                         .reg_off = HHI_HDMI_PLL_CNTL,
 219                         .shift   = 0,
 220                         .width   = 9,
 221                 },
 222                 .n = {
 223                         .reg_off = HHI_HDMI_PLL_CNTL,
 224                         .shift   = 9,
 225                         .width   = 5,
 226                 },
 227                 /*
 228                  * On gxl, there is a register shift due to
 229                  * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
 230                  * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
 231                  * instead which is defined at the same offset.
 232                  */
 233                 .frac = {
 234                         .reg_off = HHI_HDMI_PLL_CNTL2,
 235                         .shift   = 0,
 236                         .width   = 10,
 237                 },
 238                 .l = {
 239                         .reg_off = HHI_HDMI_PLL_CNTL,
 240                         .shift   = 31,
 241                         .width   = 1,
 242                 },
 243                 .rst = {
 244                         .reg_off = HHI_HDMI_PLL_CNTL,
 245                         .shift   = 28,
 246                         .width   = 1,
 247                 },
 248         },
 249         .hw.init = &(struct clk_init_data){
 250                 .name = "hdmi_pll_dco",
 251                 .ops = &meson_clk_pll_ro_ops,
 252                 .parent_data = &(const struct clk_parent_data) {
 253                         .fw_name = "xtal",
 254                 },
 255                 .num_parents = 1,
 256                 /*
 257                  * Display directly handle hdmi pll registers ATM, we need
 258                  * NOCACHE to keep our view of the clock as accurate as possible
 259                  */
 260                 .flags = CLK_GET_RATE_NOCACHE,
 261         },
 262 };
 263
 264 static struct clk_regmap gxbb_hdmi_pll_od = {
 265         .data = &(struct clk_regmap_div_data){
 266                 .offset = HHI_HDMI_PLL_CNTL2,
 267                 .shift = 16,
 268                 .width = 2,
 269                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 270         },
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "hdmi_pll_od",
 273                 .ops = &clk_regmap_divider_ro_ops,
 274                 .parent_hws = (const struct clk_hw *[]) {
 275                         &gxbb_hdmi_pll_dco.hw
 276                 },
 277                 .num_parents = 1,
 278                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 279         },
 280 };
 281
 282 static struct clk_regmap gxbb_hdmi_pll_od2 = {
 283         .data = &(struct clk_regmap_div_data){
 284                 .offset = HHI_HDMI_PLL_CNTL2,
 285                 .shift = 22,
 286                 .width = 2,
 287                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 288         },
 289         .hw.init = &(struct clk_init_data){
 290                 .name = "hdmi_pll_od2",
 291                 .ops = &clk_regmap_divider_ro_ops,
 292                 .parent_hws = (const struct clk_hw *[]) {
 293                         &gxbb_hdmi_pll_od.hw
 294                 },
 295                 .num_parents = 1,
 296                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 297         },
 298 };
 299
 300 static struct clk_regmap gxbb_hdmi_pll = {
 301         .data = &(struct clk_regmap_div_data){
 302                 .offset = HHI_HDMI_PLL_CNTL2,
 303                 .shift = 18,
 304                 .width = 2,
 305                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 306         },
 307         .hw.init = &(struct clk_init_data){
 308                 .name = "hdmi_pll",
 309                 .ops = &clk_regmap_divider_ro_ops,
 310                 .parent_hws = (const struct clk_hw *[]) {
 311                         &gxbb_hdmi_pll_od2.hw
 312                 },
 313                 .num_parents = 1,
 314                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 315         },
 316 };
 317
 318 static struct clk_regmap gxl_hdmi_pll_od = {
 319         .data = &(struct clk_regmap_div_data){
 320                 .offset = HHI_HDMI_PLL_CNTL + 8,
 321                 .shift = 21,
 322                 .width = 2,
 323                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 324         },
 325         .hw.init = &(struct clk_init_data){
 326                 .name = "hdmi_pll_od",
 327                 .ops = &clk_regmap_divider_ro_ops,
 328                 .parent_hws = (const struct clk_hw *[]) {
 329                         &gxl_hdmi_pll_dco.hw
 330                 },
 331                 .num_parents = 1,
 332                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 333         },
 334 };
 335
 336 static struct clk_regmap gxl_hdmi_pll_od2 = {
 337         .data = &(struct clk_regmap_div_data){
 338                 .offset = HHI_HDMI_PLL_CNTL + 8,
 339                 .shift = 23,
 340                 .width = 2,
 341                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 342         },
 343         .hw.init = &(struct clk_init_data){
 344                 .name = "hdmi_pll_od2",
 345                 .ops = &clk_regmap_divider_ro_ops,
 346                 .parent_hws = (const struct clk_hw *[]) {
 347                         &gxl_hdmi_pll_od.hw
 348                 },
 349                 .num_parents = 1,
 350                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 351         },
 352 };
 353
 354 static struct clk_regmap gxl_hdmi_pll = {
 355         .data = &(struct clk_regmap_div_data){
 356                 .offset = HHI_HDMI_PLL_CNTL + 8,
 357                 .shift = 19,
 358                 .width = 2,
 359                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 360         },
 361         .hw.init = &(struct clk_init_data){
 362                 .name = "hdmi_pll",
 363                 .ops = &clk_regmap_divider_ro_ops,
 364                 .parent_hws = (const struct clk_hw *[]) {
 365                         &gxl_hdmi_pll_od2.hw
 366                 },
 367                 .num_parents = 1,
 368                 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
 369         },
 370 };
 371
 372 static struct clk_regmap gxbb_sys_pll_dco = {
 373         .data = &(struct meson_clk_pll_data){
 374                 .en = {
 375                         .reg_off = HHI_SYS_PLL_CNTL,
 376                         .shift   = 30,
 377                         .width   = 1,
 378                 },
 379                 .m = {
 380                         .reg_off = HHI_SYS_PLL_CNTL,
 381                         .shift   = 0,
 382                         .width   = 9,
 383                 },
 384                 .n = {
 385                         .reg_off = HHI_SYS_PLL_CNTL,
 386                         .shift   = 9,
 387                         .width   = 5,
 388                 },
 389                 .l = {
 390                         .reg_off = HHI_SYS_PLL_CNTL,
 391                         .shift   = 31,
 392                         .width   = 1,
 393                 },
 394                 .rst = {
 395                         .reg_off = HHI_SYS_PLL_CNTL,
 396                         .shift   = 29,
 397                         .width   = 1,
 398                 },
 399         },
 400         .hw.init = &(struct clk_init_data){
 401                 .name = "sys_pll_dco",
 402                 .ops = &meson_clk_pll_ro_ops,
 403                 .parent_data = &(const struct clk_parent_data) {
 404                         .fw_name = "xtal",
 405                 },
 406                 .num_parents = 1,
 407         },
 408 };
 409
 410 static struct clk_regmap gxbb_sys_pll = {
 411         .data = &(struct clk_regmap_div_data){
 412                 .offset = HHI_SYS_PLL_CNTL,
 413                 .shift = 10,
 414                 .width = 2,
 415                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 416         },
 417         .hw.init = &(struct clk_init_data){
 418                 .name = "sys_pll",
 419                 .ops = &clk_regmap_divider_ro_ops,
 420                 .parent_hws = (const struct clk_hw *[]) {
 421                         &gxbb_sys_pll_dco.hw
 422                 },
 423                 .num_parents = 1,
 424                 .flags = CLK_SET_RATE_PARENT,
 425         },
 426 };
 427
 428 static const struct reg_sequence gxbb_gp0_init_regs[] = {
 429         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0x69c80000 },
 430         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a5590c4 },
 431         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0x0000500d },
 432 };
 433
 434 static struct clk_regmap gxbb_gp0_pll_dco = {
 435         .data = &(struct meson_clk_pll_data){
 436                 .en = {
 437                         .reg_off = HHI_GP0_PLL_CNTL,
 438                         .shift   = 30,
 439                         .width   = 1,
 440                 },
 441                 .m = {
 442                         .reg_off = HHI_GP0_PLL_CNTL,
 443                         .shift   = 0,
 444                         .width   = 9,
 445                 },
 446                 .n = {
 447                         .reg_off = HHI_GP0_PLL_CNTL,
 448                         .shift   = 9,
 449                         .width   = 5,
 450                 },
 451                 .l = {
 452                         .reg_off = HHI_GP0_PLL_CNTL,
 453                         .shift   = 31,
 454                         .width   = 1,
 455                 },
 456                 .rst = {
 457                         .reg_off = HHI_GP0_PLL_CNTL,
 458                         .shift   = 29,
 459                         .width   = 1,
 460                 },
 461                 .table = gxbb_gp0_pll_params_table,
 462                 .init_regs = gxbb_gp0_init_regs,
 463                 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
 464         },
 465         .hw.init = &(struct clk_init_data){
 466                 .name = "gp0_pll_dco",
 467                 .ops = &meson_clk_pll_ops,
 468                 .parent_data = &(const struct clk_parent_data) {
 469                         .fw_name = "xtal",
 470                 },
 471                 .num_parents = 1,
 472         },
 473 };
 474
 475 static const struct reg_sequence gxl_gp0_init_regs[] = {
 476         { .reg = HHI_GP0_PLL_CNTL1,     .def = 0xc084b000 },
 477         { .reg = HHI_GP0_PLL_CNTL2,     .def = 0xb75020be },
 478         { .reg = HHI_GP0_PLL_CNTL3,     .def = 0x0a59a288 },
 479         { .reg = HHI_GP0_PLL_CNTL4,     .def = 0xc000004d },
 480         { .reg = HHI_GP0_PLL_CNTL5,     .def = 0x00078000 },
 481 };
 482
 483 static struct clk_regmap gxl_gp0_pll_dco = {
 484         .data = &(struct meson_clk_pll_data){
 485                 .en = {
 486                         .reg_off = HHI_GP0_PLL_CNTL,
 487                         .shift   = 30,
 488                         .width   = 1,
 489                 },
 490                 .m = {
 491                         .reg_off = HHI_GP0_PLL_CNTL,
 492                         .shift   = 0,
 493                         .width   = 9,
 494                 },
 495                 .n = {
 496                         .reg_off = HHI_GP0_PLL_CNTL,
 497                         .shift   = 9,
 498                         .width   = 5,
 499                 },
 500                 .frac = {
 501                         .reg_off = HHI_GP0_PLL_CNTL1,
 502                         .shift   = 0,
 503                         .width   = 10,
 504                 },
 505                 .l = {
 506                         .reg_off = HHI_GP0_PLL_CNTL,
 507                         .shift   = 31,
 508                         .width   = 1,
 509                 },
 510                 .rst = {
 511                         .reg_off = HHI_GP0_PLL_CNTL,
 512                         .shift   = 29,
 513                         .width   = 1,
 514                 },
 515                 .table = gxl_gp0_pll_params_table,
 516                 .init_regs = gxl_gp0_init_regs,
 517                 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
 518         },
 519         .hw.init = &(struct clk_init_data){
 520                 .name = "gp0_pll_dco",
 521                 .ops = &meson_clk_pll_ops,
 522                 .parent_data = &(const struct clk_parent_data) {
 523                         .fw_name = "xtal",
 524                 },
 525                 .num_parents = 1,
 526         },
 527 };
 528
 529 static struct clk_regmap gxbb_gp0_pll = {
 530         .data = &(struct clk_regmap_div_data){
 531                 .offset = HHI_GP0_PLL_CNTL,
 532                 .shift = 16,
 533                 .width = 2,
 534                 .flags = CLK_DIVIDER_POWER_OF_TWO,
 535         },
 536         .hw.init = &(struct clk_init_data){
 537                 .name = "gp0_pll",
 538                 .ops = &clk_regmap_divider_ops,
 539                 .parent_data = &(const struct clk_parent_data) {
 540                         /*
 541                          * Note:
 542                          * GXL and GXBB have different gp0_pll_dco (with
 543                          * different struct clk_hw). We fallback to the global
 544                          * naming string mechanism so gp0_pll picks up the
 545                          * appropriate one.
 546                          */
 547                         .name = "gp0_pll_dco",
 548                         .index = -1,
 549                 },
 550                 .num_parents = 1,
 551                 .flags = CLK_SET_RATE_PARENT,
 552         },
 553 };
 554
 555 static struct clk_fixed_factor gxbb_fclk_div2_div = {
 556         .mult = 1,
 557         .div = 2,
 558         .hw.init = &(struct clk_init_data){
 559                 .name = "fclk_div2_div",
 560                 .ops = &clk_fixed_factor_ops,
 561                 .parent_hws = (const struct clk_hw *[]) {
 562                         &gxbb_fixed_pll.hw
 563                 },
 564                 .num_parents = 1,
 565         },
 566 };
 567
 568 static struct clk_regmap gxbb_fclk_div2 = {
 569         .data = &(struct clk_regmap_gate_data){
 570                 .offset = HHI_MPLL_CNTL6,
 571                 .bit_idx = 27,
 572         },
 573         .hw.init = &(struct clk_init_data){
 574                 .name = "fclk_div2",
 575                 .ops = &clk_regmap_gate_ops,
 576                 .parent_hws = (const struct clk_hw *[]) {
 577                         &gxbb_fclk_div2_div.hw
 578                 },
 579                 .num_parents = 1,
 580                 .flags = CLK_IS_CRITICAL,
 581         },
 582 };
 583
 584 static struct clk_fixed_factor gxbb_fclk_div3_div = {
 585         .mult = 1,
 586         .div = 3,
 587         .hw.init = &(struct clk_init_data){
 588                 .name = "fclk_div3_div",
 589                 .ops = &clk_fixed_factor_ops,
 590                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 591                 .num_parents = 1,
 592         },
 593 };
 594
 595 static struct clk_regmap gxbb_fclk_div3 = {
 596         .data = &(struct clk_regmap_gate_data){
 597                 .offset = HHI_MPLL_CNTL6,
 598                 .bit_idx = 28,
 599         },
 600         .hw.init = &(struct clk_init_data){
 601                 .name = "fclk_div3",
 602                 .ops = &clk_regmap_gate_ops,
 603                 .parent_hws = (const struct clk_hw *[]) {
 604                         &gxbb_fclk_div3_div.hw
 605                 },
 606                 .num_parents = 1,
 607                 /*
 608                  * FIXME:
 609                  * This clock, as fdiv2, is used by the SCPI FW and is required
 610                  * by the platform to operate correctly.
 611                  * Until the following condition are met, we need this clock to
 612                  * be marked as critical:
 613                  * a) The SCPI generic driver claims and enable all the clocks
 614                  *    it needs
 615                  * b) CCF has a clock hand-off mechanism to make the sure the
 616                  *    clock stays on until the proper driver comes along
 617                  */
 618                 .flags = CLK_IS_CRITICAL,
 619         },
 620 };
 621
 622 static struct clk_fixed_factor gxbb_fclk_div4_div = {
 623         .mult = 1,
 624         .div = 4,
 625         .hw.init = &(struct clk_init_data){
 626                 .name = "fclk_div4_div",
 627                 .ops = &clk_fixed_factor_ops,
 628                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 629                 .num_parents = 1,
 630         },
 631 };
 632
 633 static struct clk_regmap gxbb_fclk_div4 = {
 634         .data = &(struct clk_regmap_gate_data){
 635                 .offset = HHI_MPLL_CNTL6,
 636                 .bit_idx = 29,
 637         },
 638         .hw.init = &(struct clk_init_data){
 639                 .name = "fclk_div4",
 640                 .ops = &clk_regmap_gate_ops,
 641                 .parent_hws = (const struct clk_hw *[]) {
 642                         &gxbb_fclk_div4_div.hw
 643                 },
 644                 .num_parents = 1,
 645         },
 646 };
 647
 648 static struct clk_fixed_factor gxbb_fclk_div5_div = {
 649         .mult = 1,
 650         .div = 5,
 651         .hw.init = &(struct clk_init_data){
 652                 .name = "fclk_div5_div",
 653                 .ops = &clk_fixed_factor_ops,
 654                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 655                 .num_parents = 1,
 656         },
 657 };
 658
 659 static struct clk_regmap gxbb_fclk_div5 = {
 660         .data = &(struct clk_regmap_gate_data){
 661                 .offset = HHI_MPLL_CNTL6,
 662                 .bit_idx = 30,
 663         },
 664         .hw.init = &(struct clk_init_data){
 665                 .name = "fclk_div5",
 666                 .ops = &clk_regmap_gate_ops,
 667                 .parent_hws = (const struct clk_hw *[]) {
 668                         &gxbb_fclk_div5_div.hw
 669                 },
 670                 .num_parents = 1,
 671         },
 672 };
 673
 674 static struct clk_fixed_factor gxbb_fclk_div7_div = {
 675         .mult = 1,
 676         .div = 7,
 677         .hw.init = &(struct clk_init_data){
 678                 .name = "fclk_div7_div",
 679                 .ops = &clk_fixed_factor_ops,
 680                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 681                 .num_parents = 1,
 682         },
 683 };
 684
 685 static struct clk_regmap gxbb_fclk_div7 = {
 686         .data = &(struct clk_regmap_gate_data){
 687                 .offset = HHI_MPLL_CNTL6,
 688                 .bit_idx = 31,
 689         },
 690         .hw.init = &(struct clk_init_data){
 691                 .name = "fclk_div7",
 692                 .ops = &clk_regmap_gate_ops,
 693                 .parent_hws = (const struct clk_hw *[]) {
 694                         &gxbb_fclk_div7_div.hw
 695                 },
 696                 .num_parents = 1,
 697         },
 698 };
 699
 700 static struct clk_regmap gxbb_mpll_prediv = {
 701         .data = &(struct clk_regmap_div_data){
 702                 .offset = HHI_MPLL_CNTL5,
 703                 .shift = 12,
 704                 .width = 1,
 705         },
 706         .hw.init = &(struct clk_init_data){
 707                 .name = "mpll_prediv",
 708                 .ops = &clk_regmap_divider_ro_ops,
 709                 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
 710                 .num_parents = 1,
 711         },
 712 };
 713
 714 static struct clk_regmap gxbb_mpll0_div = {
 715         .data = &(struct meson_clk_mpll_data){
 716                 .sdm = {
 717                         .reg_off = HHI_MPLL_CNTL7,
 718                         .shift   = 0,
 719                         .width   = 14,
 720                 },
 721                 .sdm_en = {
 722                         .reg_off = HHI_MPLL_CNTL7,
 723                         .shift   = 15,
 724                         .width   = 1,
 725                 },
 726                 .n2 = {
 727                         .reg_off = HHI_MPLL_CNTL7,
 728                         .shift   = 16,
 729                         .width   = 9,
 730                 },
 731                 .lock = &meson_clk_lock,
 732         },
 733         .hw.init = &(struct clk_init_data){
 734                 .name = "mpll0_div",
 735                 .ops = &meson_clk_mpll_ops,
 736                 .parent_hws = (const struct clk_hw *[]) {
 737                         &gxbb_mpll_prediv.hw
 738                 },
 739                 .num_parents = 1,
 740         },
 741 };
 742
 743 static struct clk_regmap gxbb_mpll0 = {
 744         .data = &(struct clk_regmap_gate_data){
 745                 .offset = HHI_MPLL_CNTL7,
 746                 .bit_idx = 14,
 747         },
 748         .hw.init = &(struct clk_init_data){
 749                 .name = "mpll0",
 750                 .ops = &clk_regmap_gate_ops,
 751                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll0_div.hw },
 752                 .num_parents = 1,
 753                 .flags = CLK_SET_RATE_PARENT,
 754         },
 755 };
 756
 757 static struct clk_regmap gxbb_mpll1_div = {
 758         .data = &(struct meson_clk_mpll_data){
 759                 .sdm = {
 760                         .reg_off = HHI_MPLL_CNTL8,
 761                         .shift   = 0,
 762                         .width   = 14,
 763                 },
 764                 .sdm_en = {
 765                         .reg_off = HHI_MPLL_CNTL8,
 766                         .shift   = 15,
 767                         .width   = 1,
 768                 },
 769                 .n2 = {
 770                         .reg_off = HHI_MPLL_CNTL8,
 771                         .shift   = 16,
 772                         .width   = 9,
 773                 },
 774                 .lock = &meson_clk_lock,
 775         },
 776         .hw.init = &(struct clk_init_data){
 777                 .name = "mpll1_div",
 778                 .ops = &meson_clk_mpll_ops,
 779                 .parent_hws = (const struct clk_hw *[]) {
 780                         &gxbb_mpll_prediv.hw
 781                 },
 782                 .num_parents = 1,
 783         },
 784 };
 785
 786 static struct clk_regmap gxbb_mpll1 = {
 787         .data = &(struct clk_regmap_gate_data){
 788                 .offset = HHI_MPLL_CNTL8,
 789                 .bit_idx = 14,
 790         },
 791         .hw.init = &(struct clk_init_data){
 792                 .name = "mpll1",
 793                 .ops = &clk_regmap_gate_ops,
 794                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
 795                 .num_parents = 1,
 796                 .flags = CLK_SET_RATE_PARENT,
 797         },
 798 };
 799
 800 static struct clk_regmap gxbb_mpll2_div = {
 801         .data = &(struct meson_clk_mpll_data){
 802                 .sdm = {
 803                         .reg_off = HHI_MPLL_CNTL9,
 804                         .shift   = 0,
 805                         .width   = 14,
 806                 },
 807                 .sdm_en = {
 808                         .reg_off = HHI_MPLL_CNTL9,
 809                         .shift   = 15,
 810                         .width   = 1,
 811                 },
 812                 .n2 = {
 813                         .reg_off = HHI_MPLL_CNTL9,
 814                         .shift   = 16,
 815                         .width   = 9,
 816                 },
 817                 .lock = &meson_clk_lock,
 818         },
 819         .hw.init = &(struct clk_init_data){
 820                 .name = "mpll2_div",
 821                 .ops = &meson_clk_mpll_ops,
 822                 .parent_hws = (const struct clk_hw *[]) {
 823                         &gxbb_mpll_prediv.hw
 824                 },
 825                 .num_parents = 1,
 826         },
 827 };
 828
 829 static struct clk_regmap gxbb_mpll2 = {
 830         .data = &(struct clk_regmap_gate_data){
 831                 .offset = HHI_MPLL_CNTL9,
 832                 .bit_idx = 14,
 833         },
 834         .hw.init = &(struct clk_init_data){
 835                 .name = "mpll2",
 836                 .ops = &clk_regmap_gate_ops,
 837                 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
 838                 .num_parents = 1,
 839                 .flags = CLK_SET_RATE_PARENT,
 840         },
 841 };
 842
 843 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 844 static const struct clk_parent_data clk81_parent_data[] = {
 845         { .fw_name = "xtal", },
 846         { .hw = &gxbb_fclk_div7.hw },
 847         { .hw = &gxbb_mpll1.hw },
 848         { .hw = &gxbb_mpll2.hw },
 849         { .hw = &gxbb_fclk_div4.hw },
 850         { .hw = &gxbb_fclk_div3.hw },
 851         { .hw = &gxbb_fclk_div5.hw },
 852 };
 853
 854 static struct clk_regmap gxbb_mpeg_clk_sel = {
 855         .data = &(struct clk_regmap_mux_data){
 856                 .offset = HHI_MPEG_CLK_CNTL,
 857                 .mask = 0x7,
 858                 .shift = 12,
 859                 .table = mux_table_clk81,
 860         },
 861         .hw.init = &(struct clk_init_data){
 862                 .name = "mpeg_clk_sel",
 863                 .ops = &clk_regmap_mux_ro_ops,
 864                 /*
 865                  * bits 14:12 selects from 8 possible parents:
 866                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 867                  * fclk_div4, fclk_div3, fclk_div5
 868                  */
 869                 .parent_data = clk81_parent_data,
 870                 .num_parents = ARRAY_SIZE(clk81_parent_data),
 871         },
 872 };
 873
 874 static struct clk_regmap gxbb_mpeg_clk_div = {
 875         .data = &(struct clk_regmap_div_data){
 876                 .offset = HHI_MPEG_CLK_CNTL,
 877                 .shift = 0,
 878                 .width = 7,
 879         },
 880         .hw.init = &(struct clk_init_data){
 881                 .name = "mpeg_clk_div",
 882                 .ops = &clk_regmap_divider_ro_ops,
 883                 .parent_hws = (const struct clk_hw *[]) {
 884                         &gxbb_mpeg_clk_sel.hw
 885                 },
 886                 .num_parents = 1,
 887         },
 888 };
 889
 890 /* the mother of dragons gates */
 891 static struct clk_regmap gxbb_clk81 = {
 892         .data = &(struct clk_regmap_gate_data){
 893                 .offset = HHI_MPEG_CLK_CNTL,
 894                 .bit_idx = 7,
 895         },
 896         .hw.init = &(struct clk_init_data){
 897                 .name = "clk81",
 898                 .ops = &clk_regmap_gate_ops,
 899                 .parent_hws = (const struct clk_hw *[]) {
 900                         &gxbb_mpeg_clk_div.hw
 901                 },
 902                 .num_parents = 1,
 903                 .flags = CLK_IS_CRITICAL,
 904         },
 905 };
 906
 907 static struct clk_regmap gxbb_sar_adc_clk_sel = {
 908         .data = &(struct clk_regmap_mux_data){
 909                 .offset = HHI_SAR_CLK_CNTL,
 910                 .mask = 0x3,
 911                 .shift = 9,
 912         },
 913         .hw.init = &(struct clk_init_data){
 914                 .name = "sar_adc_clk_sel",
 915                 .ops = &clk_regmap_mux_ops,
 916                 /* NOTE: The datasheet doesn't list the parents for bit 10 */
 917                 .parent_data = (const struct clk_parent_data []) {
 918                         { .fw_name = "xtal", },
 919                         { .hw = &gxbb_clk81.hw },
 920                 },
 921                 .num_parents = 2,
 922         },
 923 };
 924
 925 static struct clk_regmap gxbb_sar_adc_clk_div = {
 926         .data = &(struct clk_regmap_div_data){
 927                 .offset = HHI_SAR_CLK_CNTL,
 928                 .shift = 0,
 929                 .width = 8,
 930         },
 931         .hw.init = &(struct clk_init_data){
 932                 .name = "sar_adc_clk_div",
 933                 .ops = &clk_regmap_divider_ops,
 934                 .parent_hws = (const struct clk_hw *[]) {
 935                         &gxbb_sar_adc_clk_sel.hw
 936                 },
 937                 .num_parents = 1,
 938                 .flags = CLK_SET_RATE_PARENT,
 939         },
 940 };
 941
 942 static struct clk_regmap gxbb_sar_adc_clk = {
 943         .data = &(struct clk_regmap_gate_data){
 944                 .offset = HHI_SAR_CLK_CNTL,
 945                 .bit_idx = 8,
 946         },
 947         .hw.init = &(struct clk_init_data){
 948                 .name = "sar_adc_clk",
 949                 .ops = &clk_regmap_gate_ops,
 950                 .parent_hws = (const struct clk_hw *[]) {
 951                         &gxbb_sar_adc_clk_div.hw
 952                 },
 953                 .num_parents = 1,
 954                 .flags = CLK_SET_RATE_PARENT,
 955         },
 956 };
 957
 958 /*
 959  * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
 960  * muxed by a glitch-free switch. The CCF can manage this glitch-free
 961  * mux because it does top-to-bottom updates the each clock tree and
 962  * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
 963  */
 964
 965 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
 966         { .fw_name = "xtal", },
 967         { .hw = &gxbb_gp0_pll.hw },
 968         { .hw = &gxbb_mpll2.hw },
 969         { .hw = &gxbb_mpll1.hw },
 970         { .hw = &gxbb_fclk_div7.hw },
 971         { .hw = &gxbb_fclk_div4.hw },
 972         { .hw = &gxbb_fclk_div3.hw },
 973         { .hw = &gxbb_fclk_div5.hw },
 974 };
 975
 976 static struct clk_regmap gxbb_mali_0_sel = {
 977         .data = &(struct clk_regmap_mux_data){
 978                 .offset = HHI_MALI_CLK_CNTL,
 979                 .mask = 0x7,
 980                 .shift = 9,
 981         },
 982         .hw.init = &(struct clk_init_data){
 983                 .name = "mali_0_sel",
 984                 .ops = &clk_regmap_mux_ops,
 985                 .parent_data = gxbb_mali_0_1_parent_data,
 986                 .num_parents = 8,
 987                 /*
 988                  * Don't request the parent to change the rate because
 989                  * all GPU frequencies can be derived from the fclk_*
 990                  * clocks and one special GP0_PLL setting. This is
 991                  * important because we need the MPLL clocks for audio.
 992                  */
 993                 .flags = 0,
 994         },
 995 };
 996
 997 static struct clk_regmap gxbb_mali_0_div = {
 998         .data = &(struct clk_regmap_div_data){
 999                 .offset = HHI_MALI_CLK_CNTL,
1000                 .shift = 0,
1001                 .width = 7,
1002         },
1003         .hw.init = &(struct clk_init_data){
1004                 .name = "mali_0_div",
1005                 .ops = &clk_regmap_divider_ops,
1006                 .parent_hws = (const struct clk_hw *[]) {
1007                         &gxbb_mali_0_sel.hw
1008                 },
1009                 .num_parents = 1,
1010                 .flags = CLK_SET_RATE_PARENT,
1011         },
1012 };
1013
1014 static struct clk_regmap gxbb_mali_0 = {
1015         .data = &(struct clk_regmap_gate_data){
1016                 .offset = HHI_MALI_CLK_CNTL,
1017                 .bit_idx = 8,
1018         },
1019         .hw.init = &(struct clk_init_data){
1020                 .name = "mali_0",
1021                 .ops = &clk_regmap_gate_ops,
1022                 .parent_hws = (const struct clk_hw *[]) {
1023                         &gxbb_mali_0_div.hw
1024                 },
1025                 .num_parents = 1,
1026                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1027         },
1028 };
1029
1030 static struct clk_regmap gxbb_mali_1_sel = {
1031         .data = &(struct clk_regmap_mux_data){
1032                 .offset = HHI_MALI_CLK_CNTL,
1033                 .mask = 0x7,
1034                 .shift = 25,
1035         },
1036         .hw.init = &(struct clk_init_data){
1037                 .name = "mali_1_sel",
1038                 .ops = &clk_regmap_mux_ops,
1039                 .parent_data = gxbb_mali_0_1_parent_data,
1040                 .num_parents = 8,
1041                 /*
1042                  * Don't request the parent to change the rate because
1043                  * all GPU frequencies can be derived from the fclk_*
1044                  * clocks and one special GP0_PLL setting. This is
1045                  * important because we need the MPLL clocks for audio.
1046                  */
1047                 .flags = 0,
1048         },
1049 };
1050
1051 static struct clk_regmap gxbb_mali_1_div = {
1052         .data = &(struct clk_regmap_div_data){
1053                 .offset = HHI_MALI_CLK_CNTL,
1054                 .shift = 16,
1055                 .width = 7,
1056         },
1057         .hw.init = &(struct clk_init_data){
1058                 .name = "mali_1_div",
1059                 .ops = &clk_regmap_divider_ops,
1060                 .parent_hws = (const struct clk_hw *[]) {
1061                         &gxbb_mali_1_sel.hw
1062                 },
1063                 .num_parents = 1,
1064                 .flags = CLK_SET_RATE_PARENT,
1065         },
1066 };
1067
1068 static struct clk_regmap gxbb_mali_1 = {
1069         .data = &(struct clk_regmap_gate_data){
1070                 .offset = HHI_MALI_CLK_CNTL,
1071                 .bit_idx = 24,
1072         },
1073         .hw.init = &(struct clk_init_data){
1074                 .name = "mali_1",
1075                 .ops = &clk_regmap_gate_ops,
1076                 .parent_hws = (const struct clk_hw *[]) {
1077                         &gxbb_mali_1_div.hw
1078                 },
1079                 .num_parents = 1,
1080                 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1081         },
1082 };
1083
1084 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1085         &gxbb_mali_0.hw,
1086         &gxbb_mali_1.hw,
1087 };
1088
1089 static struct clk_regmap gxbb_mali = {
1090         .data = &(struct clk_regmap_mux_data){
1091                 .offset = HHI_MALI_CLK_CNTL,
1092                 .mask = 1,
1093                 .shift = 31,
1094         },
1095         .hw.init = &(struct clk_init_data){
1096                 .name = "mali",
1097                 .ops = &clk_regmap_mux_ops,
1098                 .parent_hws = gxbb_mali_parent_hws,
1099                 .num_parents = 2,
1100                 .flags = CLK_SET_RATE_PARENT,
1101         },
1102 };
1103
1104 static struct clk_regmap gxbb_cts_amclk_sel = {
1105         .data = &(struct clk_regmap_mux_data){
1106                 .offset = HHI_AUD_CLK_CNTL,
1107                 .mask = 0x3,
1108                 .shift = 9,
1109                 .table = (u32[]){ 1, 2, 3 },
1110                 .flags = CLK_MUX_ROUND_CLOSEST,
1111         },
1112         .hw.init = &(struct clk_init_data){
1113                 .name = "cts_amclk_sel",
1114                 .ops = &clk_regmap_mux_ops,
1115                 .parent_hws = (const struct clk_hw *[]) {
1116                         &gxbb_mpll0.hw,
1117                         &gxbb_mpll1.hw,
1118                         &gxbb_mpll2.hw,
1119                 },
1120                 .num_parents = 3,
1121         },
1122 };
1123
1124 static struct clk_regmap gxbb_cts_amclk_div = {
1125         .data = &(struct clk_regmap_div_data) {
1126                 .offset = HHI_AUD_CLK_CNTL,
1127                 .shift = 0,
1128                 .width = 8,
1129                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1130         },
1131         .hw.init = &(struct clk_init_data){
1132                 .name = "cts_amclk_div",
1133                 .ops = &clk_regmap_divider_ops,
1134                 .parent_hws = (const struct clk_hw *[]) {
1135                         &gxbb_cts_amclk_sel.hw
1136                 },
1137                 .num_parents = 1,
1138                 .flags = CLK_SET_RATE_PARENT,
1139         },
1140 };
1141
1142 static struct clk_regmap gxbb_cts_amclk = {
1143         .data = &(struct clk_regmap_gate_data){
1144                 .offset = HHI_AUD_CLK_CNTL,
1145                 .bit_idx = 8,
1146         },
1147         .hw.init = &(struct clk_init_data){
1148                 .name = "cts_amclk",
1149                 .ops = &clk_regmap_gate_ops,
1150                 .parent_hws = (const struct clk_hw *[]) {
1151                         &gxbb_cts_amclk_div.hw
1152                 },
1153                 .num_parents = 1,
1154                 .flags = CLK_SET_RATE_PARENT,
1155         },
1156 };
1157
1158 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1159         .data = &(struct clk_regmap_mux_data){
1160                 .offset = HHI_AUD_CLK_CNTL2,
1161                 .mask = 0x3,
1162                 .shift = 25,
1163                 .table = (u32[]){ 1, 2, 3 },
1164                 .flags = CLK_MUX_ROUND_CLOSEST,
1165         },
1166         .hw.init = &(struct clk_init_data) {
1167                 .name = "cts_mclk_i958_sel",
1168                 .ops = &clk_regmap_mux_ops,
1169                 .parent_hws = (const struct clk_hw *[]) {
1170                         &gxbb_mpll0.hw,
1171                         &gxbb_mpll1.hw,
1172                         &gxbb_mpll2.hw,
1173                 },
1174                 .num_parents = 3,
1175         },
1176 };
1177
1178 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1179         .data = &(struct clk_regmap_div_data){
1180                 .offset = HHI_AUD_CLK_CNTL2,
1181                 .shift = 16,
1182                 .width = 8,
1183                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1184         },
1185         .hw.init = &(struct clk_init_data) {
1186                 .name = "cts_mclk_i958_div",
1187                 .ops = &clk_regmap_divider_ops,
1188                 .parent_hws = (const struct clk_hw *[]) {
1189                         &gxbb_cts_mclk_i958_sel.hw
1190                 },
1191                 .num_parents = 1,
1192                 .flags = CLK_SET_RATE_PARENT,
1193         },
1194 };
1195
1196 static struct clk_regmap gxbb_cts_mclk_i958 = {
1197         .data = &(struct clk_regmap_gate_data){
1198                 .offset = HHI_AUD_CLK_CNTL2,
1199                 .bit_idx = 24,
1200         },
1201         .hw.init = &(struct clk_init_data){
1202                 .name = "cts_mclk_i958",
1203                 .ops = &clk_regmap_gate_ops,
1204                 .parent_hws = (const struct clk_hw *[]) {
1205                         &gxbb_cts_mclk_i958_div.hw
1206                 },
1207                 .num_parents = 1,
1208                 .flags = CLK_SET_RATE_PARENT,
1209         },
1210 };
1211
1212 static struct clk_regmap gxbb_cts_i958 = {
1213         .data = &(struct clk_regmap_mux_data){
1214                 .offset = HHI_AUD_CLK_CNTL2,
1215                 .mask = 0x1,
1216                 .shift = 27,
1217                 },
1218         .hw.init = &(struct clk_init_data){
1219                 .name = "cts_i958",
1220                 .ops = &clk_regmap_mux_ops,
1221                 .parent_hws = (const struct clk_hw *[]) {
1222                         &gxbb_cts_amclk.hw,
1223                         &gxbb_cts_mclk_i958.hw
1224                 },
1225                 .num_parents = 2,
1226                 /*
1227                  *The parent is specific to origin of the audio data. Let the
1228                  * consumer choose the appropriate parent
1229                  */
1230                 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1231         },
1232 };
1233
1234 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1235         { .fw_name = "xtal", },
1236         /*
1237          * FIXME: This clock is provided by the ao clock controller but the
1238          * clock is not yet part of the binding of this controller, so string
1239          * name must be use to set this parent.
1240          */
1241         { .name = "cts_slow_oscin", .index = -1 },
1242         { .hw = &gxbb_fclk_div3.hw },
1243         { .hw = &gxbb_fclk_div5.hw },
1244 };
1245
1246 static struct clk_regmap gxbb_32k_clk_sel = {
1247         .data = &(struct clk_regmap_mux_data){
1248                 .offset = HHI_32K_CLK_CNTL,
1249                 .mask = 0x3,
1250                 .shift = 16,
1251                 },
1252         .hw.init = &(struct clk_init_data){
1253                 .name = "32k_clk_sel",
1254                 .ops = &clk_regmap_mux_ops,
1255                 .parent_data = gxbb_32k_clk_parent_data,
1256                 .num_parents = 4,
1257                 .flags = CLK_SET_RATE_PARENT,
1258         },
1259 };
1260
1261 static struct clk_regmap gxbb_32k_clk_div = {
1262         .data = &(struct clk_regmap_div_data){
1263                 .offset = HHI_32K_CLK_CNTL,
1264                 .shift = 0,
1265                 .width = 14,
1266         },
1267         .hw.init = &(struct clk_init_data){
1268                 .name = "32k_clk_div",
1269                 .ops = &clk_regmap_divider_ops,
1270                 .parent_hws = (const struct clk_hw *[]) {
1271                         &gxbb_32k_clk_sel.hw
1272                 },
1273                 .num_parents = 1,
1274                 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1275         },
1276 };
1277
1278 static struct clk_regmap gxbb_32k_clk = {
1279         .data = &(struct clk_regmap_gate_data){
1280                 .offset = HHI_32K_CLK_CNTL,
1281                 .bit_idx = 15,
1282         },
1283         .hw.init = &(struct clk_init_data){
1284                 .name = "32k_clk",
1285                 .ops = &clk_regmap_gate_ops,
1286                 .parent_hws = (const struct clk_hw *[]) {
1287                         &gxbb_32k_clk_div.hw
1288                 },
1289                 .num_parents = 1,
1290                 .flags = CLK_SET_RATE_PARENT,
1291         },
1292 };
1293
1294 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1295         { .fw_name = "xtal", },
1296         { .hw = &gxbb_fclk_div2.hw },
1297         { .hw = &gxbb_fclk_div3.hw },
1298         { .hw = &gxbb_fclk_div5.hw },
1299         { .hw = &gxbb_fclk_div7.hw },
1300         /*
1301          * Following these parent clocks, we should also have had mpll2, mpll3
1302          * and gp0_pll but these clocks are too precious to be used here. All
1303          * the necessary rates for MMC and NAND operation can be acheived using
1304          * xtal or fclk_div clocks
1305          */
1306 };
1307
1308 /* SDIO clock */
1309 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1310         .data = &(struct clk_regmap_mux_data){
1311                 .offset = HHI_SD_EMMC_CLK_CNTL,
1312                 .mask = 0x7,
1313                 .shift = 9,
1314         },
1315         .hw.init = &(struct clk_init_data) {
1316                 .name = "sd_emmc_a_clk0_sel",
1317                 .ops = &clk_regmap_mux_ops,
1318                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1319                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1320                 .flags = CLK_SET_RATE_PARENT,
1321         },
1322 };
1323
1324 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1325         .data = &(struct clk_regmap_div_data){
1326                 .offset = HHI_SD_EMMC_CLK_CNTL,
1327                 .shift = 0,
1328                 .width = 7,
1329                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1330         },
1331         .hw.init = &(struct clk_init_data) {
1332                 .name = "sd_emmc_a_clk0_div",
1333                 .ops = &clk_regmap_divider_ops,
1334                 .parent_hws = (const struct clk_hw *[]) {
1335                         &gxbb_sd_emmc_a_clk0_sel.hw
1336                 },
1337                 .num_parents = 1,
1338                 .flags = CLK_SET_RATE_PARENT,
1339         },
1340 };
1341
1342 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1343         .data = &(struct clk_regmap_gate_data){
1344                 .offset = HHI_SD_EMMC_CLK_CNTL,
1345                 .bit_idx = 7,
1346         },
1347         .hw.init = &(struct clk_init_data){
1348                 .name = "sd_emmc_a_clk0",
1349                 .ops = &clk_regmap_gate_ops,
1350                 .parent_hws = (const struct clk_hw *[]) {
1351                         &gxbb_sd_emmc_a_clk0_div.hw
1352                 },
1353                 .num_parents = 1,
1354                 .flags = CLK_SET_RATE_PARENT,
1355         },
1356 };
1357
1358 /* SDcard clock */
1359 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1360         .data = &(struct clk_regmap_mux_data){
1361                 .offset = HHI_SD_EMMC_CLK_CNTL,
1362                 .mask = 0x7,
1363                 .shift = 25,
1364         },
1365         .hw.init = &(struct clk_init_data) {
1366                 .name = "sd_emmc_b_clk0_sel",
1367                 .ops = &clk_regmap_mux_ops,
1368                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1369                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1370                 .flags = CLK_SET_RATE_PARENT,
1371         },
1372 };
1373
1374 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1375         .data = &(struct clk_regmap_div_data){
1376                 .offset = HHI_SD_EMMC_CLK_CNTL,
1377                 .shift = 16,
1378                 .width = 7,
1379                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1380         },
1381         .hw.init = &(struct clk_init_data) {
1382                 .name = "sd_emmc_b_clk0_div",
1383                 .ops = &clk_regmap_divider_ops,
1384                 .parent_hws = (const struct clk_hw *[]) {
1385                         &gxbb_sd_emmc_b_clk0_sel.hw
1386                 },
1387                 .num_parents = 1,
1388                 .flags = CLK_SET_RATE_PARENT,
1389         },
1390 };
1391
1392 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1393         .data = &(struct clk_regmap_gate_data){
1394                 .offset = HHI_SD_EMMC_CLK_CNTL,
1395                 .bit_idx = 23,
1396         },
1397         .hw.init = &(struct clk_init_data){
1398                 .name = "sd_emmc_b_clk0",
1399                 .ops = &clk_regmap_gate_ops,
1400                 .parent_hws = (const struct clk_hw *[]) {
1401                         &gxbb_sd_emmc_b_clk0_div.hw
1402                 },
1403                 .num_parents = 1,
1404                 .flags = CLK_SET_RATE_PARENT,
1405         },
1406 };
1407
1408 /* EMMC/NAND clock */
1409 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1410         .data = &(struct clk_regmap_mux_data){
1411                 .offset = HHI_NAND_CLK_CNTL,
1412                 .mask = 0x7,
1413                 .shift = 9,
1414         },
1415         .hw.init = &(struct clk_init_data) {
1416                 .name = "sd_emmc_c_clk0_sel",
1417                 .ops = &clk_regmap_mux_ops,
1418                 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1419                 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1420                 .flags = CLK_SET_RATE_PARENT,
1421         },
1422 };
1423
1424 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1425         .data = &(struct clk_regmap_div_data){
1426                 .offset = HHI_NAND_CLK_CNTL,
1427                 .shift = 0,
1428                 .width = 7,
1429                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1430         },
1431         .hw.init = &(struct clk_init_data) {
1432                 .name = "sd_emmc_c_clk0_div",
1433                 .ops = &clk_regmap_divider_ops,
1434                 .parent_hws = (const struct clk_hw *[]) {
1435                         &gxbb_sd_emmc_c_clk0_sel.hw
1436                 },
1437                 .num_parents = 1,
1438                 .flags = CLK_SET_RATE_PARENT,
1439         },
1440 };
1441
1442 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1443         .data = &(struct clk_regmap_gate_data){
1444                 .offset = HHI_NAND_CLK_CNTL,
1445                 .bit_idx = 7,
1446         },
1447         .hw.init = &(struct clk_init_data){
1448                 .name = "sd_emmc_c_clk0",
1449                 .ops = &clk_regmap_gate_ops,
1450                 .parent_hws = (const struct clk_hw *[]) {
1451                         &gxbb_sd_emmc_c_clk0_div.hw
1452                 },
1453                 .num_parents = 1,
1454                 .flags = CLK_SET_RATE_PARENT,
1455         },
1456 };
1457
1458 /* VPU Clock */
1459
1460 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1461         &gxbb_fclk_div4.hw,
1462         &gxbb_fclk_div3.hw,
1463         &gxbb_fclk_div5.hw,
1464         &gxbb_fclk_div7.hw,
1465 };
1466
1467 static struct clk_regmap gxbb_vpu_0_sel = {
1468         .data = &(struct clk_regmap_mux_data){
1469                 .offset = HHI_VPU_CLK_CNTL,
1470                 .mask = 0x3,
1471                 .shift = 9,
1472         },
1473         .hw.init = &(struct clk_init_data){
1474                 .name = "vpu_0_sel",
1475                 .ops = &clk_regmap_mux_ops,
1476                 /*
1477                  * bits 9:10 selects from 4 possible parents:
1478                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1479                  */
1480                 .parent_hws = gxbb_vpu_parent_hws,
1481                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1482                 .flags = CLK_SET_RATE_NO_REPARENT,
1483         },
1484 };
1485
1486 static struct clk_regmap gxbb_vpu_0_div = {
1487         .data = &(struct clk_regmap_div_data){
1488                 .offset = HHI_VPU_CLK_CNTL,
1489                 .shift = 0,
1490                 .width = 7,
1491         },
1492         .hw.init = &(struct clk_init_data){
1493                 .name = "vpu_0_div",
1494                 .ops = &clk_regmap_divider_ops,
1495                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1496                 .num_parents = 1,
1497                 .flags = CLK_SET_RATE_PARENT,
1498         },
1499 };
1500
1501 static struct clk_regmap gxbb_vpu_0 = {
1502         .data = &(struct clk_regmap_gate_data){
1503                 .offset = HHI_VPU_CLK_CNTL,
1504                 .bit_idx = 8,
1505         },
1506         .hw.init = &(struct clk_init_data) {
1507                 .name = "vpu_0",
1508                 .ops = &clk_regmap_gate_ops,
1509                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1510                 .num_parents = 1,
1511                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1512         },
1513 };
1514
1515 static struct clk_regmap gxbb_vpu_1_sel = {
1516         .data = &(struct clk_regmap_mux_data){
1517                 .offset = HHI_VPU_CLK_CNTL,
1518                 .mask = 0x3,
1519                 .shift = 25,
1520         },
1521         .hw.init = &(struct clk_init_data){
1522                 .name = "vpu_1_sel",
1523                 .ops = &clk_regmap_mux_ops,
1524                 /*
1525                  * bits 25:26 selects from 4 possible parents:
1526                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1527                  */
1528                 .parent_hws = gxbb_vpu_parent_hws,
1529                 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1530                 .flags = CLK_SET_RATE_NO_REPARENT,
1531         },
1532 };
1533
1534 static struct clk_regmap gxbb_vpu_1_div = {
1535         .data = &(struct clk_regmap_div_data){
1536                 .offset = HHI_VPU_CLK_CNTL,
1537                 .shift = 16,
1538                 .width = 7,
1539         },
1540         .hw.init = &(struct clk_init_data){
1541                 .name = "vpu_1_div",
1542                 .ops = &clk_regmap_divider_ops,
1543                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1544                 .num_parents = 1,
1545                 .flags = CLK_SET_RATE_PARENT,
1546         },
1547 };
1548
1549 static struct clk_regmap gxbb_vpu_1 = {
1550         .data = &(struct clk_regmap_gate_data){
1551                 .offset = HHI_VPU_CLK_CNTL,
1552                 .bit_idx = 24,
1553         },
1554         .hw.init = &(struct clk_init_data) {
1555                 .name = "vpu_1",
1556                 .ops = &clk_regmap_gate_ops,
1557                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1558                 .num_parents = 1,
1559                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1560         },
1561 };
1562
1563 static struct clk_regmap gxbb_vpu = {
1564         .data = &(struct clk_regmap_mux_data){
1565                 .offset = HHI_VPU_CLK_CNTL,
1566                 .mask = 1,
1567                 .shift = 31,
1568         },
1569         .hw.init = &(struct clk_init_data){
1570                 .name = "vpu",
1571                 .ops = &clk_regmap_mux_ops,
1572                 /*
1573                  * bit 31 selects from 2 possible parents:
1574                  * vpu_0 or vpu_1
1575                  */
1576                 .parent_hws = (const struct clk_hw *[]) {
1577                         &gxbb_vpu_0.hw,
1578                         &gxbb_vpu_1.hw
1579                 },
1580                 .num_parents = 2,
1581                 .flags = CLK_SET_RATE_NO_REPARENT,
1582         },
1583 };
1584
1585 /* VAPB Clock */
1586
1587 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1588         &gxbb_fclk_div4.hw,
1589         &gxbb_fclk_div3.hw,
1590         &gxbb_fclk_div5.hw,
1591         &gxbb_fclk_div7.hw,
1592 };
1593
1594 static struct clk_regmap gxbb_vapb_0_sel = {
1595         .data = &(struct clk_regmap_mux_data){
1596                 .offset = HHI_VAPBCLK_CNTL,
1597                 .mask = 0x3,
1598                 .shift = 9,
1599         },
1600         .hw.init = &(struct clk_init_data){
1601                 .name = "vapb_0_sel",
1602                 .ops = &clk_regmap_mux_ops,
1603                 /*
1604                  * bits 9:10 selects from 4 possible parents:
1605                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1606                  */
1607                 .parent_hws = gxbb_vapb_parent_hws,
1608                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1609                 .flags = CLK_SET_RATE_NO_REPARENT,
1610         },
1611 };
1612
1613 static struct clk_regmap gxbb_vapb_0_div = {
1614         .data = &(struct clk_regmap_div_data){
1615                 .offset = HHI_VAPBCLK_CNTL,
1616                 .shift = 0,
1617                 .width = 7,
1618         },
1619         .hw.init = &(struct clk_init_data){
1620                 .name = "vapb_0_div",
1621                 .ops = &clk_regmap_divider_ops,
1622                 .parent_hws = (const struct clk_hw *[]) {
1623                         &gxbb_vapb_0_sel.hw
1624                 },
1625                 .num_parents = 1,
1626                 .flags = CLK_SET_RATE_PARENT,
1627         },
1628 };
1629
1630 static struct clk_regmap gxbb_vapb_0 = {
1631         .data = &(struct clk_regmap_gate_data){
1632                 .offset = HHI_VAPBCLK_CNTL,
1633                 .bit_idx = 8,
1634         },
1635         .hw.init = &(struct clk_init_data) {
1636                 .name = "vapb_0",
1637                 .ops = &clk_regmap_gate_ops,
1638                 .parent_hws = (const struct clk_hw *[]) {
1639                         &gxbb_vapb_0_div.hw
1640                 },
1641                 .num_parents = 1,
1642                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1643         },
1644 };
1645
1646 static struct clk_regmap gxbb_vapb_1_sel = {
1647         .data = &(struct clk_regmap_mux_data){
1648                 .offset = HHI_VAPBCLK_CNTL,
1649                 .mask = 0x3,
1650                 .shift = 25,
1651         },
1652         .hw.init = &(struct clk_init_data){
1653                 .name = "vapb_1_sel",
1654                 .ops = &clk_regmap_mux_ops,
1655                 /*
1656                  * bits 25:26 selects from 4 possible parents:
1657                  * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1658                  */
1659                 .parent_hws = gxbb_vapb_parent_hws,
1660                 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1661                 .flags = CLK_SET_RATE_NO_REPARENT,
1662         },
1663 };
1664
1665 static struct clk_regmap gxbb_vapb_1_div = {
1666         .data = &(struct clk_regmap_div_data){
1667                 .offset = HHI_VAPBCLK_CNTL,
1668                 .shift = 16,
1669                 .width = 7,
1670         },
1671         .hw.init = &(struct clk_init_data){
1672                 .name = "vapb_1_div",
1673                 .ops = &clk_regmap_divider_ops,
1674                 .parent_hws = (const struct clk_hw *[]) {
1675                         &gxbb_vapb_1_sel.hw
1676                 },
1677                 .num_parents = 1,
1678                 .flags = CLK_SET_RATE_PARENT,
1679         },
1680 };
1681
1682 static struct clk_regmap gxbb_vapb_1 = {
1683         .data = &(struct clk_regmap_gate_data){
1684                 .offset = HHI_VAPBCLK_CNTL,
1685                 .bit_idx = 24,
1686         },
1687         .hw.init = &(struct clk_init_data) {
1688                 .name = "vapb_1",
1689                 .ops = &clk_regmap_gate_ops,
1690                 .parent_hws = (const struct clk_hw *[]) {
1691                         &gxbb_vapb_1_div.hw
1692                 },
1693                 .num_parents = 1,
1694                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1695         },
1696 };
1697
1698 static struct clk_regmap gxbb_vapb_sel = {
1699         .data = &(struct clk_regmap_mux_data){
1700                 .offset = HHI_VAPBCLK_CNTL,
1701                 .mask = 1,
1702                 .shift = 31,
1703         },
1704         .hw.init = &(struct clk_init_data){
1705                 .name = "vapb_sel",
1706                 .ops = &clk_regmap_mux_ops,
1707                 /*
1708                  * bit 31 selects from 2 possible parents:
1709                  * vapb_0 or vapb_1
1710                  */
1711                 .parent_hws = (const struct clk_hw *[]) {
1712                         &gxbb_vapb_0.hw,
1713                         &gxbb_vapb_1.hw
1714                 },
1715                 .num_parents = 2,
1716                 .flags = CLK_SET_RATE_NO_REPARENT,
1717         },
1718 };
1719
1720 static struct clk_regmap gxbb_vapb = {
1721         .data = &(struct clk_regmap_gate_data){
1722                 .offset = HHI_VAPBCLK_CNTL,
1723                 .bit_idx = 30,
1724         },
1725         .hw.init = &(struct clk_init_data) {
1726                 .name = "vapb",
1727                 .ops = &clk_regmap_gate_ops,
1728                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1729                 .num_parents = 1,
1730                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1731         },
1732 };
1733
1734 /* Video Clocks */
1735
1736 static struct clk_regmap gxbb_vid_pll_div = {
1737         .data = &(struct meson_vid_pll_div_data){
1738                 .val = {
1739                         .reg_off = HHI_VID_PLL_CLK_DIV,
1740                         .shift   = 0,
1741                         .width   = 15,
1742                 },
1743                 .sel = {
1744                         .reg_off = HHI_VID_PLL_CLK_DIV,
1745                         .shift   = 16,
1746                         .width   = 2,
1747                 },
1748         },
1749         .hw.init = &(struct clk_init_data) {
1750                 .name = "vid_pll_div",
1751                 .ops = &meson_vid_pll_div_ro_ops,
1752                 .parent_data = &(const struct clk_parent_data) {
1753                         /*
1754                          * Note:
1755                          * GXL and GXBB have different hdmi_plls (with
1756                          * different struct clk_hw). We fallback to the global
1757                          * naming string mechanism so vid_pll_div picks up the
1758                          * appropriate one.
1759                          */
1760                         .name = "hdmi_pll",
1761                         .index = -1,
1762                 },
1763                 .num_parents = 1,
1764                 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1765         },
1766 };
1767
1768 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1769         { .hw = &gxbb_vid_pll_div.hw },
1770         /*
1771          * Note:
1772          * GXL and GXBB have different hdmi_plls (with
1773          * different struct clk_hw). We fallback to the global
1774          * naming string mechanism so vid_pll_div picks up the
1775          * appropriate one.
1776          */
1777         { .name = "hdmi_pll", .index = -1 },
1778 };
1779
1780 static struct clk_regmap gxbb_vid_pll_sel = {
1781         .data = &(struct clk_regmap_mux_data){
1782                 .offset = HHI_VID_PLL_CLK_DIV,
1783                 .mask = 0x1,
1784                 .shift = 18,
1785         },
1786         .hw.init = &(struct clk_init_data){
1787                 .name = "vid_pll_sel",
1788                 .ops = &clk_regmap_mux_ops,
1789                 /*
1790                  * bit 18 selects from 2 possible parents:
1791                  * vid_pll_div or hdmi_pll
1792                  */
1793                 .parent_data = gxbb_vid_pll_parent_data,
1794                 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1795                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1796         },
1797 };
1798
1799 static struct clk_regmap gxbb_vid_pll = {
1800         .data = &(struct clk_regmap_gate_data){
1801                 .offset = HHI_VID_PLL_CLK_DIV,
1802                 .bit_idx = 19,
1803         },
1804         .hw.init = &(struct clk_init_data) {
1805                 .name = "vid_pll",
1806                 .ops = &clk_regmap_gate_ops,
1807                 .parent_hws = (const struct clk_hw *[]) {
1808                         &gxbb_vid_pll_sel.hw
1809                 },
1810                 .num_parents = 1,
1811                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1812         },
1813 };
1814
1815 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1816         &gxbb_vid_pll.hw,
1817         &gxbb_fclk_div4.hw,
1818         &gxbb_fclk_div3.hw,
1819         &gxbb_fclk_div5.hw,
1820         &gxbb_vid_pll.hw,
1821         &gxbb_fclk_div7.hw,
1822         &gxbb_mpll1.hw,
1823 };
1824
1825 static struct clk_regmap gxbb_vclk_sel = {
1826         .data = &(struct clk_regmap_mux_data){
1827                 .offset = HHI_VID_CLK_CNTL,
1828                 .mask = 0x7,
1829                 .shift = 16,
1830         },
1831         .hw.init = &(struct clk_init_data){
1832                 .name = "vclk_sel",
1833                 .ops = &clk_regmap_mux_ops,
1834                 /*
1835                  * bits 16:18 selects from 8 possible parents:
1836                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1837                  * vid_pll, fclk_div7, mp1
1838                  */
1839                 .parent_hws = gxbb_vclk_parent_hws,
1840                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1841                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1842         },
1843 };
1844
1845 static struct clk_regmap gxbb_vclk2_sel = {
1846         .data = &(struct clk_regmap_mux_data){
1847                 .offset = HHI_VIID_CLK_CNTL,
1848                 .mask = 0x7,
1849                 .shift = 16,
1850         },
1851         .hw.init = &(struct clk_init_data){
1852                 .name = "vclk2_sel",
1853                 .ops = &clk_regmap_mux_ops,
1854                 /*
1855                  * bits 16:18 selects from 8 possible parents:
1856                  * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1857                  * vid_pll, fclk_div7, mp1
1858                  */
1859                 .parent_hws = gxbb_vclk_parent_hws,
1860                 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1861                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1862         },
1863 };
1864
1865 static struct clk_regmap gxbb_vclk_input = {
1866         .data = &(struct clk_regmap_gate_data){
1867                 .offset = HHI_VID_CLK_DIV,
1868                 .bit_idx = 16,
1869         },
1870         .hw.init = &(struct clk_init_data) {
1871                 .name = "vclk_input",
1872                 .ops = &clk_regmap_gate_ops,
1873                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1874                 .num_parents = 1,
1875                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1876         },
1877 };
1878
1879 static struct clk_regmap gxbb_vclk2_input = {
1880         .data = &(struct clk_regmap_gate_data){
1881                 .offset = HHI_VIID_CLK_DIV,
1882                 .bit_idx = 16,
1883         },
1884         .hw.init = &(struct clk_init_data) {
1885                 .name = "vclk2_input",
1886                 .ops = &clk_regmap_gate_ops,
1887                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1888                 .num_parents = 1,
1889                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1890         },
1891 };
1892
1893 static struct clk_regmap gxbb_vclk_div = {
1894         .data = &(struct clk_regmap_div_data){
1895                 .offset = HHI_VID_CLK_DIV,
1896                 .shift = 0,
1897                 .width = 8,
1898         },
1899         .hw.init = &(struct clk_init_data){
1900                 .name = "vclk_div",
1901                 .ops = &clk_regmap_divider_ops,
1902                 .parent_hws = (const struct clk_hw *[]) {
1903                         &gxbb_vclk_input.hw
1904                 },
1905                 .num_parents = 1,
1906                 .flags = CLK_GET_RATE_NOCACHE,
1907         },
1908 };
1909
1910 static struct clk_regmap gxbb_vclk2_div = {
1911         .data = &(struct clk_regmap_div_data){
1912                 .offset = HHI_VIID_CLK_DIV,
1913                 .shift = 0,
1914                 .width = 8,
1915         },
1916         .hw.init = &(struct clk_init_data){
1917                 .name = "vclk2_div",
1918                 .ops = &clk_regmap_divider_ops,
1919                 .parent_hws = (const struct clk_hw *[]) {
1920                         &gxbb_vclk2_input.hw
1921                 },
1922                 .num_parents = 1,
1923                 .flags = CLK_GET_RATE_NOCACHE,
1924         },
1925 };
1926
1927 static struct clk_regmap gxbb_vclk = {
1928         .data = &(struct clk_regmap_gate_data){
1929                 .offset = HHI_VID_CLK_CNTL,
1930                 .bit_idx = 19,
1931         },
1932         .hw.init = &(struct clk_init_data) {
1933                 .name = "vclk",
1934                 .ops = &clk_regmap_gate_ops,
1935                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1936                 .num_parents = 1,
1937                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1938         },
1939 };
1940
1941 static struct clk_regmap gxbb_vclk2 = {
1942         .data = &(struct clk_regmap_gate_data){
1943                 .offset = HHI_VIID_CLK_CNTL,
1944                 .bit_idx = 19,
1945         },
1946         .hw.init = &(struct clk_init_data) {
1947                 .name = "vclk2",
1948                 .ops = &clk_regmap_gate_ops,
1949                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1950                 .num_parents = 1,
1951                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1952         },
1953 };
1954
1955 static struct clk_regmap gxbb_vclk_div1 = {
1956         .data = &(struct clk_regmap_gate_data){
1957                 .offset = HHI_VID_CLK_CNTL,
1958                 .bit_idx = 0,
1959         },
1960         .hw.init = &(struct clk_init_data) {
1961                 .name = "vclk_div1",
1962                 .ops = &clk_regmap_gate_ops,
1963                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1964                 .num_parents = 1,
1965                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1966         },
1967 };
1968
1969 static struct clk_regmap gxbb_vclk_div2_en = {
1970         .data = &(struct clk_regmap_gate_data){
1971                 .offset = HHI_VID_CLK_CNTL,
1972                 .bit_idx = 1,
1973         },
1974         .hw.init = &(struct clk_init_data) {
1975                 .name = "vclk_div2_en",
1976                 .ops = &clk_regmap_gate_ops,
1977                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1978                 .num_parents = 1,
1979                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1980         },
1981 };
1982
1983 static struct clk_regmap gxbb_vclk_div4_en = {
1984         .data = &(struct clk_regmap_gate_data){
1985                 .offset = HHI_VID_CLK_CNTL,
1986                 .bit_idx = 2,
1987         },
1988         .hw.init = &(struct clk_init_data) {
1989                 .name = "vclk_div4_en",
1990                 .ops = &clk_regmap_gate_ops,
1991                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1992                 .num_parents = 1,
1993                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1994         },
1995 };
1996
1997 static struct clk_regmap gxbb_vclk_div6_en = {
1998         .data = &(struct clk_regmap_gate_data){
1999                 .offset = HHI_VID_CLK_CNTL,
2000                 .bit_idx = 3,
2001         },
2002         .hw.init = &(struct clk_init_data) {
2003                 .name = "vclk_div6_en",
2004                 .ops = &clk_regmap_gate_ops,
2005                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2006                 .num_parents = 1,
2007                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2008         },
2009 };
2010
2011 static struct clk_regmap gxbb_vclk_div12_en = {
2012         .data = &(struct clk_regmap_gate_data){
2013                 .offset = HHI_VID_CLK_CNTL,
2014                 .bit_idx = 4,
2015         },
2016         .hw.init = &(struct clk_init_data) {
2017                 .name = "vclk_div12_en",
2018                 .ops = &clk_regmap_gate_ops,
2019                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2020                 .num_parents = 1,
2021                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2022         },
2023 };
2024
2025 static struct clk_regmap gxbb_vclk2_div1 = {
2026         .data = &(struct clk_regmap_gate_data){
2027                 .offset = HHI_VIID_CLK_CNTL,
2028                 .bit_idx = 0,
2029         },
2030         .hw.init = &(struct clk_init_data) {
2031                 .name = "vclk2_div1",
2032                 .ops = &clk_regmap_gate_ops,
2033                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2034                 .num_parents = 1,
2035                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2036         },
2037 };
2038
2039 static struct clk_regmap gxbb_vclk2_div2_en = {
2040         .data = &(struct clk_regmap_gate_data){
2041                 .offset = HHI_VIID_CLK_CNTL,
2042                 .bit_idx = 1,
2043         },
2044         .hw.init = &(struct clk_init_data) {
2045                 .name = "vclk2_div2_en",
2046                 .ops = &clk_regmap_gate_ops,
2047                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2048                 .num_parents = 1,
2049                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2050         },
2051 };
2052
2053 static struct clk_regmap gxbb_vclk2_div4_en = {
2054         .data = &(struct clk_regmap_gate_data){
2055                 .offset = HHI_VIID_CLK_CNTL,
2056                 .bit_idx = 2,
2057         },
2058         .hw.init = &(struct clk_init_data) {
2059                 .name = "vclk2_div4_en",
2060                 .ops = &clk_regmap_gate_ops,
2061                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2062                 .num_parents = 1,
2063                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2064         },
2065 };
2066
2067 static struct clk_regmap gxbb_vclk2_div6_en = {
2068         .data = &(struct clk_regmap_gate_data){
2069                 .offset = HHI_VIID_CLK_CNTL,
2070                 .bit_idx = 3,
2071         },
2072         .hw.init = &(struct clk_init_data) {
2073                 .name = "vclk2_div6_en",
2074                 .ops = &clk_regmap_gate_ops,
2075                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2076                 .num_parents = 1,
2077                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2078         },
2079 };
2080
2081 static struct clk_regmap gxbb_vclk2_div12_en = {
2082         .data = &(struct clk_regmap_gate_data){
2083                 .offset = HHI_VIID_CLK_CNTL,
2084                 .bit_idx = 4,
2085         },
2086         .hw.init = &(struct clk_init_data) {
2087                 .name = "vclk2_div12_en",
2088                 .ops = &clk_regmap_gate_ops,
2089                 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2090                 .num_parents = 1,
2091                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2092         },
2093 };
2094
2095 static struct clk_fixed_factor gxbb_vclk_div2 = {
2096         .mult = 1,
2097         .div = 2,
2098         .hw.init = &(struct clk_init_data){
2099                 .name = "vclk_div2",
2100                 .ops = &clk_fixed_factor_ops,
2101                 .parent_hws = (const struct clk_hw *[]) {
2102                         &gxbb_vclk_div2_en.hw
2103                 },
2104                 .num_parents = 1,
2105         },
2106 };
2107
2108 static struct clk_fixed_factor gxbb_vclk_div4 = {
2109         .mult = 1,
2110         .div = 4,
2111         .hw.init = &(struct clk_init_data){
2112                 .name = "vclk_div4",
2113                 .ops = &clk_fixed_factor_ops,
2114                 .parent_hws = (const struct clk_hw *[]) {
2115                         &gxbb_vclk_div4_en.hw
2116                 },
2117                 .num_parents = 1,
2118         },
2119 };
2120
2121 static struct clk_fixed_factor gxbb_vclk_div6 = {
2122         .mult = 1,
2123         .div = 6,
2124         .hw.init = &(struct clk_init_data){
2125                 .name = "vclk_div6",
2126                 .ops = &clk_fixed_factor_ops,
2127                 .parent_hws = (const struct clk_hw *[]) {
2128                         &gxbb_vclk_div6_en.hw
2129                 },
2130                 .num_parents = 1,
2131         },
2132 };
2133
2134 static struct clk_fixed_factor gxbb_vclk_div12 = {
2135         .mult = 1,
2136         .div = 12,
2137         .hw.init = &(struct clk_init_data){
2138                 .name = "vclk_div12",
2139                 .ops = &clk_fixed_factor_ops,
2140                 .parent_hws = (const struct clk_hw *[]) {
2141                         &gxbb_vclk_div12_en.hw
2142                 },
2143                 .num_parents = 1,
2144         },
2145 };
2146
2147 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2148         .mult = 1,
2149         .div = 2,
2150         .hw.init = &(struct clk_init_data){
2151                 .name = "vclk2_div2",
2152                 .ops = &clk_fixed_factor_ops,
2153                 .parent_hws = (const struct clk_hw *[]) {
2154                         &gxbb_vclk2_div2_en.hw
2155                 },
2156                 .num_parents = 1,
2157         },
2158 };
2159
2160 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2161         .mult = 1,
2162         .div = 4,
2163         .hw.init = &(struct clk_init_data){
2164                 .name = "vclk2_div4",
2165                 .ops = &clk_fixed_factor_ops,
2166                 .parent_hws = (const struct clk_hw *[]) {
2167                         &gxbb_vclk2_div4_en.hw
2168                 },
2169                 .num_parents = 1,
2170         },
2171 };
2172
2173 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2174         .mult = 1,
2175         .div = 6,
2176         .hw.init = &(struct clk_init_data){
2177                 .name = "vclk2_div6",
2178                 .ops = &clk_fixed_factor_ops,
2179                 .parent_hws = (const struct clk_hw *[]) {
2180                         &gxbb_vclk2_div6_en.hw
2181                 },
2182                 .num_parents = 1,
2183         },
2184 };
2185
2186 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2187         .mult = 1,
2188         .div = 12,
2189         .hw.init = &(struct clk_init_data){
2190                 .name = "vclk2_div12",
2191                 .ops = &clk_fixed_factor_ops,
2192                 .parent_hws = (const struct clk_hw *[]) {
2193                         &gxbb_vclk2_div12_en.hw
2194                 },
2195                 .num_parents = 1,
2196         },
2197 };
2198
2199 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2200 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2201         &gxbb_vclk_div1.hw,
2202         &gxbb_vclk_div2.hw,
2203         &gxbb_vclk_div4.hw,
2204         &gxbb_vclk_div6.hw,
2205         &gxbb_vclk_div12.hw,
2206         &gxbb_vclk2_div1.hw,
2207         &gxbb_vclk2_div2.hw,
2208         &gxbb_vclk2_div4.hw,
2209         &gxbb_vclk2_div6.hw,
2210         &gxbb_vclk2_div12.hw,
2211 };
2212
2213 static struct clk_regmap gxbb_cts_enci_sel = {
2214         .data = &(struct clk_regmap_mux_data){
2215                 .offset = HHI_VID_CLK_DIV,
2216                 .mask = 0xf,
2217                 .shift = 28,
2218                 .table = mux_table_cts_sel,
2219         },
2220         .hw.init = &(struct clk_init_data){
2221                 .name = "cts_enci_sel",
2222                 .ops = &clk_regmap_mux_ops,
2223                 .parent_hws = gxbb_cts_parent_hws,
2224                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2225                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2226         },
2227 };
2228
2229 static struct clk_regmap gxbb_cts_encp_sel = {
2230         .data = &(struct clk_regmap_mux_data){
2231                 .offset = HHI_VID_CLK_DIV,
2232                 .mask = 0xf,
2233                 .shift = 20,
2234                 .table = mux_table_cts_sel,
2235         },
2236         .hw.init = &(struct clk_init_data){
2237                 .name = "cts_encp_sel",
2238                 .ops = &clk_regmap_mux_ops,
2239                 .parent_hws = gxbb_cts_parent_hws,
2240                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2241                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2242         },
2243 };
2244
2245 static struct clk_regmap gxbb_cts_vdac_sel = {
2246         .data = &(struct clk_regmap_mux_data){
2247                 .offset = HHI_VIID_CLK_DIV,
2248                 .mask = 0xf,
2249                 .shift = 28,
2250                 .table = mux_table_cts_sel,
2251         },
2252         .hw.init = &(struct clk_init_data){
2253                 .name = "cts_vdac_sel",
2254                 .ops = &clk_regmap_mux_ops,
2255                 .parent_hws = gxbb_cts_parent_hws,
2256                 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2257                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2258         },
2259 };
2260
2261 /* TOFIX: add support for cts_tcon */
2262 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2263 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2264         &gxbb_vclk_div1.hw,
2265         &gxbb_vclk_div2.hw,
2266         &gxbb_vclk_div4.hw,
2267         &gxbb_vclk_div6.hw,
2268         &gxbb_vclk_div12.hw,
2269         &gxbb_vclk2_div1.hw,
2270         &gxbb_vclk2_div2.hw,
2271         &gxbb_vclk2_div4.hw,
2272         &gxbb_vclk2_div6.hw,
2273         &gxbb_vclk2_div12.hw,
2274 };
2275
2276 static struct clk_regmap gxbb_hdmi_tx_sel = {
2277         .data = &(struct clk_regmap_mux_data){
2278                 .offset = HHI_HDMI_CLK_CNTL,
2279                 .mask = 0xf,
2280                 .shift = 16,
2281                 .table = mux_table_hdmi_tx_sel,
2282         },
2283         .hw.init = &(struct clk_init_data){
2284                 .name = "hdmi_tx_sel",
2285                 .ops = &clk_regmap_mux_ops,
2286                 /*
2287                  * bits 31:28 selects from 12 possible parents:
2288                  * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2289                  * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2290                  * cts_tcon
2291                  */
2292                 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2293                 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2294                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2295         },
2296 };
2297
2298 static struct clk_regmap gxbb_cts_enci = {
2299         .data = &(struct clk_regmap_gate_data){
2300                 .offset = HHI_VID_CLK_CNTL2,
2301                 .bit_idx = 0,
2302         },
2303         .hw.init = &(struct clk_init_data) {
2304                 .name = "cts_enci",
2305                 .ops = &clk_regmap_gate_ops,
2306                 .parent_hws = (const struct clk_hw *[]) {
2307                         &gxbb_cts_enci_sel.hw
2308                 },
2309                 .num_parents = 1,
2310                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2311         },
2312 };
2313
2314 static struct clk_regmap gxbb_cts_encp = {
2315         .data = &(struct clk_regmap_gate_data){
2316                 .offset = HHI_VID_CLK_CNTL2,
2317                 .bit_idx = 2,
2318         },
2319         .hw.init = &(struct clk_init_data) {
2320                 .name = "cts_encp",
2321                 .ops = &clk_regmap_gate_ops,
2322                 .parent_hws = (const struct clk_hw *[]) {
2323                         &gxbb_cts_encp_sel.hw
2324                 },
2325                 .num_parents = 1,
2326                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2327         },
2328 };
2329
2330 static struct clk_regmap gxbb_cts_vdac = {
2331         .data = &(struct clk_regmap_gate_data){
2332                 .offset = HHI_VID_CLK_CNTL2,
2333                 .bit_idx = 4,
2334         },
2335         .hw.init = &(struct clk_init_data) {
2336                 .name = "cts_vdac",
2337                 .ops = &clk_regmap_gate_ops,
2338                 .parent_hws = (const struct clk_hw *[]) {
2339                         &gxbb_cts_vdac_sel.hw
2340                 },
2341                 .num_parents = 1,
2342                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2343         },
2344 };
2345
2346 static struct clk_regmap gxbb_hdmi_tx = {
2347         .data = &(struct clk_regmap_gate_data){
2348                 .offset = HHI_VID_CLK_CNTL2,
2349                 .bit_idx = 5,
2350         },
2351         .hw.init = &(struct clk_init_data) {
2352                 .name = "hdmi_tx",
2353                 .ops = &clk_regmap_gate_ops,
2354                 .parent_hws = (const struct clk_hw *[]) {
2355                         &gxbb_hdmi_tx_sel.hw
2356                 },
2357                 .num_parents = 1,
2358                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2359         },
2360 };
2361
2362 /* HDMI Clocks */
2363
2364 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2365         { .fw_name = "xtal", },
2366         { .hw = &gxbb_fclk_div4.hw },
2367         { .hw = &gxbb_fclk_div3.hw },
2368         { .hw = &gxbb_fclk_div5.hw },
2369 };
2370
2371 static struct clk_regmap gxbb_hdmi_sel = {
2372         .data = &(struct clk_regmap_mux_data){
2373                 .offset = HHI_HDMI_CLK_CNTL,
2374                 .mask = 0x3,
2375                 .shift = 9,
2376                 .flags = CLK_MUX_ROUND_CLOSEST,
2377         },
2378         .hw.init = &(struct clk_init_data){
2379                 .name = "hdmi_sel",
2380                 .ops = &clk_regmap_mux_ops,
2381                 .parent_data = gxbb_hdmi_parent_data,
2382                 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2383                 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2384         },
2385 };
2386
2387 static struct clk_regmap gxbb_hdmi_div = {
2388         .data = &(struct clk_regmap_div_data){
2389                 .offset = HHI_HDMI_CLK_CNTL,
2390                 .shift = 0,
2391                 .width = 7,
2392         },
2393         .hw.init = &(struct clk_init_data){
2394                 .name = "hdmi_div",
2395                 .ops = &clk_regmap_divider_ops,
2396                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2397                 .num_parents = 1,
2398                 .flags = CLK_GET_RATE_NOCACHE,
2399         },
2400 };
2401
2402 static struct clk_regmap gxbb_hdmi = {
2403         .data = &(struct clk_regmap_gate_data){
2404                 .offset = HHI_HDMI_CLK_CNTL,
2405                 .bit_idx = 8,
2406         },
2407         .hw.init = &(struct clk_init_data) {
2408                 .name = "hdmi",
2409                 .ops = &clk_regmap_gate_ops,
2410                 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2411                 .num_parents = 1,
2412                 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2413         },
2414 };
2415
2416 /* VDEC clocks */
2417
2418 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2419         &gxbb_fclk_div4.hw,
2420         &gxbb_fclk_div3.hw,
2421         &gxbb_fclk_div5.hw,
2422         &gxbb_fclk_div7.hw,
2423 };
2424
2425 static struct clk_regmap gxbb_vdec_1_sel = {
2426         .data = &(struct clk_regmap_mux_data){
2427                 .offset = HHI_VDEC_CLK_CNTL,
2428                 .mask = 0x3,
2429                 .shift = 9,
2430                 .flags = CLK_MUX_ROUND_CLOSEST,
2431         },
2432         .hw.init = &(struct clk_init_data){
2433                 .name = "vdec_1_sel",
2434                 .ops = &clk_regmap_mux_ops,
2435                 .parent_hws = gxbb_vdec_parent_hws,
2436                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2437                 .flags = CLK_SET_RATE_PARENT,
2438         },
2439 };
2440
2441 static struct clk_regmap gxbb_vdec_1_div = {
2442         .data = &(struct clk_regmap_div_data){
2443                 .offset = HHI_VDEC_CLK_CNTL,
2444                 .shift = 0,
2445                 .width = 7,
2446                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2447         },
2448         .hw.init = &(struct clk_init_data){
2449                 .name = "vdec_1_div",
2450                 .ops = &clk_regmap_divider_ops,
2451                 .parent_hws = (const struct clk_hw *[]) {
2452                         &gxbb_vdec_1_sel.hw
2453                 },
2454                 .num_parents = 1,
2455                 .flags = CLK_SET_RATE_PARENT,
2456         },
2457 };
2458
2459 static struct clk_regmap gxbb_vdec_1 = {
2460         .data = &(struct clk_regmap_gate_data){
2461                 .offset = HHI_VDEC_CLK_CNTL,
2462                 .bit_idx = 8,
2463         },
2464         .hw.init = &(struct clk_init_data) {
2465                 .name = "vdec_1",
2466                 .ops = &clk_regmap_gate_ops,
2467                 .parent_hws = (const struct clk_hw *[]) {
2468                         &gxbb_vdec_1_div.hw
2469                 },
2470                 .num_parents = 1,
2471                 .flags = CLK_SET_RATE_PARENT,
2472         },
2473 };
2474
2475 static struct clk_regmap gxbb_vdec_hevc_sel = {
2476         .data = &(struct clk_regmap_mux_data){
2477                 .offset = HHI_VDEC2_CLK_CNTL,
2478                 .mask = 0x3,
2479                 .shift = 25,
2480                 .flags = CLK_MUX_ROUND_CLOSEST,
2481         },
2482         .hw.init = &(struct clk_init_data){
2483                 .name = "vdec_hevc_sel",
2484                 .ops = &clk_regmap_mux_ops,
2485                 .parent_hws = gxbb_vdec_parent_hws,
2486                 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2487                 .flags = CLK_SET_RATE_PARENT,
2488         },
2489 };
2490
2491 static struct clk_regmap gxbb_vdec_hevc_div = {
2492         .data = &(struct clk_regmap_div_data){
2493                 .offset = HHI_VDEC2_CLK_CNTL,
2494                 .shift = 16,
2495                 .width = 7,
2496                 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2497         },
2498         .hw.init = &(struct clk_init_data){
2499                 .name = "vdec_hevc_div",
2500                 .ops = &clk_regmap_divider_ops,
2501                 .parent_hws = (const struct clk_hw *[]) {
2502                         &gxbb_vdec_hevc_sel.hw
2503                 },
2504                 .num_parents = 1,
2505                 .flags = CLK_SET_RATE_PARENT,
2506         },
2507 };
2508
2509 static struct clk_regmap gxbb_vdec_hevc = {
2510         .data = &(struct clk_regmap_gate_data){
2511                 .offset = HHI_VDEC2_CLK_CNTL,
2512                 .bit_idx = 24,
2513         },
2514         .hw.init = &(struct clk_init_data) {
2515                 .name = "vdec_hevc",
2516                 .ops = &clk_regmap_gate_ops,
2517                 .parent_hws = (const struct clk_hw *[]) {
2518                         &gxbb_vdec_hevc_div.hw
2519                 },
2520                 .num_parents = 1,
2521                 .flags = CLK_SET_RATE_PARENT,
2522         },
2523 };
2524
2525 static u32 mux_table_gen_clk[]  = { 0, 4, 5, 6, 7, 8,
2526                                     9, 10, 11, 13, 14, };
2527 static const struct clk_parent_data gen_clk_parent_data[] = {
2528         { .fw_name = "xtal", },
2529         { .hw = &gxbb_vdec_1.hw },
2530         { .hw = &gxbb_vdec_hevc.hw },
2531         { .hw = &gxbb_mpll0.hw },
2532         { .hw = &gxbb_mpll1.hw },
2533         { .hw = &gxbb_mpll2.hw },
2534         { .hw = &gxbb_fclk_div4.hw },
2535         { .hw = &gxbb_fclk_div3.hw },
2536         { .hw = &gxbb_fclk_div5.hw },
2537         { .hw = &gxbb_fclk_div7.hw },
2538         { .hw = &gxbb_gp0_pll.hw },
2539 };
2540
2541 static struct clk_regmap gxbb_gen_clk_sel = {
2542         .data = &(struct clk_regmap_mux_data){
2543                 .offset = HHI_GEN_CLK_CNTL,
2544                 .mask = 0xf,
2545                 .shift = 12,
2546                 .table = mux_table_gen_clk,
2547         },
2548         .hw.init = &(struct clk_init_data){
2549                 .name = "gen_clk_sel",
2550                 .ops = &clk_regmap_mux_ops,
2551                 /*
2552                  * bits 15:12 selects from 14 possible parents:
2553                  * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2554                  * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2555                  * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2556                  */
2557                 .parent_data = gen_clk_parent_data,
2558                 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2559         },
2560 };
2561
2562 static struct clk_regmap gxbb_gen_clk_div = {
2563         .data = &(struct clk_regmap_div_data){
2564                 .offset = HHI_GEN_CLK_CNTL,
2565                 .shift = 0,
2566                 .width = 11,
2567         },
2568         .hw.init = &(struct clk_init_data){
2569                 .name = "gen_clk_div",
2570                 .ops = &clk_regmap_divider_ops,
2571                 .parent_hws = (const struct clk_hw *[]) {
2572                         &gxbb_gen_clk_sel.hw
2573                 },
2574                 .num_parents = 1,
2575                 .flags = CLK_SET_RATE_PARENT,
2576         },
2577 };
2578
2579 static struct clk_regmap gxbb_gen_clk = {
2580         .data = &(struct clk_regmap_gate_data){
2581                 .offset = HHI_GEN_CLK_CNTL,
2582                 .bit_idx = 7,
2583         },
2584         .hw.init = &(struct clk_init_data){
2585                 .name = "gen_clk",
2586                 .ops = &clk_regmap_gate_ops,
2587                 .parent_hws = (const struct clk_hw *[]) {
2588                         &gxbb_gen_clk_div.hw
2589                 },
2590                 .num_parents = 1,
2591                 .flags = CLK_SET_RATE_PARENT,
2592         },
2593 };
2594
2595 #define MESON_GATE(_name, _reg, _bit) \
2596         MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2597
2598 /* Everything Else (EE) domain gates */
2599 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2600 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2601 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2602 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2603 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2604 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2605 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2606 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2607 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2608 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2609 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2610 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2611 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2612 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2613 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2614 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2615 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2616 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2617 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2618 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2619 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2620 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2621 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2622
2623 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2624 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2625 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2626 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2627 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2628 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2629 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2630 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2631 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2632 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2633 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2634 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2635 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2636 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2637 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2638 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2639 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2640
2641 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2642 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2643 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2644 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2645 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2646 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2647 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2648 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2649 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2650 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2651 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2652 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2653 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2654
2655 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2656 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2657 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2658 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2659 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2660 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2661 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2662 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2663 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2664 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2665 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2666 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2667 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2668 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2669 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2670 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2671
2672 /* Always On (AO) domain gates */
2673
2674 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2675 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2676 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2677 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2678 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2679
2680 /* AIU gates */
2681 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2682 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2683 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2684 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2685 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2686 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2687 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2688 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2689
2690 /* Array of all clocks provided by this provider */
2691
2692 static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
2693         .hws = {
2694                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2695                 [CLKID_HDMI_PLL]            = &gxbb_hdmi_pll.hw,
2696                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2697                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2698                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2699                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2700                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2701                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2702                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2703                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2704                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2705                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2706                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2707                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2708                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2709                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2710                 [CLKID_DOS]                 = &gxbb_dos.hw,
2711                 [CLKID_ISA]                 = &gxbb_isa.hw,
2712                 [CLKID_PL301]               = &gxbb_pl301.hw,
2713                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2714                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2715                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2716                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2717                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2718                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2719                 [CLKID_UART0]               = &gxbb_uart0.hw,
2720                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2721                 [CLKID_STREAM]              = &gxbb_stream.hw,
2722                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2723                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2724                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2725                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2726                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2727                 [CLKID_SPI]                 = &gxbb_spi.hw,
2728                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2729                 [CLKID_ETH]                 = &gxbb_eth.hw,
2730                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2731                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2732                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2733                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2734                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2735                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2736                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2737                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2738                 [CLKID_ADC]                 = &gxbb_adc.hw,
2739                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2740                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2741                 [CLKID_UART1]               = &gxbb_uart1.hw,
2742                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2743                 [CLKID_USB0]                = &gxbb_usb0.hw,
2744                 [CLKID_USB1]                = &gxbb_usb1.hw,
2745                 [CLKID_RESET]               = &gxbb_reset.hw,
2746                 [CLKID_NAND]                = &gxbb_nand.hw,
2747                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2748                 [CLKID_USB]                 = &gxbb_usb.hw,
2749                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2750                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2751                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2752                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2753                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2754                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2755                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2756                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2757                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2758                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2759                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2760                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2761                 [CLKID_UART2]               = &gxbb_uart2.hw,
2762                 [CLKID_SANA]                = &gxbb_sana.hw,
2763                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2764                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2765                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2766                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2767                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2768                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2769                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2770                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2771                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2772                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2773                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2774                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2775                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2776                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2777                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2778                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2779                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2780                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2781                 [CLKID_EDP]                 = &gxbb_edp.hw,
2782                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2783                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2784                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2785                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2786                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2787                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
2788                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
2789                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
2790                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
2791                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
2792                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
2793                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
2794                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
2795                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
2796                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
2797                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
2798                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
2799                 [CLKID_MALI]                = &gxbb_mali.hw,
2800                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
2801                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
2802                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
2803                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
2804                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
2805                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
2806                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
2807                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
2808                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
2809                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
2810                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
2811                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
2812                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
2813                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
2814                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
2815                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
2816                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
2817                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
2818                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
2819                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
2820                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
2821                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
2822                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
2823                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
2824                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
2825                 [CLKID_VPU]                 = &gxbb_vpu.hw,
2826                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
2827                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
2828                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
2829                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
2830                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
2831                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
2832                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
2833                 [CLKID_VAPB]                = &gxbb_vapb.hw,
2834                 [CLKID_HDMI_PLL_PRE_MULT]   = &gxbb_hdmi_pll_pre_mult.hw,
2835                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
2836                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
2837                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
2838                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
2839                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
2840                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
2841                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
2842                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
2843                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
2844                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
2845                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
2846                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
2847                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
2848                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
2849                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
2850                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
2851                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
2852                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
2853                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
2854                 [CLKID_HDMI_PLL_DCO]        = &gxbb_hdmi_pll_dco.hw,
2855                 [CLKID_HDMI_PLL_OD]         = &gxbb_hdmi_pll_od.hw,
2856                 [CLKID_HDMI_PLL_OD2]        = &gxbb_hdmi_pll_od2.hw,
2857                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
2858                 [CLKID_GP0_PLL_DCO]         = &gxbb_gp0_pll_dco.hw,
2859                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
2860                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
2861                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
2862                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
2863                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
2864                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
2865                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
2866                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
2867                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
2868                 [CLKID_VCLK]                = &gxbb_vclk.hw,
2869                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
2870                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
2871                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
2872                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
2873                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
2874                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
2875                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
2876                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
2877                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
2878                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
2879                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
2880                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
2881                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
2882                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
2883                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
2884                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
2885                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
2886                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
2887                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
2888                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
2889                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
2890                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
2891                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
2892                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
2893                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
2894                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
2895                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
2896                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
2897                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
2898                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
2899                 [NR_CLKS]                   = NULL,
2900         },
2901         .num = NR_CLKS,
2902 };
2903
2904 static struct clk_hw_onecell_data gxl_hw_onecell_data = {
2905         .hws = {
2906                 [CLKID_SYS_PLL]             = &gxbb_sys_pll.hw,
2907                 [CLKID_HDMI_PLL]            = &gxl_hdmi_pll.hw,
2908                 [CLKID_FIXED_PLL]           = &gxbb_fixed_pll.hw,
2909                 [CLKID_FCLK_DIV2]           = &gxbb_fclk_div2.hw,
2910                 [CLKID_FCLK_DIV3]           = &gxbb_fclk_div3.hw,
2911                 [CLKID_FCLK_DIV4]           = &gxbb_fclk_div4.hw,
2912                 [CLKID_FCLK_DIV5]           = &gxbb_fclk_div5.hw,
2913                 [CLKID_FCLK_DIV7]           = &gxbb_fclk_div7.hw,
2914                 [CLKID_GP0_PLL]             = &gxbb_gp0_pll.hw,
2915                 [CLKID_MPEG_SEL]            = &gxbb_mpeg_clk_sel.hw,
2916                 [CLKID_MPEG_DIV]            = &gxbb_mpeg_clk_div.hw,
2917                 [CLKID_CLK81]               = &gxbb_clk81.hw,
2918                 [CLKID_MPLL0]               = &gxbb_mpll0.hw,
2919                 [CLKID_MPLL1]               = &gxbb_mpll1.hw,
2920                 [CLKID_MPLL2]               = &gxbb_mpll2.hw,
2921                 [CLKID_DDR]                 = &gxbb_ddr.hw,
2922                 [CLKID_DOS]                 = &gxbb_dos.hw,
2923                 [CLKID_ISA]                 = &gxbb_isa.hw,
2924                 [CLKID_PL301]               = &gxbb_pl301.hw,
2925                 [CLKID_PERIPHS]             = &gxbb_periphs.hw,
2926                 [CLKID_SPICC]               = &gxbb_spicc.hw,
2927                 [CLKID_I2C]                 = &gxbb_i2c.hw,
2928                 [CLKID_SAR_ADC]             = &gxbb_sar_adc.hw,
2929                 [CLKID_SMART_CARD]          = &gxbb_smart_card.hw,
2930                 [CLKID_RNG0]                = &gxbb_rng0.hw,
2931                 [CLKID_UART0]               = &gxbb_uart0.hw,
2932                 [CLKID_SDHC]                = &gxbb_sdhc.hw,
2933                 [CLKID_STREAM]              = &gxbb_stream.hw,
2934                 [CLKID_ASYNC_FIFO]          = &gxbb_async_fifo.hw,
2935                 [CLKID_SDIO]                = &gxbb_sdio.hw,
2936                 [CLKID_ABUF]                = &gxbb_abuf.hw,
2937                 [CLKID_HIU_IFACE]           = &gxbb_hiu_iface.hw,
2938                 [CLKID_ASSIST_MISC]         = &gxbb_assist_misc.hw,
2939                 [CLKID_SPI]                 = &gxbb_spi.hw,
2940                 [CLKID_I2S_SPDIF]           = &gxbb_i2s_spdif.hw,
2941                 [CLKID_ETH]                 = &gxbb_eth.hw,
2942                 [CLKID_DEMUX]               = &gxbb_demux.hw,
2943                 [CLKID_AIU_GLUE]            = &gxbb_aiu_glue.hw,
2944                 [CLKID_IEC958]              = &gxbb_iec958.hw,
2945                 [CLKID_I2S_OUT]             = &gxbb_i2s_out.hw,
2946                 [CLKID_AMCLK]               = &gxbb_amclk.hw,
2947                 [CLKID_AIFIFO2]             = &gxbb_aififo2.hw,
2948                 [CLKID_MIXER]               = &gxbb_mixer.hw,
2949                 [CLKID_MIXER_IFACE]         = &gxbb_mixer_iface.hw,
2950                 [CLKID_ADC]                 = &gxbb_adc.hw,
2951                 [CLKID_BLKMV]               = &gxbb_blkmv.hw,
2952                 [CLKID_AIU]                 = &gxbb_aiu.hw,
2953                 [CLKID_UART1]               = &gxbb_uart1.hw,
2954                 [CLKID_G2D]                 = &gxbb_g2d.hw,
2955                 [CLKID_USB0]                = &gxbb_usb0.hw,
2956                 [CLKID_USB1]                = &gxbb_usb1.hw,
2957                 [CLKID_RESET]               = &gxbb_reset.hw,
2958                 [CLKID_NAND]                = &gxbb_nand.hw,
2959                 [CLKID_DOS_PARSER]          = &gxbb_dos_parser.hw,
2960                 [CLKID_USB]                 = &gxbb_usb.hw,
2961                 [CLKID_VDIN1]               = &gxbb_vdin1.hw,
2962                 [CLKID_AHB_ARB0]            = &gxbb_ahb_arb0.hw,
2963                 [CLKID_EFUSE]               = &gxbb_efuse.hw,
2964                 [CLKID_BOOT_ROM]            = &gxbb_boot_rom.hw,
2965                 [CLKID_AHB_DATA_BUS]        = &gxbb_ahb_data_bus.hw,
2966                 [CLKID_AHB_CTRL_BUS]        = &gxbb_ahb_ctrl_bus.hw,
2967                 [CLKID_HDMI_INTR_SYNC]      = &gxbb_hdmi_intr_sync.hw,
2968                 [CLKID_HDMI_PCLK]           = &gxbb_hdmi_pclk.hw,
2969                 [CLKID_USB1_DDR_BRIDGE]     = &gxbb_usb1_ddr_bridge.hw,
2970                 [CLKID_USB0_DDR_BRIDGE]     = &gxbb_usb0_ddr_bridge.hw,
2971                 [CLKID_MMC_PCLK]            = &gxbb_mmc_pclk.hw,
2972                 [CLKID_DVIN]                = &gxbb_dvin.hw,
2973                 [CLKID_UART2]               = &gxbb_uart2.hw,
2974                 [CLKID_SANA]                = &gxbb_sana.hw,
2975                 [CLKID_VPU_INTR]            = &gxbb_vpu_intr.hw,
2976                 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2977                 [CLKID_CLK81_A53]           = &gxbb_clk81_a53.hw,
2978                 [CLKID_VCLK2_VENCI0]        = &gxbb_vclk2_venci0.hw,
2979                 [CLKID_VCLK2_VENCI1]        = &gxbb_vclk2_venci1.hw,
2980                 [CLKID_VCLK2_VENCP0]        = &gxbb_vclk2_vencp0.hw,
2981                 [CLKID_VCLK2_VENCP1]        = &gxbb_vclk2_vencp1.hw,
2982                 [CLKID_GCLK_VENCI_INT0]     = &gxbb_gclk_venci_int0.hw,
2983                 [CLKID_GCLK_VENCI_INT]      = &gxbb_gclk_vencp_int.hw,
2984                 [CLKID_DAC_CLK]             = &gxbb_dac_clk.hw,
2985                 [CLKID_AOCLK_GATE]          = &gxbb_aoclk_gate.hw,
2986                 [CLKID_IEC958_GATE]         = &gxbb_iec958_gate.hw,
2987                 [CLKID_ENC480P]             = &gxbb_enc480p.hw,
2988                 [CLKID_RNG1]                = &gxbb_rng1.hw,
2989                 [CLKID_GCLK_VENCI_INT1]     = &gxbb_gclk_venci_int1.hw,
2990                 [CLKID_VCLK2_VENCLMCC]      = &gxbb_vclk2_venclmcc.hw,
2991                 [CLKID_VCLK2_VENCL]         = &gxbb_vclk2_vencl.hw,
2992                 [CLKID_VCLK_OTHER]          = &gxbb_vclk_other.hw,
2993                 [CLKID_EDP]                 = &gxbb_edp.hw,
2994                 [CLKID_AO_MEDIA_CPU]        = &gxbb_ao_media_cpu.hw,
2995                 [CLKID_AO_AHB_SRAM]         = &gxbb_ao_ahb_sram.hw,
2996                 [CLKID_AO_AHB_BUS]          = &gxbb_ao_ahb_bus.hw,
2997                 [CLKID_AO_IFACE]            = &gxbb_ao_iface.hw,
2998                 [CLKID_AO_I2C]              = &gxbb_ao_i2c.hw,
2999                 [CLKID_SD_EMMC_A]           = &gxbb_emmc_a.hw,
3000                 [CLKID_SD_EMMC_B]           = &gxbb_emmc_b.hw,
3001                 [CLKID_SD_EMMC_C]           = &gxbb_emmc_c.hw,
3002                 [CLKID_SAR_ADC_CLK]         = &gxbb_sar_adc_clk.hw,
3003                 [CLKID_SAR_ADC_SEL]         = &gxbb_sar_adc_clk_sel.hw,
3004                 [CLKID_SAR_ADC_DIV]         = &gxbb_sar_adc_clk_div.hw,
3005                 [CLKID_MALI_0_SEL]          = &gxbb_mali_0_sel.hw,
3006                 [CLKID_MALI_0_DIV]          = &gxbb_mali_0_div.hw,
3007                 [CLKID_MALI_0]              = &gxbb_mali_0.hw,
3008                 [CLKID_MALI_1_SEL]          = &gxbb_mali_1_sel.hw,
3009                 [CLKID_MALI_1_DIV]          = &gxbb_mali_1_div.hw,
3010                 [CLKID_MALI_1]              = &gxbb_mali_1.hw,
3011                 [CLKID_MALI]                = &gxbb_mali.hw,
3012                 [CLKID_CTS_AMCLK]           = &gxbb_cts_amclk.hw,
3013                 [CLKID_CTS_AMCLK_SEL]       = &gxbb_cts_amclk_sel.hw,
3014                 [CLKID_CTS_AMCLK_DIV]       = &gxbb_cts_amclk_div.hw,
3015                 [CLKID_CTS_MCLK_I958]       = &gxbb_cts_mclk_i958.hw,
3016                 [CLKID_CTS_MCLK_I958_SEL]   = &gxbb_cts_mclk_i958_sel.hw,
3017                 [CLKID_CTS_MCLK_I958_DIV]   = &gxbb_cts_mclk_i958_div.hw,
3018                 [CLKID_CTS_I958]            = &gxbb_cts_i958.hw,
3019                 [CLKID_32K_CLK]             = &gxbb_32k_clk.hw,
3020                 [CLKID_32K_CLK_SEL]         = &gxbb_32k_clk_sel.hw,
3021                 [CLKID_32K_CLK_DIV]         = &gxbb_32k_clk_div.hw,
3022                 [CLKID_SD_EMMC_A_CLK0_SEL]  = &gxbb_sd_emmc_a_clk0_sel.hw,
3023                 [CLKID_SD_EMMC_A_CLK0_DIV]  = &gxbb_sd_emmc_a_clk0_div.hw,
3024                 [CLKID_SD_EMMC_A_CLK0]      = &gxbb_sd_emmc_a_clk0.hw,
3025                 [CLKID_SD_EMMC_B_CLK0_SEL]  = &gxbb_sd_emmc_b_clk0_sel.hw,
3026                 [CLKID_SD_EMMC_B_CLK0_DIV]  = &gxbb_sd_emmc_b_clk0_div.hw,
3027                 [CLKID_SD_EMMC_B_CLK0]      = &gxbb_sd_emmc_b_clk0.hw,
3028                 [CLKID_SD_EMMC_C_CLK0_SEL]  = &gxbb_sd_emmc_c_clk0_sel.hw,
3029                 [CLKID_SD_EMMC_C_CLK0_DIV]  = &gxbb_sd_emmc_c_clk0_div.hw,
3030                 [CLKID_SD_EMMC_C_CLK0]      = &gxbb_sd_emmc_c_clk0.hw,
3031                 [CLKID_VPU_0_SEL]           = &gxbb_vpu_0_sel.hw,
3032                 [CLKID_VPU_0_DIV]           = &gxbb_vpu_0_div.hw,
3033                 [CLKID_VPU_0]               = &gxbb_vpu_0.hw,
3034                 [CLKID_VPU_1_SEL]           = &gxbb_vpu_1_sel.hw,
3035                 [CLKID_VPU_1_DIV]           = &gxbb_vpu_1_div.hw,
3036                 [CLKID_VPU_1]               = &gxbb_vpu_1.hw,
3037                 [CLKID_VPU]                 = &gxbb_vpu.hw,
3038                 [CLKID_VAPB_0_SEL]          = &gxbb_vapb_0_sel.hw,
3039                 [CLKID_VAPB_0_DIV]          = &gxbb_vapb_0_div.hw,
3040                 [CLKID_VAPB_0]              = &gxbb_vapb_0.hw,
3041                 [CLKID_VAPB_1_SEL]          = &gxbb_vapb_1_sel.hw,
3042                 [CLKID_VAPB_1_DIV]          = &gxbb_vapb_1_div.hw,
3043                 [CLKID_VAPB_1]              = &gxbb_vapb_1.hw,
3044                 [CLKID_VAPB_SEL]            = &gxbb_vapb_sel.hw,
3045                 [CLKID_VAPB]                = &gxbb_vapb.hw,
3046                 [CLKID_MPLL0_DIV]           = &gxbb_mpll0_div.hw,
3047                 [CLKID_MPLL1_DIV]           = &gxbb_mpll1_div.hw,
3048                 [CLKID_MPLL2_DIV]           = &gxbb_mpll2_div.hw,
3049                 [CLKID_MPLL_PREDIV]         = &gxbb_mpll_prediv.hw,
3050                 [CLKID_FCLK_DIV2_DIV]       = &gxbb_fclk_div2_div.hw,
3051                 [CLKID_FCLK_DIV3_DIV]       = &gxbb_fclk_div3_div.hw,
3052                 [CLKID_FCLK_DIV4_DIV]       = &gxbb_fclk_div4_div.hw,
3053                 [CLKID_FCLK_DIV5_DIV]       = &gxbb_fclk_div5_div.hw,
3054                 [CLKID_FCLK_DIV7_DIV]       = &gxbb_fclk_div7_div.hw,
3055                 [CLKID_VDEC_1_SEL]          = &gxbb_vdec_1_sel.hw,
3056                 [CLKID_VDEC_1_DIV]          = &gxbb_vdec_1_div.hw,
3057                 [CLKID_VDEC_1]              = &gxbb_vdec_1.hw,
3058                 [CLKID_VDEC_HEVC_SEL]       = &gxbb_vdec_hevc_sel.hw,
3059                 [CLKID_VDEC_HEVC_DIV]       = &gxbb_vdec_hevc_div.hw,
3060                 [CLKID_VDEC_HEVC]           = &gxbb_vdec_hevc.hw,
3061                 [CLKID_GEN_CLK_SEL]         = &gxbb_gen_clk_sel.hw,
3062                 [CLKID_GEN_CLK_DIV]         = &gxbb_gen_clk_div.hw,
3063                 [CLKID_GEN_CLK]             = &gxbb_gen_clk.hw,
3064                 [CLKID_FIXED_PLL_DCO]       = &gxbb_fixed_pll_dco.hw,
3065                 [CLKID_HDMI_PLL_DCO]        = &gxl_hdmi_pll_dco.hw,
3066                 [CLKID_HDMI_PLL_OD]         = &gxl_hdmi_pll_od.hw,
3067                 [CLKID_HDMI_PLL_OD2]        = &gxl_hdmi_pll_od2.hw,
3068                 [CLKID_SYS_PLL_DCO]         = &gxbb_sys_pll_dco.hw,
3069                 [CLKID_GP0_PLL_DCO]         = &gxl_gp0_pll_dco.hw,
3070                 [CLKID_VID_PLL_DIV]         = &gxbb_vid_pll_div.hw,
3071                 [CLKID_VID_PLL_SEL]         = &gxbb_vid_pll_sel.hw,
3072                 [CLKID_VID_PLL]             = &gxbb_vid_pll.hw,
3073                 [CLKID_VCLK_SEL]            = &gxbb_vclk_sel.hw,
3074                 [CLKID_VCLK2_SEL]           = &gxbb_vclk2_sel.hw,
3075                 [CLKID_VCLK_INPUT]          = &gxbb_vclk_input.hw,
3076                 [CLKID_VCLK2_INPUT]         = &gxbb_vclk2_input.hw,
3077                 [CLKID_VCLK_DIV]            = &gxbb_vclk_div.hw,
3078                 [CLKID_VCLK2_DIV]           = &gxbb_vclk2_div.hw,
3079                 [CLKID_VCLK]                = &gxbb_vclk.hw,
3080                 [CLKID_VCLK2]               = &gxbb_vclk2.hw,
3081                 [CLKID_VCLK_DIV1]           = &gxbb_vclk_div1.hw,
3082                 [CLKID_VCLK_DIV2_EN]        = &gxbb_vclk_div2_en.hw,
3083                 [CLKID_VCLK_DIV2]           = &gxbb_vclk_div2.hw,
3084                 [CLKID_VCLK_DIV4_EN]        = &gxbb_vclk_div4_en.hw,
3085                 [CLKID_VCLK_DIV4]           = &gxbb_vclk_div4.hw,
3086                 [CLKID_VCLK_DIV6_EN]        = &gxbb_vclk_div6_en.hw,
3087                 [CLKID_VCLK_DIV6]           = &gxbb_vclk_div6.hw,
3088                 [CLKID_VCLK_DIV12_EN]       = &gxbb_vclk_div12_en.hw,
3089                 [CLKID_VCLK_DIV12]          = &gxbb_vclk_div12.hw,
3090                 [CLKID_VCLK2_DIV1]          = &gxbb_vclk2_div1.hw,
3091                 [CLKID_VCLK2_DIV2_EN]       = &gxbb_vclk2_div2_en.hw,
3092                 [CLKID_VCLK2_DIV2]          = &gxbb_vclk2_div2.hw,
3093                 [CLKID_VCLK2_DIV4_EN]       = &gxbb_vclk2_div4_en.hw,
3094                 [CLKID_VCLK2_DIV4]          = &gxbb_vclk2_div4.hw,
3095                 [CLKID_VCLK2_DIV6_EN]       = &gxbb_vclk2_div6_en.hw,
3096                 [CLKID_VCLK2_DIV6]          = &gxbb_vclk2_div6.hw,
3097                 [CLKID_VCLK2_DIV12_EN]      = &gxbb_vclk2_div12_en.hw,
3098                 [CLKID_VCLK2_DIV12]         = &gxbb_vclk2_div12.hw,
3099                 [CLKID_CTS_ENCI_SEL]        = &gxbb_cts_enci_sel.hw,
3100                 [CLKID_CTS_ENCP_SEL]        = &gxbb_cts_encp_sel.hw,
3101                 [CLKID_CTS_VDAC_SEL]        = &gxbb_cts_vdac_sel.hw,
3102                 [CLKID_HDMI_TX_SEL]         = &gxbb_hdmi_tx_sel.hw,
3103                 [CLKID_CTS_ENCI]            = &gxbb_cts_enci.hw,
3104                 [CLKID_CTS_ENCP]            = &gxbb_cts_encp.hw,
3105                 [CLKID_CTS_VDAC]            = &gxbb_cts_vdac.hw,
3106                 [CLKID_HDMI_TX]             = &gxbb_hdmi_tx.hw,
3107                 [CLKID_HDMI_SEL]            = &gxbb_hdmi_sel.hw,
3108                 [CLKID_HDMI_DIV]            = &gxbb_hdmi_div.hw,
3109                 [CLKID_HDMI]                = &gxbb_hdmi.hw,
3110                 [CLKID_ACODEC]              = &gxl_acodec.hw,
3111                 [NR_CLKS]                   = NULL,
3112         },
3113         .num = NR_CLKS,
3114 };
3115
3116 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3117         &gxbb_clk81,
3118         &gxbb_ddr,
3119         &gxbb_dos,
3120         &gxbb_isa,
3121         &gxbb_pl301,
3122         &gxbb_periphs,
3123         &gxbb_spicc,
3124         &gxbb_i2c,
3125         &gxbb_sar_adc,
3126         &gxbb_smart_card,
3127         &gxbb_rng0,
3128         &gxbb_uart0,
3129         &gxbb_sdhc,
3130         &gxbb_stream,
3131         &gxbb_async_fifo,
3132         &gxbb_sdio,
3133         &gxbb_abuf,
3134         &gxbb_hiu_iface,
3135         &gxbb_assist_misc,
3136         &gxbb_spi,
3137         &gxbb_i2s_spdif,
3138         &gxbb_eth,
3139         &gxbb_demux,
3140         &gxbb_aiu_glue,
3141         &gxbb_iec958,
3142         &gxbb_i2s_out,
3143         &gxbb_amclk,
3144         &gxbb_aififo2,
3145         &gxbb_mixer,
3146         &gxbb_mixer_iface,
3147         &gxbb_adc,
3148         &gxbb_blkmv,
3149         &gxbb_aiu,
3150         &gxbb_uart1,
3151         &gxbb_g2d,
3152         &gxbb_usb0,
3153         &gxbb_usb1,
3154         &gxbb_reset,
3155         &gxbb_nand,
3156         &gxbb_dos_parser,
3157         &gxbb_usb,
3158         &gxbb_vdin1,
3159         &gxbb_ahb_arb0,
3160         &gxbb_efuse,
3161         &gxbb_boot_rom,
3162         &gxbb_ahb_data_bus,
3163         &gxbb_ahb_ctrl_bus,
3164         &gxbb_hdmi_intr_sync,
3165         &gxbb_hdmi_pclk,
3166         &gxbb_usb1_ddr_bridge,
3167         &gxbb_usb0_ddr_bridge,
3168         &gxbb_mmc_pclk,
3169         &gxbb_dvin,
3170         &gxbb_uart2,
3171         &gxbb_sana,
3172         &gxbb_vpu_intr,
3173         &gxbb_sec_ahb_ahb3_bridge,
3174         &gxbb_clk81_a53,
3175         &gxbb_vclk2_venci0,
3176         &gxbb_vclk2_venci1,
3177         &gxbb_vclk2_vencp0,
3178         &gxbb_vclk2_vencp1,
3179         &gxbb_gclk_venci_int0,
3180         &gxbb_gclk_vencp_int,
3181         &gxbb_dac_clk,
3182         &gxbb_aoclk_gate,
3183         &gxbb_iec958_gate,
3184         &gxbb_enc480p,
3185         &gxbb_rng1,
3186         &gxbb_gclk_venci_int1,
3187         &gxbb_vclk2_venclmcc,
3188         &gxbb_vclk2_vencl,
3189         &gxbb_vclk_other,
3190         &gxbb_edp,
3191         &gxbb_ao_media_cpu,
3192         &gxbb_ao_ahb_sram,
3193         &gxbb_ao_ahb_bus,
3194         &gxbb_ao_iface,
3195         &gxbb_ao_i2c,
3196         &gxbb_emmc_a,
3197         &gxbb_emmc_b,
3198         &gxbb_emmc_c,
3199         &gxbb_sar_adc_clk,
3200         &gxbb_mali_0,
3201         &gxbb_mali_1,
3202         &gxbb_cts_amclk,
3203         &gxbb_cts_mclk_i958,
3204         &gxbb_32k_clk,
3205         &gxbb_sd_emmc_a_clk0,
3206         &gxbb_sd_emmc_b_clk0,
3207         &gxbb_sd_emmc_c_clk0,
3208         &gxbb_vpu_0,
3209         &gxbb_vpu_1,
3210         &gxbb_vapb_0,
3211         &gxbb_vapb_1,
3212         &gxbb_vapb,
3213         &gxbb_mpeg_clk_div,
3214         &gxbb_sar_adc_clk_div,
3215         &gxbb_mali_0_div,
3216         &gxbb_mali_1_div,
3217         &gxbb_cts_mclk_i958_div,
3218         &gxbb_32k_clk_div,
3219         &gxbb_sd_emmc_a_clk0_div,
3220         &gxbb_sd_emmc_b_clk0_div,
3221         &gxbb_sd_emmc_c_clk0_div,
3222         &gxbb_vpu_0_div,
3223         &gxbb_vpu_1_div,
3224         &gxbb_vapb_0_div,
3225         &gxbb_vapb_1_div,
3226         &gxbb_mpeg_clk_sel,
3227         &gxbb_sar_adc_clk_sel,
3228         &gxbb_mali_0_sel,
3229         &gxbb_mali_1_sel,
3230         &gxbb_mali,
3231         &gxbb_cts_amclk_sel,
3232         &gxbb_cts_mclk_i958_sel,
3233         &gxbb_cts_i958,
3234         &gxbb_32k_clk_sel,
3235         &gxbb_sd_emmc_a_clk0_sel,
3236         &gxbb_sd_emmc_b_clk0_sel,
3237         &gxbb_sd_emmc_c_clk0_sel,
3238         &gxbb_vpu_0_sel,
3239         &gxbb_vpu_1_sel,
3240         &gxbb_vpu,
3241         &gxbb_vapb_0_sel,
3242         &gxbb_vapb_1_sel,
3243         &gxbb_vapb_sel,
3244         &gxbb_mpll0,
3245         &gxbb_mpll1,
3246         &gxbb_mpll2,
3247         &gxbb_mpll0_div,
3248         &gxbb_mpll1_div,
3249         &gxbb_mpll2_div,
3250         &gxbb_cts_amclk_div,
3251         &gxbb_fixed_pll,
3252         &gxbb_sys_pll,
3253         &gxbb_mpll_prediv,
3254         &gxbb_fclk_div2,
3255         &gxbb_fclk_div3,
3256         &gxbb_fclk_div4,
3257         &gxbb_fclk_div5,
3258         &gxbb_fclk_div7,
3259         &gxbb_vdec_1_sel,
3260         &gxbb_vdec_1_div,
3261         &gxbb_vdec_1,
3262         &gxbb_vdec_hevc_sel,
3263         &gxbb_vdec_hevc_div,
3264         &gxbb_vdec_hevc,
3265         &gxbb_gen_clk_sel,
3266         &gxbb_gen_clk_div,
3267         &gxbb_gen_clk,
3268         &gxbb_fixed_pll_dco,
3269         &gxbb_sys_pll_dco,
3270         &gxbb_gp0_pll,
3271         &gxbb_vid_pll,
3272         &gxbb_vid_pll_sel,
3273         &gxbb_vid_pll_div,
3274         &gxbb_vclk,
3275         &gxbb_vclk_sel,
3276         &gxbb_vclk_div,
3277         &gxbb_vclk_input,
3278         &gxbb_vclk_div1,
3279         &gxbb_vclk_div2_en,
3280         &gxbb_vclk_div4_en,
3281         &gxbb_vclk_div6_en,
3282         &gxbb_vclk_div12_en,
3283         &gxbb_vclk2,
3284         &gxbb_vclk2_sel,
3285         &gxbb_vclk2_div,
3286         &gxbb_vclk2_input,
3287         &gxbb_vclk2_div1,
3288         &gxbb_vclk2_div2_en,
3289         &gxbb_vclk2_div4_en,
3290         &gxbb_vclk2_div6_en,
3291         &gxbb_vclk2_div12_en,
3292         &gxbb_cts_enci,
3293         &gxbb_cts_enci_sel,
3294         &gxbb_cts_encp,
3295         &gxbb_cts_encp_sel,
3296         &gxbb_cts_vdac,
3297         &gxbb_cts_vdac_sel,
3298         &gxbb_hdmi_tx,
3299         &gxbb_hdmi_tx_sel,
3300         &gxbb_hdmi_sel,
3301         &gxbb_hdmi_div,
3302         &gxbb_hdmi,
3303         &gxbb_gp0_pll_dco,
3304         &gxbb_hdmi_pll,
3305         &gxbb_hdmi_pll_od,
3306         &gxbb_hdmi_pll_od2,
3307         &gxbb_hdmi_pll_dco,
3308 };
3309
3310 static struct clk_regmap *const gxl_clk_regmaps[] = {
3311         &gxbb_clk81,
3312         &gxbb_ddr,
3313         &gxbb_dos,
3314         &gxbb_isa,
3315         &gxbb_pl301,
3316         &gxbb_periphs,
3317         &gxbb_spicc,
3318         &gxbb_i2c,
3319         &gxbb_sar_adc,
3320         &gxbb_smart_card,
3321         &gxbb_rng0,
3322         &gxbb_uart0,
3323         &gxbb_sdhc,
3324         &gxbb_stream,
3325         &gxbb_async_fifo,
3326         &gxbb_sdio,
3327         &gxbb_abuf,
3328         &gxbb_hiu_iface,
3329         &gxbb_assist_misc,
3330         &gxbb_spi,
3331         &gxbb_i2s_spdif,
3332         &gxbb_eth,
3333         &gxbb_demux,
3334         &gxbb_aiu_glue,
3335         &gxbb_iec958,
3336         &gxbb_i2s_out,
3337         &gxbb_amclk,
3338         &gxbb_aififo2,
3339         &gxbb_mixer,
3340         &gxbb_mixer_iface,
3341         &gxbb_adc,
3342         &gxbb_blkmv,
3343         &gxbb_aiu,
3344         &gxbb_uart1,
3345         &gxbb_g2d,
3346         &gxbb_usb0,
3347         &gxbb_usb1,
3348         &gxbb_reset,
3349         &gxbb_nand,
3350         &gxbb_dos_parser,
3351         &gxbb_usb,
3352         &gxbb_vdin1,
3353         &gxbb_ahb_arb0,
3354         &gxbb_efuse,
3355         &gxbb_boot_rom,
3356         &gxbb_ahb_data_bus,
3357         &gxbb_ahb_ctrl_bus,
3358         &gxbb_hdmi_intr_sync,
3359         &gxbb_hdmi_pclk,
3360         &gxbb_usb1_ddr_bridge,
3361         &gxbb_usb0_ddr_bridge,
3362         &gxbb_mmc_pclk,
3363         &gxbb_dvin,
3364         &gxbb_uart2,
3365         &gxbb_sana,
3366         &gxbb_vpu_intr,
3367         &gxbb_sec_ahb_ahb3_bridge,
3368         &gxbb_clk81_a53,
3369         &gxbb_vclk2_venci0,
3370         &gxbb_vclk2_venci1,
3371         &gxbb_vclk2_vencp0,
3372         &gxbb_vclk2_vencp1,
3373         &gxbb_gclk_venci_int0,
3374         &gxbb_gclk_vencp_int,
3375         &gxbb_dac_clk,
3376         &gxbb_aoclk_gate,
3377         &gxbb_iec958_gate,
3378         &gxbb_enc480p,
3379         &gxbb_rng1,
3380         &gxbb_gclk_venci_int1,
3381         &gxbb_vclk2_venclmcc,
3382         &gxbb_vclk2_vencl,
3383         &gxbb_vclk_other,
3384         &gxbb_edp,
3385         &gxbb_ao_media_cpu,
3386         &gxbb_ao_ahb_sram,
3387         &gxbb_ao_ahb_bus,
3388         &gxbb_ao_iface,
3389         &gxbb_ao_i2c,
3390         &gxbb_emmc_a,
3391         &gxbb_emmc_b,
3392         &gxbb_emmc_c,
3393         &gxbb_sar_adc_clk,
3394         &gxbb_mali_0,
3395         &gxbb_mali_1,
3396         &gxbb_cts_amclk,
3397         &gxbb_cts_mclk_i958,
3398         &gxbb_32k_clk,
3399         &gxbb_sd_emmc_a_clk0,
3400         &gxbb_sd_emmc_b_clk0,
3401         &gxbb_sd_emmc_c_clk0,
3402         &gxbb_vpu_0,
3403         &gxbb_vpu_1,
3404         &gxbb_vapb_0,
3405         &gxbb_vapb_1,
3406         &gxbb_vapb,
3407         &gxbb_mpeg_clk_div,
3408         &gxbb_sar_adc_clk_div,
3409         &gxbb_mali_0_div,
3410         &gxbb_mali_1_div,
3411         &gxbb_cts_mclk_i958_div,
3412         &gxbb_32k_clk_div,
3413         &gxbb_sd_emmc_a_clk0_div,
3414         &gxbb_sd_emmc_b_clk0_div,
3415         &gxbb_sd_emmc_c_clk0_div,
3416         &gxbb_vpu_0_div,
3417         &gxbb_vpu_1_div,
3418         &gxbb_vapb_0_div,
3419         &gxbb_vapb_1_div,
3420         &gxbb_mpeg_clk_sel,
3421         &gxbb_sar_adc_clk_sel,
3422         &gxbb_mali_0_sel,
3423         &gxbb_mali_1_sel,
3424         &gxbb_mali,
3425         &gxbb_cts_amclk_sel,
3426         &gxbb_cts_mclk_i958_sel,
3427         &gxbb_cts_i958,
3428         &gxbb_32k_clk_sel,
3429         &gxbb_sd_emmc_a_clk0_sel,
3430         &gxbb_sd_emmc_b_clk0_sel,
3431         &gxbb_sd_emmc_c_clk0_sel,
3432         &gxbb_vpu_0_sel,
3433         &gxbb_vpu_1_sel,
3434         &gxbb_vpu,
3435         &gxbb_vapb_0_sel,
3436         &gxbb_vapb_1_sel,
3437         &gxbb_vapb_sel,
3438         &gxbb_mpll0,
3439         &gxbb_mpll1,
3440         &gxbb_mpll2,
3441         &gxbb_mpll0_div,
3442         &gxbb_mpll1_div,
3443         &gxbb_mpll2_div,
3444         &gxbb_cts_amclk_div,
3445         &gxbb_fixed_pll,
3446         &gxbb_sys_pll,
3447         &gxbb_mpll_prediv,
3448         &gxbb_fclk_div2,
3449         &gxbb_fclk_div3,
3450         &gxbb_fclk_div4,
3451         &gxbb_fclk_div5,
3452         &gxbb_fclk_div7,
3453         &gxbb_vdec_1_sel,
3454         &gxbb_vdec_1_div,
3455         &gxbb_vdec_1,
3456         &gxbb_vdec_hevc_sel,
3457         &gxbb_vdec_hevc_div,
3458         &gxbb_vdec_hevc,
3459         &gxbb_gen_clk_sel,
3460         &gxbb_gen_clk_div,
3461         &gxbb_gen_clk,
3462         &gxbb_fixed_pll_dco,
3463         &gxbb_sys_pll_dco,
3464         &gxbb_gp0_pll,
3465         &gxbb_vid_pll,
3466         &gxbb_vid_pll_sel,
3467         &gxbb_vid_pll_div,
3468         &gxbb_vclk,
3469         &gxbb_vclk_sel,
3470         &gxbb_vclk_div,
3471         &gxbb_vclk_input,
3472         &gxbb_vclk_div1,
3473         &gxbb_vclk_div2_en,
3474         &gxbb_vclk_div4_en,
3475         &gxbb_vclk_div6_en,
3476         &gxbb_vclk_div12_en,
3477         &gxbb_vclk2,
3478         &gxbb_vclk2_sel,
3479         &gxbb_vclk2_div,
3480         &gxbb_vclk2_input,
3481         &gxbb_vclk2_div1,
3482         &gxbb_vclk2_div2_en,
3483         &gxbb_vclk2_div4_en,
3484         &gxbb_vclk2_div6_en,
3485         &gxbb_vclk2_div12_en,
3486         &gxbb_cts_enci,
3487         &gxbb_cts_enci_sel,
3488         &gxbb_cts_encp,
3489         &gxbb_cts_encp_sel,
3490         &gxbb_cts_vdac,
3491         &gxbb_cts_vdac_sel,
3492         &gxbb_hdmi_tx,
3493         &gxbb_hdmi_tx_sel,
3494         &gxbb_hdmi_sel,
3495         &gxbb_hdmi_div,
3496         &gxbb_hdmi,
3497         &gxl_gp0_pll_dco,
3498         &gxl_hdmi_pll,
3499         &gxl_hdmi_pll_od,
3500         &gxl_hdmi_pll_od2,
3501         &gxl_hdmi_pll_dco,
3502         &gxl_acodec,
3503 };
3504
3505 static const struct meson_eeclkc_data gxbb_clkc_data = {
3506         .regmap_clks = gxbb_clk_regmaps,
3507         .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3508         .hw_onecell_data = &gxbb_hw_onecell_data,
3509 };
3510
3511 static const struct meson_eeclkc_data gxl_clkc_data = {
3512         .regmap_clks = gxl_clk_regmaps,
3513         .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3514         .hw_onecell_data = &gxl_hw_onecell_data,
3515 };
3516
3517 static const struct of_device_id clkc_match_table[] = {
3518         { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3519         { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3520         {},
3521 };
3522
3523 static struct platform_driver gxbb_driver = {
3524         .probe          = meson_eeclkc_probe,
3525         .driver         = {
3526                 .name   = "gxbb-clkc",
3527                 .of_match_table = clkc_match_table,
3528         },
3529 };
3530
3531 builtin_platform_driver(gxbb_driver);