2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright (c) 2016 AmLogic, Inc.
8 * Author: Michael Turquette <mturquette@baylibre.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
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17 * General Public License for more details.
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21 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution
23 * in the file called COPYING
27 * Copyright (c) 2016 AmLogic, Inc.
28 * Author: Michael Turquette <mturquette@baylibre.com>
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31 * modification, are permitted provided that the following conditions
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58 * MultiPhase Locked Loops are outputs from a PLL with additional frequency
59 * scaling capabilities. MPLL rates are calculated as:
61 * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
64 #include <linux/clk-provider.h>
71 #define to_meson_clk_mpll(_hw) container_of(_hw, struct meson_clk_mpll, hw)
73 static long rate_from_params(unsigned long parent_rate,
77 unsigned long divisor = (SDM_DEN * n2) + sdm;
82 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
85 static void params_from_rate(unsigned long requested_rate,
86 unsigned long parent_rate,
90 uint64_t div = parent_rate;
91 unsigned long rem = do_div(div, requested_rate);
96 } else if (div > N2_MAX) {
101 *sdm = DIV_ROUND_UP_ULL((u64)rem * SDM_DEN, requested_rate);
105 static unsigned long mpll_recalc_rate(struct clk_hw *hw,
106 unsigned long parent_rate)
108 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
110 unsigned long reg, sdm, n2;
114 reg = readl(mpll->base + p->reg_off);
115 sdm = PARM_GET(p->width, p->shift, reg);
118 reg = readl(mpll->base + p->reg_off);
119 n2 = PARM_GET(p->width, p->shift, reg);
121 rate = rate_from_params(parent_rate, sdm, n2);
128 static long mpll_round_rate(struct clk_hw *hw,
130 unsigned long *parent_rate)
132 unsigned long sdm, n2;
134 params_from_rate(rate, *parent_rate, &sdm, &n2);
135 return rate_from_params(*parent_rate, sdm, n2);
138 static int mpll_set_rate(struct clk_hw *hw,
140 unsigned long parent_rate)
142 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
144 unsigned long reg, sdm, n2;
145 unsigned long flags = 0;
147 params_from_rate(rate, parent_rate, &sdm, &n2);
150 spin_lock_irqsave(mpll->lock, flags);
152 __acquire(mpll->lock);
155 reg = readl(mpll->base + p->reg_off);
156 reg = PARM_SET(p->width, p->shift, reg, sdm);
157 writel(reg, mpll->base + p->reg_off);
160 reg = readl(mpll->base + p->reg_off);
161 reg = PARM_SET(p->width, p->shift, reg, 1);
162 writel(reg, mpll->base + p->reg_off);
166 reg = readl(mpll->base + p->reg_off);
167 reg = PARM_SET(p->width, p->shift, reg, 1);
168 writel(reg, mpll->base + p->reg_off);
172 reg = readl(mpll->base + p->reg_off);
173 reg = PARM_SET(p->width, p->shift, reg, n2);
174 writel(reg, mpll->base + p->reg_off);
177 spin_unlock_irqrestore(mpll->lock, flags);
179 __release(mpll->lock);
184 static void mpll_enable_core(struct clk_hw *hw, int enable)
186 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
189 unsigned long flags = 0;
192 spin_lock_irqsave(mpll->lock, flags);
194 __acquire(mpll->lock);
197 reg = readl(mpll->base + p->reg_off);
198 reg = PARM_SET(p->width, p->shift, reg, enable ? 1 : 0);
199 writel(reg, mpll->base + p->reg_off);
202 spin_unlock_irqrestore(mpll->lock, flags);
204 __release(mpll->lock);
208 static int mpll_enable(struct clk_hw *hw)
210 mpll_enable_core(hw, 1);
215 static void mpll_disable(struct clk_hw *hw)
217 mpll_enable_core(hw, 0);
220 static int mpll_is_enabled(struct clk_hw *hw)
222 struct meson_clk_mpll *mpll = to_meson_clk_mpll(hw);
228 reg = readl(mpll->base + p->reg_off);
229 en = PARM_GET(p->width, p->shift, reg);
234 const struct clk_ops meson_clk_mpll_ro_ops = {
235 .recalc_rate = mpll_recalc_rate,
236 .round_rate = mpll_round_rate,
237 .is_enabled = mpll_is_enabled,
240 const struct clk_ops meson_clk_mpll_ops = {
241 .recalc_rate = mpll_recalc_rate,
242 .round_rate = mpll_round_rate,
243 .set_rate = mpll_set_rate,
244 .enable = mpll_enable,
245 .disable = mpll_disable,
246 .is_enabled = mpll_is_enabled,