1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/init.h>
15 #include <linux/of_device.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/platform_device.h>
18 #include <linux/regmap.h>
23 static DEFINE_SPINLOCK(meson_clk_lock);
25 static struct clk_regmap axg_fixed_pll_dco = {
26 .data = &(struct meson_clk_pll_data){
28 .reg_off = HHI_MPLL_CNTL,
33 .reg_off = HHI_MPLL_CNTL,
38 .reg_off = HHI_MPLL_CNTL,
43 .reg_off = HHI_MPLL_CNTL2,
48 .reg_off = HHI_MPLL_CNTL,
53 .reg_off = HHI_MPLL_CNTL,
58 .hw.init = &(struct clk_init_data){
59 .name = "fixed_pll_dco",
60 .ops = &meson_clk_pll_ro_ops,
61 .parent_names = (const char *[]){ "xtal" },
66 static struct clk_regmap axg_fixed_pll = {
67 .data = &(struct clk_regmap_div_data){
68 .offset = HHI_MPLL_CNTL,
71 .flags = CLK_DIVIDER_POWER_OF_TWO,
73 .hw.init = &(struct clk_init_data){
75 .ops = &clk_regmap_divider_ro_ops,
76 .parent_names = (const char *[]){ "fixed_pll_dco" },
79 * This clock won't ever change at runtime so
80 * CLK_SET_RATE_PARENT is not required
85 static struct clk_regmap axg_sys_pll_dco = {
86 .data = &(struct meson_clk_pll_data){
88 .reg_off = HHI_SYS_PLL_CNTL,
93 .reg_off = HHI_SYS_PLL_CNTL,
98 .reg_off = HHI_SYS_PLL_CNTL,
103 .reg_off = HHI_SYS_PLL_CNTL,
108 .reg_off = HHI_SYS_PLL_CNTL,
113 .hw.init = &(struct clk_init_data){
114 .name = "sys_pll_dco",
115 .ops = &meson_clk_pll_ro_ops,
116 .parent_names = (const char *[]){ "xtal" },
121 static struct clk_regmap axg_sys_pll = {
122 .data = &(struct clk_regmap_div_data){
123 .offset = HHI_SYS_PLL_CNTL,
126 .flags = CLK_DIVIDER_POWER_OF_TWO,
128 .hw.init = &(struct clk_init_data){
130 .ops = &clk_regmap_divider_ro_ops,
131 .parent_names = (const char *[]){ "sys_pll_dco" },
133 .flags = CLK_SET_RATE_PARENT,
137 static const struct pll_params_table axg_gp0_pll_params_table[] = {
170 static const struct reg_sequence axg_gp0_init_regs[] = {
171 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
172 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
173 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
174 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
175 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
178 static struct clk_regmap axg_gp0_pll_dco = {
179 .data = &(struct meson_clk_pll_data){
181 .reg_off = HHI_GP0_PLL_CNTL,
186 .reg_off = HHI_GP0_PLL_CNTL,
191 .reg_off = HHI_GP0_PLL_CNTL,
196 .reg_off = HHI_GP0_PLL_CNTL1,
201 .reg_off = HHI_GP0_PLL_CNTL,
206 .reg_off = HHI_GP0_PLL_CNTL,
210 .table = axg_gp0_pll_params_table,
211 .init_regs = axg_gp0_init_regs,
212 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
214 .hw.init = &(struct clk_init_data){
215 .name = "gp0_pll_dco",
216 .ops = &meson_clk_pll_ops,
217 .parent_names = (const char *[]){ "xtal" },
222 static struct clk_regmap axg_gp0_pll = {
223 .data = &(struct clk_regmap_div_data){
224 .offset = HHI_GP0_PLL_CNTL,
227 .flags = CLK_DIVIDER_POWER_OF_TWO,
229 .hw.init = &(struct clk_init_data){
231 .ops = &clk_regmap_divider_ops,
232 .parent_names = (const char *[]){ "gp0_pll_dco" },
234 .flags = CLK_SET_RATE_PARENT,
238 static const struct reg_sequence axg_hifi_init_regs[] = {
239 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
240 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
241 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
242 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
243 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
246 static struct clk_regmap axg_hifi_pll_dco = {
247 .data = &(struct meson_clk_pll_data){
249 .reg_off = HHI_HIFI_PLL_CNTL,
254 .reg_off = HHI_HIFI_PLL_CNTL,
259 .reg_off = HHI_HIFI_PLL_CNTL,
264 .reg_off = HHI_HIFI_PLL_CNTL5,
269 .reg_off = HHI_HIFI_PLL_CNTL,
274 .reg_off = HHI_HIFI_PLL_CNTL,
278 .table = axg_gp0_pll_params_table,
279 .init_regs = axg_hifi_init_regs,
280 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
281 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
283 .hw.init = &(struct clk_init_data){
284 .name = "hifi_pll_dco",
285 .ops = &meson_clk_pll_ops,
286 .parent_names = (const char *[]){ "xtal" },
291 static struct clk_regmap axg_hifi_pll = {
292 .data = &(struct clk_regmap_div_data){
293 .offset = HHI_HIFI_PLL_CNTL,
296 .flags = CLK_DIVIDER_POWER_OF_TWO,
298 .hw.init = &(struct clk_init_data){
300 .ops = &clk_regmap_divider_ops,
301 .parent_names = (const char *[]){ "hifi_pll_dco" },
303 .flags = CLK_SET_RATE_PARENT,
307 static struct clk_fixed_factor axg_fclk_div2_div = {
310 .hw.init = &(struct clk_init_data){
311 .name = "fclk_div2_div",
312 .ops = &clk_fixed_factor_ops,
313 .parent_names = (const char *[]){ "fixed_pll" },
318 static struct clk_regmap axg_fclk_div2 = {
319 .data = &(struct clk_regmap_gate_data){
320 .offset = HHI_MPLL_CNTL6,
323 .hw.init = &(struct clk_init_data){
325 .ops = &clk_regmap_gate_ops,
326 .parent_names = (const char *[]){ "fclk_div2_div" },
328 .flags = CLK_IS_CRITICAL,
332 static struct clk_fixed_factor axg_fclk_div3_div = {
335 .hw.init = &(struct clk_init_data){
336 .name = "fclk_div3_div",
337 .ops = &clk_fixed_factor_ops,
338 .parent_names = (const char *[]){ "fixed_pll" },
343 static struct clk_regmap axg_fclk_div3 = {
344 .data = &(struct clk_regmap_gate_data){
345 .offset = HHI_MPLL_CNTL6,
348 .hw.init = &(struct clk_init_data){
350 .ops = &clk_regmap_gate_ops,
351 .parent_names = (const char *[]){ "fclk_div3_div" },
355 * This clock, as fdiv2, is used by the SCPI FW and is required
356 * by the platform to operate correctly.
357 * Until the following condition are met, we need this clock to
358 * be marked as critical:
359 * a) The SCPI generic driver claims and enable all the clocks
361 * b) CCF has a clock hand-off mechanism to make the sure the
362 * clock stays on until the proper driver comes along
364 .flags = CLK_IS_CRITICAL,
368 static struct clk_fixed_factor axg_fclk_div4_div = {
371 .hw.init = &(struct clk_init_data){
372 .name = "fclk_div4_div",
373 .ops = &clk_fixed_factor_ops,
374 .parent_names = (const char *[]){ "fixed_pll" },
379 static struct clk_regmap axg_fclk_div4 = {
380 .data = &(struct clk_regmap_gate_data){
381 .offset = HHI_MPLL_CNTL6,
384 .hw.init = &(struct clk_init_data){
386 .ops = &clk_regmap_gate_ops,
387 .parent_names = (const char *[]){ "fclk_div4_div" },
392 static struct clk_fixed_factor axg_fclk_div5_div = {
395 .hw.init = &(struct clk_init_data){
396 .name = "fclk_div5_div",
397 .ops = &clk_fixed_factor_ops,
398 .parent_names = (const char *[]){ "fixed_pll" },
403 static struct clk_regmap axg_fclk_div5 = {
404 .data = &(struct clk_regmap_gate_data){
405 .offset = HHI_MPLL_CNTL6,
408 .hw.init = &(struct clk_init_data){
410 .ops = &clk_regmap_gate_ops,
411 .parent_names = (const char *[]){ "fclk_div5_div" },
416 static struct clk_fixed_factor axg_fclk_div7_div = {
419 .hw.init = &(struct clk_init_data){
420 .name = "fclk_div7_div",
421 .ops = &clk_fixed_factor_ops,
422 .parent_names = (const char *[]){ "fixed_pll" },
427 static struct clk_regmap axg_fclk_div7 = {
428 .data = &(struct clk_regmap_gate_data){
429 .offset = HHI_MPLL_CNTL6,
432 .hw.init = &(struct clk_init_data){
434 .ops = &clk_regmap_gate_ops,
435 .parent_names = (const char *[]){ "fclk_div7_div" },
440 static struct clk_regmap axg_mpll_prediv = {
441 .data = &(struct clk_regmap_div_data){
442 .offset = HHI_MPLL_CNTL5,
446 .hw.init = &(struct clk_init_data){
447 .name = "mpll_prediv",
448 .ops = &clk_regmap_divider_ro_ops,
449 .parent_names = (const char *[]){ "fixed_pll" },
454 static struct clk_regmap axg_mpll0_div = {
455 .data = &(struct meson_clk_mpll_data){
457 .reg_off = HHI_MPLL_CNTL7,
462 .reg_off = HHI_MPLL_CNTL7,
467 .reg_off = HHI_MPLL_CNTL7,
472 .reg_off = HHI_MPLL_CNTL,
477 .reg_off = HHI_PLL_TOP_MISC,
481 .lock = &meson_clk_lock,
482 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
484 .hw.init = &(struct clk_init_data){
486 .ops = &meson_clk_mpll_ops,
487 .parent_names = (const char *[]){ "mpll_prediv" },
492 static struct clk_regmap axg_mpll0 = {
493 .data = &(struct clk_regmap_gate_data){
494 .offset = HHI_MPLL_CNTL7,
497 .hw.init = &(struct clk_init_data){
499 .ops = &clk_regmap_gate_ops,
500 .parent_names = (const char *[]){ "mpll0_div" },
502 .flags = CLK_SET_RATE_PARENT,
506 static struct clk_regmap axg_mpll1_div = {
507 .data = &(struct meson_clk_mpll_data){
509 .reg_off = HHI_MPLL_CNTL8,
514 .reg_off = HHI_MPLL_CNTL8,
519 .reg_off = HHI_MPLL_CNTL8,
524 .reg_off = HHI_PLL_TOP_MISC,
528 .lock = &meson_clk_lock,
529 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
531 .hw.init = &(struct clk_init_data){
533 .ops = &meson_clk_mpll_ops,
534 .parent_names = (const char *[]){ "mpll_prediv" },
539 static struct clk_regmap axg_mpll1 = {
540 .data = &(struct clk_regmap_gate_data){
541 .offset = HHI_MPLL_CNTL8,
544 .hw.init = &(struct clk_init_data){
546 .ops = &clk_regmap_gate_ops,
547 .parent_names = (const char *[]){ "mpll1_div" },
549 .flags = CLK_SET_RATE_PARENT,
553 static struct clk_regmap axg_mpll2_div = {
554 .data = &(struct meson_clk_mpll_data){
556 .reg_off = HHI_MPLL_CNTL9,
561 .reg_off = HHI_MPLL_CNTL9,
566 .reg_off = HHI_MPLL_CNTL9,
571 .reg_off = HHI_PLL_TOP_MISC,
575 .lock = &meson_clk_lock,
576 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
578 .hw.init = &(struct clk_init_data){
580 .ops = &meson_clk_mpll_ops,
581 .parent_names = (const char *[]){ "mpll_prediv" },
586 static struct clk_regmap axg_mpll2 = {
587 .data = &(struct clk_regmap_gate_data){
588 .offset = HHI_MPLL_CNTL9,
591 .hw.init = &(struct clk_init_data){
593 .ops = &clk_regmap_gate_ops,
594 .parent_names = (const char *[]){ "mpll2_div" },
596 .flags = CLK_SET_RATE_PARENT,
600 static struct clk_regmap axg_mpll3_div = {
601 .data = &(struct meson_clk_mpll_data){
603 .reg_off = HHI_MPLL3_CNTL0,
608 .reg_off = HHI_MPLL3_CNTL0,
613 .reg_off = HHI_MPLL3_CNTL0,
618 .reg_off = HHI_PLL_TOP_MISC,
622 .lock = &meson_clk_lock,
623 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
625 .hw.init = &(struct clk_init_data){
627 .ops = &meson_clk_mpll_ops,
628 .parent_names = (const char *[]){ "mpll_prediv" },
633 static struct clk_regmap axg_mpll3 = {
634 .data = &(struct clk_regmap_gate_data){
635 .offset = HHI_MPLL3_CNTL0,
638 .hw.init = &(struct clk_init_data){
640 .ops = &clk_regmap_gate_ops,
641 .parent_names = (const char *[]){ "mpll3_div" },
643 .flags = CLK_SET_RATE_PARENT,
647 static const struct pll_params_table axg_pcie_pll_params_table[] = {
655 static const struct reg_sequence axg_pcie_init_regs[] = {
656 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
657 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
658 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
659 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
660 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
661 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
662 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
665 static struct clk_regmap axg_pcie_pll_dco = {
666 .data = &(struct meson_clk_pll_data){
668 .reg_off = HHI_PCIE_PLL_CNTL,
673 .reg_off = HHI_PCIE_PLL_CNTL,
678 .reg_off = HHI_PCIE_PLL_CNTL,
683 .reg_off = HHI_PCIE_PLL_CNTL1,
688 .reg_off = HHI_PCIE_PLL_CNTL,
693 .reg_off = HHI_PCIE_PLL_CNTL,
697 .table = axg_pcie_pll_params_table,
698 .init_regs = axg_pcie_init_regs,
699 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
701 .hw.init = &(struct clk_init_data){
702 .name = "pcie_pll_dco",
703 .ops = &meson_clk_pll_ops,
704 .parent_names = (const char *[]){ "xtal" },
709 static struct clk_regmap axg_pcie_pll_od = {
710 .data = &(struct clk_regmap_div_data){
711 .offset = HHI_PCIE_PLL_CNTL,
714 .flags = CLK_DIVIDER_POWER_OF_TWO,
716 .hw.init = &(struct clk_init_data){
717 .name = "pcie_pll_od",
718 .ops = &clk_regmap_divider_ops,
719 .parent_names = (const char *[]){ "pcie_pll_dco" },
721 .flags = CLK_SET_RATE_PARENT,
725 static struct clk_regmap axg_pcie_pll = {
726 .data = &(struct clk_regmap_div_data){
727 .offset = HHI_PCIE_PLL_CNTL6,
730 .flags = CLK_DIVIDER_POWER_OF_TWO,
732 .hw.init = &(struct clk_init_data){
734 .ops = &clk_regmap_divider_ops,
735 .parent_names = (const char *[]){ "pcie_pll_od" },
737 .flags = CLK_SET_RATE_PARENT,
741 static struct clk_regmap axg_pcie_mux = {
742 .data = &(struct clk_regmap_mux_data){
743 .offset = HHI_PCIE_PLL_CNTL6,
746 /* skip the parent mpll3, reserved for debug */
747 .table = (u32[]){ 1 },
749 .hw.init = &(struct clk_init_data){
751 .ops = &clk_regmap_mux_ops,
752 .parent_names = (const char *[]){ "pcie_pll" },
754 .flags = CLK_SET_RATE_PARENT,
758 static struct clk_regmap axg_pcie_ref = {
759 .data = &(struct clk_regmap_mux_data){
760 .offset = HHI_PCIE_PLL_CNTL6,
763 /* skip the parent 0, reserved for debug */
764 .table = (u32[]){ 1 },
766 .hw.init = &(struct clk_init_data){
768 .ops = &clk_regmap_mux_ops,
769 .parent_names = (const char *[]){ "pcie_mux" },
771 .flags = CLK_SET_RATE_PARENT,
775 static struct clk_regmap axg_pcie_cml_en0 = {
776 .data = &(struct clk_regmap_gate_data){
777 .offset = HHI_PCIE_PLL_CNTL6,
780 .hw.init = &(struct clk_init_data) {
781 .name = "pcie_cml_en0",
782 .ops = &clk_regmap_gate_ops,
783 .parent_names = (const char *[]){ "pcie_ref" },
785 .flags = CLK_SET_RATE_PARENT,
790 static struct clk_regmap axg_pcie_cml_en1 = {
791 .data = &(struct clk_regmap_gate_data){
792 .offset = HHI_PCIE_PLL_CNTL6,
795 .hw.init = &(struct clk_init_data) {
796 .name = "pcie_cml_en1",
797 .ops = &clk_regmap_gate_ops,
798 .parent_names = (const char *[]){ "pcie_ref" },
800 .flags = CLK_SET_RATE_PARENT,
804 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
805 static const char * const clk81_parent_names[] = {
806 "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
807 "fclk_div3", "fclk_div5"
810 static struct clk_regmap axg_mpeg_clk_sel = {
811 .data = &(struct clk_regmap_mux_data){
812 .offset = HHI_MPEG_CLK_CNTL,
815 .table = mux_table_clk81,
817 .hw.init = &(struct clk_init_data){
818 .name = "mpeg_clk_sel",
819 .ops = &clk_regmap_mux_ro_ops,
820 .parent_names = clk81_parent_names,
821 .num_parents = ARRAY_SIZE(clk81_parent_names),
825 static struct clk_regmap axg_mpeg_clk_div = {
826 .data = &(struct clk_regmap_div_data){
827 .offset = HHI_MPEG_CLK_CNTL,
831 .hw.init = &(struct clk_init_data){
832 .name = "mpeg_clk_div",
833 .ops = &clk_regmap_divider_ops,
834 .parent_names = (const char *[]){ "mpeg_clk_sel" },
836 .flags = CLK_SET_RATE_PARENT,
840 static struct clk_regmap axg_clk81 = {
841 .data = &(struct clk_regmap_gate_data){
842 .offset = HHI_MPEG_CLK_CNTL,
845 .hw.init = &(struct clk_init_data){
847 .ops = &clk_regmap_gate_ops,
848 .parent_names = (const char *[]){ "mpeg_clk_div" },
850 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
854 static const char * const axg_sd_emmc_clk0_parent_names[] = {
855 "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
858 * Following these parent clocks, we should also have had mpll2, mpll3
859 * and gp0_pll but these clocks are too precious to be used here. All
860 * the necessary rates for MMC and NAND operation can be acheived using
861 * xtal or fclk_div clocks
866 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
867 .data = &(struct clk_regmap_mux_data){
868 .offset = HHI_SD_EMMC_CLK_CNTL,
872 .hw.init = &(struct clk_init_data) {
873 .name = "sd_emmc_b_clk0_sel",
874 .ops = &clk_regmap_mux_ops,
875 .parent_names = axg_sd_emmc_clk0_parent_names,
876 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
877 .flags = CLK_SET_RATE_PARENT,
881 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
882 .data = &(struct clk_regmap_div_data){
883 .offset = HHI_SD_EMMC_CLK_CNTL,
886 .flags = CLK_DIVIDER_ROUND_CLOSEST,
888 .hw.init = &(struct clk_init_data) {
889 .name = "sd_emmc_b_clk0_div",
890 .ops = &clk_regmap_divider_ops,
891 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
893 .flags = CLK_SET_RATE_PARENT,
897 static struct clk_regmap axg_sd_emmc_b_clk0 = {
898 .data = &(struct clk_regmap_gate_data){
899 .offset = HHI_SD_EMMC_CLK_CNTL,
902 .hw.init = &(struct clk_init_data){
903 .name = "sd_emmc_b_clk0",
904 .ops = &clk_regmap_gate_ops,
905 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
907 .flags = CLK_SET_RATE_PARENT,
911 /* EMMC/NAND clock */
912 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
913 .data = &(struct clk_regmap_mux_data){
914 .offset = HHI_NAND_CLK_CNTL,
918 .hw.init = &(struct clk_init_data) {
919 .name = "sd_emmc_c_clk0_sel",
920 .ops = &clk_regmap_mux_ops,
921 .parent_names = axg_sd_emmc_clk0_parent_names,
922 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
923 .flags = CLK_SET_RATE_PARENT,
927 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
928 .data = &(struct clk_regmap_div_data){
929 .offset = HHI_NAND_CLK_CNTL,
932 .flags = CLK_DIVIDER_ROUND_CLOSEST,
934 .hw.init = &(struct clk_init_data) {
935 .name = "sd_emmc_c_clk0_div",
936 .ops = &clk_regmap_divider_ops,
937 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
939 .flags = CLK_SET_RATE_PARENT,
943 static struct clk_regmap axg_sd_emmc_c_clk0 = {
944 .data = &(struct clk_regmap_gate_data){
945 .offset = HHI_NAND_CLK_CNTL,
948 .hw.init = &(struct clk_init_data){
949 .name = "sd_emmc_c_clk0",
950 .ops = &clk_regmap_gate_ops,
951 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
953 .flags = CLK_SET_RATE_PARENT,
957 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
958 9, 10, 11, 13, 14, };
959 static const char * const gen_clk_parent_names[] = {
960 "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
961 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
964 static struct clk_regmap axg_gen_clk_sel = {
965 .data = &(struct clk_regmap_mux_data){
966 .offset = HHI_GEN_CLK_CNTL,
969 .table = mux_table_gen_clk,
971 .hw.init = &(struct clk_init_data){
972 .name = "gen_clk_sel",
973 .ops = &clk_regmap_mux_ops,
975 * bits 15:12 selects from 14 possible parents:
976 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
977 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
978 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
980 .parent_names = gen_clk_parent_names,
981 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
985 static struct clk_regmap axg_gen_clk_div = {
986 .data = &(struct clk_regmap_div_data){
987 .offset = HHI_GEN_CLK_CNTL,
991 .hw.init = &(struct clk_init_data){
992 .name = "gen_clk_div",
993 .ops = &clk_regmap_divider_ops,
994 .parent_names = (const char *[]){ "gen_clk_sel" },
996 .flags = CLK_SET_RATE_PARENT,
1000 static struct clk_regmap axg_gen_clk = {
1001 .data = &(struct clk_regmap_gate_data){
1002 .offset = HHI_GEN_CLK_CNTL,
1005 .hw.init = &(struct clk_init_data){
1007 .ops = &clk_regmap_gate_ops,
1008 .parent_names = (const char *[]){ "gen_clk_div" },
1010 .flags = CLK_SET_RATE_PARENT,
1014 /* Everything Else (EE) domain gates */
1015 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1016 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1017 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1018 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1019 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1020 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1021 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1022 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1023 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1024 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1025 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1026 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1027 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1028 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1029 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1030 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1031 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1032 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1033 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1034 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1036 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1037 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1038 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1039 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1040 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1041 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1042 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1043 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1044 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1045 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1046 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1048 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1049 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1050 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1051 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1052 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1053 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1054 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1055 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1056 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1058 /* Always On (AO) domain gates */
1060 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1061 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1062 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1063 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1064 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1066 /* Array of all clocks provided by this provider */
1068 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1070 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1071 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1072 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1073 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1074 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1075 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1076 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1077 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1078 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1079 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1080 [CLKID_CLK81] = &axg_clk81.hw,
1081 [CLKID_MPLL0] = &axg_mpll0.hw,
1082 [CLKID_MPLL1] = &axg_mpll1.hw,
1083 [CLKID_MPLL2] = &axg_mpll2.hw,
1084 [CLKID_MPLL3] = &axg_mpll3.hw,
1085 [CLKID_DDR] = &axg_ddr.hw,
1086 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1087 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1088 [CLKID_ISA] = &axg_isa.hw,
1089 [CLKID_PL301] = &axg_pl301.hw,
1090 [CLKID_PERIPHS] = &axg_periphs.hw,
1091 [CLKID_SPICC0] = &axg_spicc_0.hw,
1092 [CLKID_I2C] = &axg_i2c.hw,
1093 [CLKID_RNG0] = &axg_rng0.hw,
1094 [CLKID_UART0] = &axg_uart0.hw,
1095 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1096 [CLKID_SPICC1] = &axg_spicc_1.hw,
1097 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1098 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1099 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1100 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1101 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1102 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1103 [CLKID_DMA] = &axg_dma.hw,
1104 [CLKID_SPI] = &axg_spi.hw,
1105 [CLKID_AUDIO] = &axg_audio.hw,
1106 [CLKID_ETH] = &axg_eth_core.hw,
1107 [CLKID_UART1] = &axg_uart1.hw,
1108 [CLKID_G2D] = &axg_g2d.hw,
1109 [CLKID_USB0] = &axg_usb0.hw,
1110 [CLKID_USB1] = &axg_usb1.hw,
1111 [CLKID_RESET] = &axg_reset.hw,
1112 [CLKID_USB] = &axg_usb_general.hw,
1113 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1114 [CLKID_EFUSE] = &axg_efuse.hw,
1115 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1116 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1117 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1118 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1119 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1120 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1121 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1122 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1123 [CLKID_GIC] = &axg_gic.hw,
1124 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1125 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1126 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1127 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1128 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1129 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1130 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1131 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1132 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1133 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1134 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1135 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1136 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1137 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1138 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1139 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1140 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1141 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1142 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1143 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1144 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1145 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1146 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1147 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1148 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1149 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1150 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1151 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
1152 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1153 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1154 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1155 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1156 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1157 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1158 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1159 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1160 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1166 /* Convenience table to populate regmap in .probe */
1167 static struct clk_regmap *const axg_clk_regmaps[] = {
1206 &axg_sec_ahb_ahb3_bridge,
1213 &axg_sd_emmc_b_clk0,
1214 &axg_sd_emmc_c_clk0,
1216 &axg_sd_emmc_b_clk0_div,
1217 &axg_sd_emmc_c_clk0_div,
1219 &axg_sd_emmc_b_clk0_sel,
1220 &axg_sd_emmc_c_clk0_sel,
1258 static const struct of_device_id clkc_match_table[] = {
1259 { .compatible = "amlogic,axg-clkc" },
1263 static int axg_clkc_probe(struct platform_device *pdev)
1265 struct device *dev = &pdev->dev;
1269 /* Get the hhi system controller node if available */
1270 map = syscon_node_to_regmap(of_get_parent(dev->of_node));
1272 dev_err(dev, "failed to get HHI regmap\n");
1273 return PTR_ERR(map);
1276 /* Populate regmap for the regmap backed clocks */
1277 for (i = 0; i < ARRAY_SIZE(axg_clk_regmaps); i++)
1278 axg_clk_regmaps[i]->map = map;
1280 for (i = 0; i < axg_hw_onecell_data.num; i++) {
1281 /* array might be sparse */
1282 if (!axg_hw_onecell_data.hws[i])
1285 ret = devm_clk_hw_register(dev, axg_hw_onecell_data.hws[i]);
1287 dev_err(dev, "Clock registration failed\n");
1292 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1293 &axg_hw_onecell_data);
1296 static struct platform_driver axg_driver = {
1297 .probe = axg_clkc_probe,
1300 .of_match_table = clkc_match_table,
1304 builtin_platform_driver(axg_driver);