drivers/clk/meson/axg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AmLogic Meson-AXG Clock Controller Driver
   4  *
   5  * Copyright (c) 2016 Baylibre SAS.
   6  * Author: Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * Copyright (c) 2017 Amlogic, inc.
   9  * Author: Qiufang Dai <qiufang.dai@amlogic.com>
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/of_address.h>
  15 #include <linux/of_device.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/init.h>
  18
  19 #include "clkc.h"
  20 #include "axg.h"
  21
  22 static DEFINE_SPINLOCK(meson_clk_lock);
  23
  24 static struct meson_clk_pll axg_fixed_pll = {
  25         .m = {
  26                 .reg_off = HHI_MPLL_CNTL,
  27                 .shift   = 0,
  28                 .width   = 9,
  29         },
  30         .n = {
  31                 .reg_off = HHI_MPLL_CNTL,
  32                 .shift   = 9,
  33                 .width   = 5,
  34         },
  35         .od = {
  36                 .reg_off = HHI_MPLL_CNTL,
  37                 .shift   = 16,
  38                 .width   = 2,
  39         },
  40         .frac = {
  41                 .reg_off = HHI_MPLL_CNTL2,
  42                 .shift   = 0,
  43                 .width   = 12,
  44         },
  45         .lock = &meson_clk_lock,
  46         .hw.init = &(struct clk_init_data){
  47                 .name = "fixed_pll",
  48                 .ops = &meson_clk_pll_ro_ops,
  49                 .parent_names = (const char *[]){ "xtal" },
  50                 .num_parents = 1,
  51         },
  52 };
  53
  54 static struct meson_clk_pll axg_sys_pll = {
  55         .m = {
  56                 .reg_off = HHI_SYS_PLL_CNTL,
  57                 .shift   = 0,
  58                 .width   = 9,
  59         },
  60         .n = {
  61                 .reg_off = HHI_SYS_PLL_CNTL,
  62                 .shift   = 9,
  63                 .width   = 5,
  64         },
  65         .od = {
  66                 .reg_off = HHI_SYS_PLL_CNTL,
  67                 .shift   = 16,
  68                 .width   = 2,
  69         },
  70         .lock = &meson_clk_lock,
  71         .hw.init = &(struct clk_init_data){
  72                 .name = "sys_pll",
  73                 .ops = &meson_clk_pll_ro_ops,
  74                 .parent_names = (const char *[]){ "xtal" },
  75                 .num_parents = 1,
  76                 .flags = CLK_GET_RATE_NOCACHE,
  77         },
  78 };
  79
  80 static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
  81         PLL_RATE(240000000, 40, 1, 2),
  82         PLL_RATE(246000000, 41, 1, 2),
  83         PLL_RATE(252000000, 42, 1, 2),
  84         PLL_RATE(258000000, 43, 1, 2),
  85         PLL_RATE(264000000, 44, 1, 2),
  86         PLL_RATE(270000000, 45, 1, 2),
  87         PLL_RATE(276000000, 46, 1, 2),
  88         PLL_RATE(282000000, 47, 1, 2),
  89         PLL_RATE(288000000, 48, 1, 2),
  90         PLL_RATE(294000000, 49, 1, 2),
  91         PLL_RATE(300000000, 50, 1, 2),
  92         PLL_RATE(306000000, 51, 1, 2),
  93         PLL_RATE(312000000, 52, 1, 2),
  94         PLL_RATE(318000000, 53, 1, 2),
  95         PLL_RATE(324000000, 54, 1, 2),
  96         PLL_RATE(330000000, 55, 1, 2),
  97         PLL_RATE(336000000, 56, 1, 2),
  98         PLL_RATE(342000000, 57, 1, 2),
  99         PLL_RATE(348000000, 58, 1, 2),
 100         PLL_RATE(354000000, 59, 1, 2),
 101         PLL_RATE(360000000, 60, 1, 2),
 102         PLL_RATE(366000000, 61, 1, 2),
 103         PLL_RATE(372000000, 62, 1, 2),
 104         PLL_RATE(378000000, 63, 1, 2),
 105         PLL_RATE(384000000, 64, 1, 2),
 106         PLL_RATE(390000000, 65, 1, 3),
 107         PLL_RATE(396000000, 66, 1, 3),
 108         PLL_RATE(402000000, 67, 1, 3),
 109         PLL_RATE(408000000, 68, 1, 3),
 110         PLL_RATE(480000000, 40, 1, 1),
 111         PLL_RATE(492000000, 41, 1, 1),
 112         PLL_RATE(504000000, 42, 1, 1),
 113         PLL_RATE(516000000, 43, 1, 1),
 114         PLL_RATE(528000000, 44, 1, 1),
 115         PLL_RATE(540000000, 45, 1, 1),
 116         PLL_RATE(552000000, 46, 1, 1),
 117         PLL_RATE(564000000, 47, 1, 1),
 118         PLL_RATE(576000000, 48, 1, 1),
 119         PLL_RATE(588000000, 49, 1, 1),
 120         PLL_RATE(600000000, 50, 1, 1),
 121         PLL_RATE(612000000, 51, 1, 1),
 122         PLL_RATE(624000000, 52, 1, 1),
 123         PLL_RATE(636000000, 53, 1, 1),
 124         PLL_RATE(648000000, 54, 1, 1),
 125         PLL_RATE(660000000, 55, 1, 1),
 126         PLL_RATE(672000000, 56, 1, 1),
 127         PLL_RATE(684000000, 57, 1, 1),
 128         PLL_RATE(696000000, 58, 1, 1),
 129         PLL_RATE(708000000, 59, 1, 1),
 130         PLL_RATE(720000000, 60, 1, 1),
 131         PLL_RATE(732000000, 61, 1, 1),
 132         PLL_RATE(744000000, 62, 1, 1),
 133         PLL_RATE(756000000, 63, 1, 1),
 134         PLL_RATE(768000000, 64, 1, 1),
 135         PLL_RATE(780000000, 65, 1, 1),
 136         PLL_RATE(792000000, 66, 1, 1),
 137         PLL_RATE(804000000, 67, 1, 1),
 138         PLL_RATE(816000000, 68, 1, 1),
 139         PLL_RATE(960000000, 40, 1, 0),
 140         PLL_RATE(984000000, 41, 1, 0),
 141         PLL_RATE(1008000000, 42, 1, 0),
 142         PLL_RATE(1032000000, 43, 1, 0),
 143         PLL_RATE(1056000000, 44, 1, 0),
 144         PLL_RATE(1080000000, 45, 1, 0),
 145         PLL_RATE(1104000000, 46, 1, 0),
 146         PLL_RATE(1128000000, 47, 1, 0),
 147         PLL_RATE(1152000000, 48, 1, 0),
 148         PLL_RATE(1176000000, 49, 1, 0),
 149         PLL_RATE(1200000000, 50, 1, 0),
 150         PLL_RATE(1224000000, 51, 1, 0),
 151         PLL_RATE(1248000000, 52, 1, 0),
 152         PLL_RATE(1272000000, 53, 1, 0),
 153         PLL_RATE(1296000000, 54, 1, 0),
 154         PLL_RATE(1320000000, 55, 1, 0),
 155         PLL_RATE(1344000000, 56, 1, 0),
 156         PLL_RATE(1368000000, 57, 1, 0),
 157         PLL_RATE(1392000000, 58, 1, 0),
 158         PLL_RATE(1416000000, 59, 1, 0),
 159         PLL_RATE(1440000000, 60, 1, 0),
 160         PLL_RATE(1464000000, 61, 1, 0),
 161         PLL_RATE(1488000000, 62, 1, 0),
 162         PLL_RATE(1512000000, 63, 1, 0),
 163         PLL_RATE(1536000000, 64, 1, 0),
 164         PLL_RATE(1560000000, 65, 1, 0),
 165         PLL_RATE(1584000000, 66, 1, 0),
 166         PLL_RATE(1608000000, 67, 1, 0),
 167         PLL_RATE(1632000000, 68, 1, 0),
 168         { /* sentinel */ },
 169 };
 170
 171 static struct pll_params_table axg_gp0_params_table[] = {
 172         PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
 173         PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
 174         PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
 175         PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
 176         PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
 177         PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
 178 };
 179
 180 static struct meson_clk_pll axg_gp0_pll = {
 181         .m = {
 182                 .reg_off = HHI_GP0_PLL_CNTL,
 183                 .shift   = 0,
 184                 .width   = 9,
 185         },
 186         .n = {
 187                 .reg_off = HHI_GP0_PLL_CNTL,
 188                 .shift   = 9,
 189                 .width   = 5,
 190         },
 191         .od = {
 192                 .reg_off = HHI_GP0_PLL_CNTL,
 193                 .shift   = 16,
 194                 .width   = 2,
 195         },
 196         .params = {
 197                 .params_table = axg_gp0_params_table,
 198                 .params_count = ARRAY_SIZE(axg_gp0_params_table),
 199                 .no_init_reset = true,
 200                 .reset_lock_loop = true,
 201         },
 202         .rate_table = axg_gp0_pll_rate_table,
 203         .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
 204         .lock = &meson_clk_lock,
 205         .hw.init = &(struct clk_init_data){
 206                 .name = "gp0_pll",
 207                 .ops = &meson_clk_pll_ops,
 208                 .parent_names = (const char *[]){ "xtal" },
 209                 .num_parents = 1,
 210         },
 211 };
 212
 213
 214 static struct clk_fixed_factor axg_fclk_div2 = {
 215         .mult = 1,
 216         .div = 2,
 217         .hw.init = &(struct clk_init_data){
 218                 .name = "fclk_div2",
 219                 .ops = &clk_fixed_factor_ops,
 220                 .parent_names = (const char *[]){ "fixed_pll" },
 221                 .num_parents = 1,
 222         },
 223 };
 224
 225 static struct clk_fixed_factor axg_fclk_div3 = {
 226         .mult = 1,
 227         .div = 3,
 228         .hw.init = &(struct clk_init_data){
 229                 .name = "fclk_div3",
 230                 .ops = &clk_fixed_factor_ops,
 231                 .parent_names = (const char *[]){ "fixed_pll" },
 232                 .num_parents = 1,
 233         },
 234 };
 235
 236 static struct clk_fixed_factor axg_fclk_div4 = {
 237         .mult = 1,
 238         .div = 4,
 239         .hw.init = &(struct clk_init_data){
 240                 .name = "fclk_div4",
 241                 .ops = &clk_fixed_factor_ops,
 242                 .parent_names = (const char *[]){ "fixed_pll" },
 243                 .num_parents = 1,
 244         },
 245 };
 246
 247 static struct clk_fixed_factor axg_fclk_div5 = {
 248         .mult = 1,
 249         .div = 5,
 250         .hw.init = &(struct clk_init_data){
 251                 .name = "fclk_div5",
 252                 .ops = &clk_fixed_factor_ops,
 253                 .parent_names = (const char *[]){ "fixed_pll" },
 254                 .num_parents = 1,
 255         },
 256 };
 257
 258 static struct clk_fixed_factor axg_fclk_div7 = {
 259         .mult = 1,
 260         .div = 7,
 261         .hw.init = &(struct clk_init_data){
 262                 .name = "fclk_div7",
 263                 .ops = &clk_fixed_factor_ops,
 264                 .parent_names = (const char *[]){ "fixed_pll" },
 265                 .num_parents = 1,
 266         },
 267 };
 268
 269 static struct meson_clk_mpll axg_mpll0 = {
 270         .sdm = {
 271                 .reg_off = HHI_MPLL_CNTL7,
 272                 .shift   = 0,
 273                 .width   = 14,
 274         },
 275         .sdm_en = {
 276                 .reg_off = HHI_MPLL_CNTL7,
 277                 .shift   = 15,
 278                 .width   = 1,
 279         },
 280         .n2 = {
 281                 .reg_off = HHI_MPLL_CNTL7,
 282                 .shift   = 16,
 283                 .width   = 9,
 284         },
 285         .en = {
 286                 .reg_off = HHI_MPLL_CNTL7,
 287                 .shift   = 14,
 288                 .width   = 1,
 289         },
 290         .ssen = {
 291                 .reg_off = HHI_MPLL_CNTL,
 292                 .shift   = 25,
 293                 .width   = 1,
 294         },
 295         .misc = {
 296                 .reg_off = HHI_PLL_TOP_MISC,
 297                 .shift   = 0,
 298                 .width   = 1,
 299         },
 300         .lock = &meson_clk_lock,
 301         .hw.init = &(struct clk_init_data){
 302                 .name = "mpll0",
 303                 .ops = &meson_clk_mpll_ops,
 304                 .parent_names = (const char *[]){ "fixed_pll" },
 305                 .num_parents = 1,
 306         },
 307 };
 308
 309 static struct meson_clk_mpll axg_mpll1 = {
 310         .sdm = {
 311                 .reg_off = HHI_MPLL_CNTL8,
 312                 .shift   = 0,
 313                 .width   = 14,
 314         },
 315         .sdm_en = {
 316                 .reg_off = HHI_MPLL_CNTL8,
 317                 .shift   = 15,
 318                 .width   = 1,
 319         },
 320         .n2 = {
 321                 .reg_off = HHI_MPLL_CNTL8,
 322                 .shift   = 16,
 323                 .width   = 9,
 324         },
 325         .en = {
 326                 .reg_off = HHI_MPLL_CNTL8,
 327                 .shift   = 14,
 328                 .width   = 1,
 329         },
 330         .misc = {
 331                 .reg_off = HHI_PLL_TOP_MISC,
 332                 .shift   = 1,
 333                 .width   = 1,
 334         },
 335         .lock = &meson_clk_lock,
 336         .hw.init = &(struct clk_init_data){
 337                 .name = "mpll1",
 338                 .ops = &meson_clk_mpll_ops,
 339                 .parent_names = (const char *[]){ "fixed_pll" },
 340                 .num_parents = 1,
 341         },
 342 };
 343
 344 static struct meson_clk_mpll axg_mpll2 = {
 345         .sdm = {
 346                 .reg_off = HHI_MPLL_CNTL9,
 347                 .shift   = 0,
 348                 .width   = 14,
 349         },
 350         .sdm_en = {
 351                 .reg_off = HHI_MPLL_CNTL9,
 352                 .shift   = 15,
 353                 .width   = 1,
 354         },
 355         .n2 = {
 356                 .reg_off = HHI_MPLL_CNTL9,
 357                 .shift   = 16,
 358                 .width   = 9,
 359         },
 360         .en = {
 361                 .reg_off = HHI_MPLL_CNTL9,
 362                 .shift   = 14,
 363                 .width   = 1,
 364         },
 365         .misc = {
 366                 .reg_off = HHI_PLL_TOP_MISC,
 367                 .shift   = 2,
 368                 .width   = 1,
 369         },
 370         .lock = &meson_clk_lock,
 371         .hw.init = &(struct clk_init_data){
 372                 .name = "mpll2",
 373                 .ops = &meson_clk_mpll_ops,
 374                 .parent_names = (const char *[]){ "fixed_pll" },
 375                 .num_parents = 1,
 376         },
 377 };
 378
 379 static struct meson_clk_mpll axg_mpll3 = {
 380         .sdm = {
 381                 .reg_off = HHI_MPLL3_CNTL0,
 382                 .shift   = 12,
 383                 .width   = 14,
 384         },
 385         .sdm_en = {
 386                 .reg_off = HHI_MPLL3_CNTL0,
 387                 .shift   = 11,
 388                 .width   = 1,
 389         },
 390         .n2 = {
 391                 .reg_off = HHI_MPLL3_CNTL0,
 392                 .shift   = 2,
 393                 .width   = 9,
 394         },
 395         .en = {
 396                 .reg_off = HHI_MPLL3_CNTL0,
 397                 .shift   = 0,
 398                 .width   = 1,
 399         },
 400         .misc = {
 401                 .reg_off = HHI_PLL_TOP_MISC,
 402                 .shift   = 3,
 403                 .width   = 1,
 404         },
 405         .lock = &meson_clk_lock,
 406         .hw.init = &(struct clk_init_data){
 407                 .name = "mpll3",
 408                 .ops = &meson_clk_mpll_ops,
 409                 .parent_names = (const char *[]){ "fixed_pll" },
 410                 .num_parents = 1,
 411         },
 412 };
 413
 414 static u32 mux_table_clk81[]    = { 0, 2, 3, 4, 5, 6, 7 };
 415 static const char * const clk81_parent_names[] = {
 416         "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
 417         "fclk_div3", "fclk_div5"
 418 };
 419
 420 static struct clk_mux axg_mpeg_clk_sel = {
 421         .reg = (void *)HHI_MPEG_CLK_CNTL,
 422         .mask = 0x7,
 423         .shift = 12,
 424         .flags = CLK_MUX_READ_ONLY,
 425         .table = mux_table_clk81,
 426         .lock = &meson_clk_lock,
 427         .hw.init = &(struct clk_init_data){
 428                 .name = "mpeg_clk_sel",
 429                 .ops = &clk_mux_ro_ops,
 430                 .parent_names = clk81_parent_names,
 431                 .num_parents = ARRAY_SIZE(clk81_parent_names),
 432         },
 433 };
 434
 435 static struct clk_divider axg_mpeg_clk_div = {
 436         .reg = (void *)HHI_MPEG_CLK_CNTL,
 437         .shift = 0,
 438         .width = 7,
 439         .lock = &meson_clk_lock,
 440         .hw.init = &(struct clk_init_data){
 441                 .name = "mpeg_clk_div",
 442                 .ops = &clk_divider_ops,
 443                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 444                 .num_parents = 1,
 445                 .flags = CLK_SET_RATE_PARENT,
 446         },
 447 };
 448
 449 static struct clk_gate axg_clk81 = {
 450         .reg = (void *)HHI_MPEG_CLK_CNTL,
 451         .bit_idx = 7,
 452         .lock = &meson_clk_lock,
 453         .hw.init = &(struct clk_init_data){
 454                 .name = "clk81",
 455                 .ops = &clk_gate_ops,
 456                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 457                 .num_parents = 1,
 458                 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
 459         },
 460 };
 461
 462 static const char * const axg_sd_emmc_clk0_parent_names[] = {
 463         "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
 464
 465         /*
 466          * Following these parent clocks, we should also have had mpll2, mpll3
 467          * and gp0_pll but these clocks are too precious to be used here. All
 468          * the necessary rates for MMC and NAND operation can be acheived using
 469          * xtal or fclk_div clocks
 470          */
 471 };
 472
 473 /* SDcard clock */
 474 static struct clk_mux axg_sd_emmc_b_clk0_sel = {
 475         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
 476         .mask = 0x7,
 477         .shift = 25,
 478         .lock = &meson_clk_lock,
 479         .hw.init = &(struct clk_init_data) {
 480                 .name = "sd_emmc_b_clk0_sel",
 481                 .ops = &clk_mux_ops,
 482                 .parent_names = axg_sd_emmc_clk0_parent_names,
 483                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 484                 .flags = CLK_SET_RATE_PARENT,
 485         },
 486 };
 487
 488 static struct clk_divider axg_sd_emmc_b_clk0_div = {
 489         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
 490         .shift = 16,
 491         .width = 7,
 492         .lock = &meson_clk_lock,
 493         .flags = CLK_DIVIDER_ROUND_CLOSEST,
 494         .hw.init = &(struct clk_init_data) {
 495                 .name = "sd_emmc_b_clk0_div",
 496                 .ops = &clk_divider_ops,
 497                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
 498                 .num_parents = 1,
 499                 .flags = CLK_SET_RATE_PARENT,
 500         },
 501 };
 502
 503 static struct clk_gate axg_sd_emmc_b_clk0 = {
 504         .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
 505         .bit_idx = 23,
 506         .lock = &meson_clk_lock,
 507         .hw.init = &(struct clk_init_data){
 508                 .name = "sd_emmc_b_clk0",
 509                 .ops = &clk_gate_ops,
 510                 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
 511                 .num_parents = 1,
 512                 .flags = CLK_SET_RATE_PARENT,
 513         },
 514 };
 515
 516 /* EMMC/NAND clock */
 517 static struct clk_mux axg_sd_emmc_c_clk0_sel = {
 518         .reg = (void *)HHI_NAND_CLK_CNTL,
 519         .mask = 0x7,
 520         .shift = 9,
 521         .lock = &meson_clk_lock,
 522         .hw.init = &(struct clk_init_data) {
 523                 .name = "sd_emmc_c_clk0_sel",
 524                 .ops = &clk_mux_ops,
 525                 .parent_names = axg_sd_emmc_clk0_parent_names,
 526                 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
 527                 .flags = CLK_SET_RATE_PARENT,
 528         },
 529 };
 530
 531 static struct clk_divider axg_sd_emmc_c_clk0_div = {
 532         .reg = (void *)HHI_NAND_CLK_CNTL,
 533         .shift = 0,
 534         .width = 7,
 535         .lock = &meson_clk_lock,
 536         .flags = CLK_DIVIDER_ROUND_CLOSEST,
 537         .hw.init = &(struct clk_init_data) {
 538                 .name = "sd_emmc_c_clk0_div",
 539                 .ops = &clk_divider_ops,
 540                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
 541                 .num_parents = 1,
 542                 .flags = CLK_SET_RATE_PARENT,
 543         },
 544 };
 545
 546 static struct clk_gate axg_sd_emmc_c_clk0 = {
 547         .reg = (void *)HHI_NAND_CLK_CNTL,
 548         .bit_idx = 7,
 549         .lock = &meson_clk_lock,
 550         .hw.init = &(struct clk_init_data){
 551                 .name = "sd_emmc_c_clk0",
 552                 .ops = &clk_gate_ops,
 553                 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
 554                 .num_parents = 1,
 555                 .flags = CLK_SET_RATE_PARENT,
 556         },
 557 };
 558
 559 /* Everything Else (EE) domain gates */
 560 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
 561 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
 562 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
 563 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
 564 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
 565 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
 566 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
 567 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
 568 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
 569 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
 570 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
 571 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
 572 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
 573 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
 574 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
 575 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
 576 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
 577 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
 578 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
 579 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
 580
 581 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
 582 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
 583 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
 584 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
 585 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
 586 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
 587 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
 588 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
 589 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
 590 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
 591 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
 592
 593 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
 594 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
 595 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
 596 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
 597 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
 598 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
 599 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
 600 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
 601
 602 /* Always On (AO) domain gates */
 603
 604 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
 605 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
 606 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
 607 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
 608 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
 609
 610 /* Array of all clocks provided by this provider */
 611
 612 static struct clk_hw_onecell_data axg_hw_onecell_data = {
 613         .hws = {
 614                 [CLKID_SYS_PLL]                 = &axg_sys_pll.hw,
 615                 [CLKID_FIXED_PLL]               = &axg_fixed_pll.hw,
 616                 [CLKID_FCLK_DIV2]               = &axg_fclk_div2.hw,
 617                 [CLKID_FCLK_DIV3]               = &axg_fclk_div3.hw,
 618                 [CLKID_FCLK_DIV4]               = &axg_fclk_div4.hw,
 619                 [CLKID_FCLK_DIV5]               = &axg_fclk_div5.hw,
 620                 [CLKID_FCLK_DIV7]               = &axg_fclk_div7.hw,
 621                 [CLKID_GP0_PLL]                 = &axg_gp0_pll.hw,
 622                 [CLKID_MPEG_SEL]                = &axg_mpeg_clk_sel.hw,
 623                 [CLKID_MPEG_DIV]                = &axg_mpeg_clk_div.hw,
 624                 [CLKID_CLK81]                   = &axg_clk81.hw,
 625                 [CLKID_MPLL0]                   = &axg_mpll0.hw,
 626                 [CLKID_MPLL1]                   = &axg_mpll1.hw,
 627                 [CLKID_MPLL2]                   = &axg_mpll2.hw,
 628                 [CLKID_MPLL3]                   = &axg_mpll3.hw,
 629                 [CLKID_DDR]                     = &axg_ddr.hw,
 630                 [CLKID_AUDIO_LOCKER]            = &axg_audio_locker.hw,
 631                 [CLKID_MIPI_DSI_HOST]           = &axg_mipi_dsi_host.hw,
 632                 [CLKID_ISA]                     = &axg_isa.hw,
 633                 [CLKID_PL301]                   = &axg_pl301.hw,
 634                 [CLKID_PERIPHS]                 = &axg_periphs.hw,
 635                 [CLKID_SPICC0]                  = &axg_spicc_0.hw,
 636                 [CLKID_I2C]                     = &axg_i2c.hw,
 637                 [CLKID_RNG0]                    = &axg_rng0.hw,
 638                 [CLKID_UART0]                   = &axg_uart0.hw,
 639                 [CLKID_MIPI_DSI_PHY]            = &axg_mipi_dsi_phy.hw,
 640                 [CLKID_SPICC1]                  = &axg_spicc_1.hw,
 641                 [CLKID_PCIE_A]                  = &axg_pcie_a.hw,
 642                 [CLKID_PCIE_B]                  = &axg_pcie_b.hw,
 643                 [CLKID_HIU_IFACE]               = &axg_hiu_reg.hw,
 644                 [CLKID_ASSIST_MISC]             = &axg_assist_misc.hw,
 645                 [CLKID_SD_EMMC_B]               = &axg_emmc_b.hw,
 646                 [CLKID_SD_EMMC_C]               = &axg_emmc_c.hw,
 647                 [CLKID_DMA]                     = &axg_dma.hw,
 648                 [CLKID_SPI]                     = &axg_spi.hw,
 649                 [CLKID_AUDIO]                   = &axg_audio.hw,
 650                 [CLKID_ETH]                     = &axg_eth_core.hw,
 651                 [CLKID_UART1]                   = &axg_uart1.hw,
 652                 [CLKID_G2D]                     = &axg_g2d.hw,
 653                 [CLKID_USB0]                    = &axg_usb0.hw,
 654                 [CLKID_USB1]                    = &axg_usb1.hw,
 655                 [CLKID_RESET]                   = &axg_reset.hw,
 656                 [CLKID_USB]                     = &axg_usb_general.hw,
 657                 [CLKID_AHB_ARB0]                = &axg_ahb_arb0.hw,
 658                 [CLKID_EFUSE]                   = &axg_efuse.hw,
 659                 [CLKID_BOOT_ROM]                = &axg_boot_rom.hw,
 660                 [CLKID_AHB_DATA_BUS]            = &axg_ahb_data_bus.hw,
 661                 [CLKID_AHB_CTRL_BUS]            = &axg_ahb_ctrl_bus.hw,
 662                 [CLKID_USB1_DDR_BRIDGE]         = &axg_usb1_to_ddr.hw,
 663                 [CLKID_USB0_DDR_BRIDGE]         = &axg_usb0_to_ddr.hw,
 664                 [CLKID_MMC_PCLK]                = &axg_mmc_pclk.hw,
 665                 [CLKID_VPU_INTR]                = &axg_vpu_intr.hw,
 666                 [CLKID_SEC_AHB_AHB3_BRIDGE]     = &axg_sec_ahb_ahb3_bridge.hw,
 667                 [CLKID_GIC]                     = &axg_gic.hw,
 668                 [CLKID_AO_MEDIA_CPU]            = &axg_ao_media_cpu.hw,
 669                 [CLKID_AO_AHB_SRAM]             = &axg_ao_ahb_sram.hw,
 670                 [CLKID_AO_AHB_BUS]              = &axg_ao_ahb_bus.hw,
 671                 [CLKID_AO_IFACE]                = &axg_ao_iface.hw,
 672                 [CLKID_AO_I2C]                  = &axg_ao_i2c.hw,
 673                 [CLKID_SD_EMMC_B_CLK0_SEL]      = &axg_sd_emmc_b_clk0_sel.hw,
 674                 [CLKID_SD_EMMC_B_CLK0_DIV]      = &axg_sd_emmc_b_clk0_div.hw,
 675                 [CLKID_SD_EMMC_B_CLK0]          = &axg_sd_emmc_b_clk0.hw,
 676                 [CLKID_SD_EMMC_C_CLK0_SEL]      = &axg_sd_emmc_c_clk0_sel.hw,
 677                 [CLKID_SD_EMMC_C_CLK0_DIV]      = &axg_sd_emmc_c_clk0_div.hw,
 678                 [CLKID_SD_EMMC_C_CLK0]          = &axg_sd_emmc_c_clk0.hw,
 679                 [NR_CLKS]                       = NULL,
 680         },
 681         .num = NR_CLKS,
 682 };
 683
 684 /* Convenience tables to populate base addresses in .probe */
 685
 686 static struct meson_clk_pll *const axg_clk_plls[] = {
 687         &axg_fixed_pll,
 688         &axg_sys_pll,
 689         &axg_gp0_pll,
 690 };
 691
 692 static struct meson_clk_mpll *const axg_clk_mplls[] = {
 693         &axg_mpll0,
 694         &axg_mpll1,
 695         &axg_mpll2,
 696         &axg_mpll3,
 697 };
 698
 699 static struct clk_gate *const axg_clk_gates[] = {
 700         &axg_clk81,
 701         &axg_ddr,
 702         &axg_audio_locker,
 703         &axg_mipi_dsi_host,
 704         &axg_isa,
 705         &axg_pl301,
 706         &axg_periphs,
 707         &axg_spicc_0,
 708         &axg_i2c,
 709         &axg_rng0,
 710         &axg_uart0,
 711         &axg_mipi_dsi_phy,
 712         &axg_spicc_1,
 713         &axg_pcie_a,
 714         &axg_pcie_b,
 715         &axg_hiu_reg,
 716         &axg_assist_misc,
 717         &axg_emmc_b,
 718         &axg_emmc_c,
 719         &axg_dma,
 720         &axg_spi,
 721         &axg_audio,
 722         &axg_eth_core,
 723         &axg_uart1,
 724         &axg_g2d,
 725         &axg_usb0,
 726         &axg_usb1,
 727         &axg_reset,
 728         &axg_usb_general,
 729         &axg_ahb_arb0,
 730         &axg_efuse,
 731         &axg_boot_rom,
 732         &axg_ahb_data_bus,
 733         &axg_ahb_ctrl_bus,
 734         &axg_usb1_to_ddr,
 735         &axg_usb0_to_ddr,
 736         &axg_mmc_pclk,
 737         &axg_vpu_intr,
 738         &axg_sec_ahb_ahb3_bridge,
 739         &axg_gic,
 740         &axg_ao_media_cpu,
 741         &axg_ao_ahb_sram,
 742         &axg_ao_ahb_bus,
 743         &axg_ao_iface,
 744         &axg_ao_i2c,
 745         &axg_sd_emmc_b_clk0,
 746         &axg_sd_emmc_c_clk0,
 747 };
 748
 749 static struct clk_mux *const axg_clk_muxes[] = {
 750         &axg_mpeg_clk_sel,
 751         &axg_sd_emmc_b_clk0_sel,
 752         &axg_sd_emmc_c_clk0_sel,
 753 };
 754
 755 static struct clk_divider *const axg_clk_dividers[] = {
 756         &axg_mpeg_clk_div,
 757         &axg_sd_emmc_b_clk0_div,
 758         &axg_sd_emmc_c_clk0_div,
 759 };
 760
 761 struct clkc_data {
 762         struct clk_gate *const *clk_gates;
 763         unsigned int clk_gates_count;
 764         struct meson_clk_mpll *const *clk_mplls;
 765         unsigned int clk_mplls_count;
 766         struct meson_clk_pll *const *clk_plls;
 767         unsigned int clk_plls_count;
 768         struct clk_mux *const *clk_muxes;
 769         unsigned int clk_muxes_count;
 770         struct clk_divider *const *clk_dividers;
 771         unsigned int clk_dividers_count;
 772         struct clk_hw_onecell_data *hw_onecell_data;
 773 };
 774
 775 static const struct clkc_data axg_clkc_data = {
 776         .clk_gates = axg_clk_gates,
 777         .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
 778         .clk_mplls = axg_clk_mplls,
 779         .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
 780         .clk_plls = axg_clk_plls,
 781         .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
 782         .clk_muxes = axg_clk_muxes,
 783         .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
 784         .clk_dividers = axg_clk_dividers,
 785         .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
 786         .hw_onecell_data = &axg_hw_onecell_data,
 787 };
 788
 789 static const struct of_device_id clkc_match_table[] = {
 790         { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
 791         {}
 792 };
 793
 794 static int axg_clkc_probe(struct platform_device *pdev)
 795 {
 796         struct device *dev = &pdev->dev;
 797         const struct clkc_data *clkc_data;
 798         struct resource *res;
 799         void __iomem *clk_base;
 800         int ret, i;
 801
 802         clkc_data = of_device_get_match_data(dev);
 803         if (!clkc_data)
 804                 return -EINVAL;
 805
 806         /*  Generic clocks and PLLs */
 807         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 808         if (!res)
 809                 return -EINVAL;
 810         clk_base = devm_ioremap(dev, res->start, resource_size(res));
 811         if (!clk_base) {
 812                 dev_err(dev, "Unable to map clk base\n");
 813                 return -ENXIO;
 814         }
 815
 816         /* Populate base address for PLLs */
 817         for (i = 0; i < clkc_data->clk_plls_count; i++)
 818                 clkc_data->clk_plls[i]->base = clk_base;
 819
 820         /* Populate base address for MPLLs */
 821         for (i = 0; i < clkc_data->clk_mplls_count; i++)
 822                 clkc_data->clk_mplls[i]->base = clk_base;
 823
 824         /* Populate base address for gates */
 825         for (i = 0; i < clkc_data->clk_gates_count; i++)
 826                 clkc_data->clk_gates[i]->reg = clk_base +
 827                         (u64)clkc_data->clk_gates[i]->reg;
 828
 829         /* Populate base address for muxes */
 830         for (i = 0; i < clkc_data->clk_muxes_count; i++)
 831                 clkc_data->clk_muxes[i]->reg = clk_base +
 832                         (u64)clkc_data->clk_muxes[i]->reg;
 833
 834         /* Populate base address for dividers */
 835         for (i = 0; i < clkc_data->clk_dividers_count; i++)
 836                 clkc_data->clk_dividers[i]->reg = clk_base +
 837                         (u64)clkc_data->clk_dividers[i]->reg;
 838
 839         for (i = 0; i < clkc_data->hw_onecell_data->num; i++) {
 840                 /* array might be sparse */
 841                 if (!clkc_data->hw_onecell_data->hws[i])
 842                         continue;
 843
 844                 ret = devm_clk_hw_register(dev,
 845                                            clkc_data->hw_onecell_data->hws[i]);
 846                 if (ret) {
 847                         dev_err(dev, "Clock registration failed\n");
 848                         return ret;
 849                 }
 850         }
 851
 852         return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
 853                                            clkc_data->hw_onecell_data);
 854 }
 855
 856 static struct platform_driver axg_driver = {
 857         .probe          = axg_clkc_probe,
 858         .driver         = {
 859                 .name   = "axg-clkc",
 860                 .of_match_table = clkc_match_table,
 861         },
 862 };
 863
 864 builtin_platform_driver(axg_driver);