1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
5 * Copyright (c) 2016 Baylibre SAS.
6 * Author: Michael Turquette <mturquette@baylibre.com>
8 * Copyright (c) 2017 Amlogic, inc.
9 * Author: Qiufang Dai <qiufang.dai@amlogic.com>
12 #include <linux/clk-provider.h>
13 #include <linux/init.h>
14 #include <linux/of_device.h>
15 #include <linux/platform_device.h>
17 #include "clk-input.h"
18 #include "clk-regmap.h"
22 #include "meson-eeclk.h"
24 static DEFINE_SPINLOCK(meson_clk_lock);
26 static struct clk_regmap axg_fixed_pll_dco = {
27 .data = &(struct meson_clk_pll_data){
29 .reg_off = HHI_MPLL_CNTL,
34 .reg_off = HHI_MPLL_CNTL,
39 .reg_off = HHI_MPLL_CNTL,
44 .reg_off = HHI_MPLL_CNTL2,
49 .reg_off = HHI_MPLL_CNTL,
54 .reg_off = HHI_MPLL_CNTL,
59 .hw.init = &(struct clk_init_data){
60 .name = "fixed_pll_dco",
61 .ops = &meson_clk_pll_ro_ops,
62 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
67 static struct clk_regmap axg_fixed_pll = {
68 .data = &(struct clk_regmap_div_data){
69 .offset = HHI_MPLL_CNTL,
72 .flags = CLK_DIVIDER_POWER_OF_TWO,
74 .hw.init = &(struct clk_init_data){
76 .ops = &clk_regmap_divider_ro_ops,
77 .parent_names = (const char *[]){ "fixed_pll_dco" },
80 * This clock won't ever change at runtime so
81 * CLK_SET_RATE_PARENT is not required
86 static struct clk_regmap axg_sys_pll_dco = {
87 .data = &(struct meson_clk_pll_data){
89 .reg_off = HHI_SYS_PLL_CNTL,
94 .reg_off = HHI_SYS_PLL_CNTL,
99 .reg_off = HHI_SYS_PLL_CNTL,
104 .reg_off = HHI_SYS_PLL_CNTL,
109 .reg_off = HHI_SYS_PLL_CNTL,
114 .hw.init = &(struct clk_init_data){
115 .name = "sys_pll_dco",
116 .ops = &meson_clk_pll_ro_ops,
117 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
122 static struct clk_regmap axg_sys_pll = {
123 .data = &(struct clk_regmap_div_data){
124 .offset = HHI_SYS_PLL_CNTL,
127 .flags = CLK_DIVIDER_POWER_OF_TWO,
129 .hw.init = &(struct clk_init_data){
131 .ops = &clk_regmap_divider_ro_ops,
132 .parent_names = (const char *[]){ "sys_pll_dco" },
134 .flags = CLK_SET_RATE_PARENT,
138 static const struct pll_params_table axg_gp0_pll_params_table[] = {
171 static const struct reg_sequence axg_gp0_init_regs[] = {
172 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
173 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
174 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
175 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
176 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
179 static struct clk_regmap axg_gp0_pll_dco = {
180 .data = &(struct meson_clk_pll_data){
182 .reg_off = HHI_GP0_PLL_CNTL,
187 .reg_off = HHI_GP0_PLL_CNTL,
192 .reg_off = HHI_GP0_PLL_CNTL,
197 .reg_off = HHI_GP0_PLL_CNTL1,
202 .reg_off = HHI_GP0_PLL_CNTL,
207 .reg_off = HHI_GP0_PLL_CNTL,
211 .table = axg_gp0_pll_params_table,
212 .init_regs = axg_gp0_init_regs,
213 .init_count = ARRAY_SIZE(axg_gp0_init_regs),
215 .hw.init = &(struct clk_init_data){
216 .name = "gp0_pll_dco",
217 .ops = &meson_clk_pll_ops,
218 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
223 static struct clk_regmap axg_gp0_pll = {
224 .data = &(struct clk_regmap_div_data){
225 .offset = HHI_GP0_PLL_CNTL,
228 .flags = CLK_DIVIDER_POWER_OF_TWO,
230 .hw.init = &(struct clk_init_data){
232 .ops = &clk_regmap_divider_ops,
233 .parent_names = (const char *[]){ "gp0_pll_dco" },
235 .flags = CLK_SET_RATE_PARENT,
239 static const struct reg_sequence axg_hifi_init_regs[] = {
240 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0xc084b000 },
241 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0xb75020be },
242 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x0a6a3a88 },
243 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0xc000004d },
244 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x00058000 },
247 static struct clk_regmap axg_hifi_pll_dco = {
248 .data = &(struct meson_clk_pll_data){
250 .reg_off = HHI_HIFI_PLL_CNTL,
255 .reg_off = HHI_HIFI_PLL_CNTL,
260 .reg_off = HHI_HIFI_PLL_CNTL,
265 .reg_off = HHI_HIFI_PLL_CNTL5,
270 .reg_off = HHI_HIFI_PLL_CNTL,
275 .reg_off = HHI_HIFI_PLL_CNTL,
279 .table = axg_gp0_pll_params_table,
280 .init_regs = axg_hifi_init_regs,
281 .init_count = ARRAY_SIZE(axg_hifi_init_regs),
282 .flags = CLK_MESON_PLL_ROUND_CLOSEST,
284 .hw.init = &(struct clk_init_data){
285 .name = "hifi_pll_dco",
286 .ops = &meson_clk_pll_ops,
287 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
292 static struct clk_regmap axg_hifi_pll = {
293 .data = &(struct clk_regmap_div_data){
294 .offset = HHI_HIFI_PLL_CNTL,
297 .flags = CLK_DIVIDER_POWER_OF_TWO,
299 .hw.init = &(struct clk_init_data){
301 .ops = &clk_regmap_divider_ops,
302 .parent_names = (const char *[]){ "hifi_pll_dco" },
304 .flags = CLK_SET_RATE_PARENT,
308 static struct clk_fixed_factor axg_fclk_div2_div = {
311 .hw.init = &(struct clk_init_data){
312 .name = "fclk_div2_div",
313 .ops = &clk_fixed_factor_ops,
314 .parent_names = (const char *[]){ "fixed_pll" },
319 static struct clk_regmap axg_fclk_div2 = {
320 .data = &(struct clk_regmap_gate_data){
321 .offset = HHI_MPLL_CNTL6,
324 .hw.init = &(struct clk_init_data){
326 .ops = &clk_regmap_gate_ops,
327 .parent_names = (const char *[]){ "fclk_div2_div" },
329 .flags = CLK_IS_CRITICAL,
333 static struct clk_fixed_factor axg_fclk_div3_div = {
336 .hw.init = &(struct clk_init_data){
337 .name = "fclk_div3_div",
338 .ops = &clk_fixed_factor_ops,
339 .parent_names = (const char *[]){ "fixed_pll" },
344 static struct clk_regmap axg_fclk_div3 = {
345 .data = &(struct clk_regmap_gate_data){
346 .offset = HHI_MPLL_CNTL6,
349 .hw.init = &(struct clk_init_data){
351 .ops = &clk_regmap_gate_ops,
352 .parent_names = (const char *[]){ "fclk_div3_div" },
356 * This clock, as fdiv2, is used by the SCPI FW and is required
357 * by the platform to operate correctly.
358 * Until the following condition are met, we need this clock to
359 * be marked as critical:
360 * a) The SCPI generic driver claims and enable all the clocks
362 * b) CCF has a clock hand-off mechanism to make the sure the
363 * clock stays on until the proper driver comes along
365 .flags = CLK_IS_CRITICAL,
369 static struct clk_fixed_factor axg_fclk_div4_div = {
372 .hw.init = &(struct clk_init_data){
373 .name = "fclk_div4_div",
374 .ops = &clk_fixed_factor_ops,
375 .parent_names = (const char *[]){ "fixed_pll" },
380 static struct clk_regmap axg_fclk_div4 = {
381 .data = &(struct clk_regmap_gate_data){
382 .offset = HHI_MPLL_CNTL6,
385 .hw.init = &(struct clk_init_data){
387 .ops = &clk_regmap_gate_ops,
388 .parent_names = (const char *[]){ "fclk_div4_div" },
393 static struct clk_fixed_factor axg_fclk_div5_div = {
396 .hw.init = &(struct clk_init_data){
397 .name = "fclk_div5_div",
398 .ops = &clk_fixed_factor_ops,
399 .parent_names = (const char *[]){ "fixed_pll" },
404 static struct clk_regmap axg_fclk_div5 = {
405 .data = &(struct clk_regmap_gate_data){
406 .offset = HHI_MPLL_CNTL6,
409 .hw.init = &(struct clk_init_data){
411 .ops = &clk_regmap_gate_ops,
412 .parent_names = (const char *[]){ "fclk_div5_div" },
417 static struct clk_fixed_factor axg_fclk_div7_div = {
420 .hw.init = &(struct clk_init_data){
421 .name = "fclk_div7_div",
422 .ops = &clk_fixed_factor_ops,
423 .parent_names = (const char *[]){ "fixed_pll" },
428 static struct clk_regmap axg_fclk_div7 = {
429 .data = &(struct clk_regmap_gate_data){
430 .offset = HHI_MPLL_CNTL6,
433 .hw.init = &(struct clk_init_data){
435 .ops = &clk_regmap_gate_ops,
436 .parent_names = (const char *[]){ "fclk_div7_div" },
441 static struct clk_regmap axg_mpll_prediv = {
442 .data = &(struct clk_regmap_div_data){
443 .offset = HHI_MPLL_CNTL5,
447 .hw.init = &(struct clk_init_data){
448 .name = "mpll_prediv",
449 .ops = &clk_regmap_divider_ro_ops,
450 .parent_names = (const char *[]){ "fixed_pll" },
455 static struct clk_regmap axg_mpll0_div = {
456 .data = &(struct meson_clk_mpll_data){
458 .reg_off = HHI_MPLL_CNTL7,
463 .reg_off = HHI_MPLL_CNTL7,
468 .reg_off = HHI_MPLL_CNTL7,
473 .reg_off = HHI_MPLL_CNTL,
478 .reg_off = HHI_PLL_TOP_MISC,
482 .lock = &meson_clk_lock,
483 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
485 .hw.init = &(struct clk_init_data){
487 .ops = &meson_clk_mpll_ops,
488 .parent_names = (const char *[]){ "mpll_prediv" },
493 static struct clk_regmap axg_mpll0 = {
494 .data = &(struct clk_regmap_gate_data){
495 .offset = HHI_MPLL_CNTL7,
498 .hw.init = &(struct clk_init_data){
500 .ops = &clk_regmap_gate_ops,
501 .parent_names = (const char *[]){ "mpll0_div" },
503 .flags = CLK_SET_RATE_PARENT,
507 static struct clk_regmap axg_mpll1_div = {
508 .data = &(struct meson_clk_mpll_data){
510 .reg_off = HHI_MPLL_CNTL8,
515 .reg_off = HHI_MPLL_CNTL8,
520 .reg_off = HHI_MPLL_CNTL8,
525 .reg_off = HHI_PLL_TOP_MISC,
529 .lock = &meson_clk_lock,
530 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
532 .hw.init = &(struct clk_init_data){
534 .ops = &meson_clk_mpll_ops,
535 .parent_names = (const char *[]){ "mpll_prediv" },
540 static struct clk_regmap axg_mpll1 = {
541 .data = &(struct clk_regmap_gate_data){
542 .offset = HHI_MPLL_CNTL8,
545 .hw.init = &(struct clk_init_data){
547 .ops = &clk_regmap_gate_ops,
548 .parent_names = (const char *[]){ "mpll1_div" },
550 .flags = CLK_SET_RATE_PARENT,
554 static struct clk_regmap axg_mpll2_div = {
555 .data = &(struct meson_clk_mpll_data){
557 .reg_off = HHI_MPLL_CNTL9,
562 .reg_off = HHI_MPLL_CNTL9,
567 .reg_off = HHI_MPLL_CNTL9,
572 .reg_off = HHI_PLL_TOP_MISC,
576 .lock = &meson_clk_lock,
577 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
579 .hw.init = &(struct clk_init_data){
581 .ops = &meson_clk_mpll_ops,
582 .parent_names = (const char *[]){ "mpll_prediv" },
587 static struct clk_regmap axg_mpll2 = {
588 .data = &(struct clk_regmap_gate_data){
589 .offset = HHI_MPLL_CNTL9,
592 .hw.init = &(struct clk_init_data){
594 .ops = &clk_regmap_gate_ops,
595 .parent_names = (const char *[]){ "mpll2_div" },
597 .flags = CLK_SET_RATE_PARENT,
601 static struct clk_regmap axg_mpll3_div = {
602 .data = &(struct meson_clk_mpll_data){
604 .reg_off = HHI_MPLL3_CNTL0,
609 .reg_off = HHI_MPLL3_CNTL0,
614 .reg_off = HHI_MPLL3_CNTL0,
619 .reg_off = HHI_PLL_TOP_MISC,
623 .lock = &meson_clk_lock,
624 .flags = CLK_MESON_MPLL_ROUND_CLOSEST,
626 .hw.init = &(struct clk_init_data){
628 .ops = &meson_clk_mpll_ops,
629 .parent_names = (const char *[]){ "mpll_prediv" },
634 static struct clk_regmap axg_mpll3 = {
635 .data = &(struct clk_regmap_gate_data){
636 .offset = HHI_MPLL3_CNTL0,
639 .hw.init = &(struct clk_init_data){
641 .ops = &clk_regmap_gate_ops,
642 .parent_names = (const char *[]){ "mpll3_div" },
644 .flags = CLK_SET_RATE_PARENT,
648 static const struct pll_params_table axg_pcie_pll_params_table[] = {
656 static const struct reg_sequence axg_pcie_init_regs[] = {
657 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x0084a2aa },
658 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0xb75020be },
659 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x0a47488e },
660 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0xc000004d },
661 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x00078000 },
662 { .reg = HHI_PCIE_PLL_CNTL6, .def = 0x002323c6 },
663 { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
666 static struct clk_regmap axg_pcie_pll_dco = {
667 .data = &(struct meson_clk_pll_data){
669 .reg_off = HHI_PCIE_PLL_CNTL,
674 .reg_off = HHI_PCIE_PLL_CNTL,
679 .reg_off = HHI_PCIE_PLL_CNTL,
684 .reg_off = HHI_PCIE_PLL_CNTL1,
689 .reg_off = HHI_PCIE_PLL_CNTL,
694 .reg_off = HHI_PCIE_PLL_CNTL,
698 .table = axg_pcie_pll_params_table,
699 .init_regs = axg_pcie_init_regs,
700 .init_count = ARRAY_SIZE(axg_pcie_init_regs),
702 .hw.init = &(struct clk_init_data){
703 .name = "pcie_pll_dco",
704 .ops = &meson_clk_pll_ops,
705 .parent_names = (const char *[]){ IN_PREFIX "xtal" },
710 static struct clk_regmap axg_pcie_pll_od = {
711 .data = &(struct clk_regmap_div_data){
712 .offset = HHI_PCIE_PLL_CNTL,
715 .flags = CLK_DIVIDER_POWER_OF_TWO,
717 .hw.init = &(struct clk_init_data){
718 .name = "pcie_pll_od",
719 .ops = &clk_regmap_divider_ops,
720 .parent_names = (const char *[]){ "pcie_pll_dco" },
722 .flags = CLK_SET_RATE_PARENT,
726 static struct clk_regmap axg_pcie_pll = {
727 .data = &(struct clk_regmap_div_data){
728 .offset = HHI_PCIE_PLL_CNTL6,
731 .flags = CLK_DIVIDER_POWER_OF_TWO,
733 .hw.init = &(struct clk_init_data){
735 .ops = &clk_regmap_divider_ops,
736 .parent_names = (const char *[]){ "pcie_pll_od" },
738 .flags = CLK_SET_RATE_PARENT,
742 static struct clk_regmap axg_pcie_mux = {
743 .data = &(struct clk_regmap_mux_data){
744 .offset = HHI_PCIE_PLL_CNTL6,
747 /* skip the parent mpll3, reserved for debug */
748 .table = (u32[]){ 1 },
750 .hw.init = &(struct clk_init_data){
752 .ops = &clk_regmap_mux_ops,
753 .parent_names = (const char *[]){ "pcie_pll" },
755 .flags = CLK_SET_RATE_PARENT,
759 static struct clk_regmap axg_pcie_ref = {
760 .data = &(struct clk_regmap_mux_data){
761 .offset = HHI_PCIE_PLL_CNTL6,
764 /* skip the parent 0, reserved for debug */
765 .table = (u32[]){ 1 },
767 .hw.init = &(struct clk_init_data){
769 .ops = &clk_regmap_mux_ops,
770 .parent_names = (const char *[]){ "pcie_mux" },
772 .flags = CLK_SET_RATE_PARENT,
776 static struct clk_regmap axg_pcie_cml_en0 = {
777 .data = &(struct clk_regmap_gate_data){
778 .offset = HHI_PCIE_PLL_CNTL6,
781 .hw.init = &(struct clk_init_data) {
782 .name = "pcie_cml_en0",
783 .ops = &clk_regmap_gate_ops,
784 .parent_names = (const char *[]){ "pcie_ref" },
786 .flags = CLK_SET_RATE_PARENT,
791 static struct clk_regmap axg_pcie_cml_en1 = {
792 .data = &(struct clk_regmap_gate_data){
793 .offset = HHI_PCIE_PLL_CNTL6,
796 .hw.init = &(struct clk_init_data) {
797 .name = "pcie_cml_en1",
798 .ops = &clk_regmap_gate_ops,
799 .parent_names = (const char *[]){ "pcie_ref" },
801 .flags = CLK_SET_RATE_PARENT,
805 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
806 static const char * const clk81_parent_names[] = {
807 IN_PREFIX "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
808 "fclk_div3", "fclk_div5"
811 static struct clk_regmap axg_mpeg_clk_sel = {
812 .data = &(struct clk_regmap_mux_data){
813 .offset = HHI_MPEG_CLK_CNTL,
816 .table = mux_table_clk81,
818 .hw.init = &(struct clk_init_data){
819 .name = "mpeg_clk_sel",
820 .ops = &clk_regmap_mux_ro_ops,
821 .parent_names = clk81_parent_names,
822 .num_parents = ARRAY_SIZE(clk81_parent_names),
826 static struct clk_regmap axg_mpeg_clk_div = {
827 .data = &(struct clk_regmap_div_data){
828 .offset = HHI_MPEG_CLK_CNTL,
832 .hw.init = &(struct clk_init_data){
833 .name = "mpeg_clk_div",
834 .ops = &clk_regmap_divider_ops,
835 .parent_names = (const char *[]){ "mpeg_clk_sel" },
837 .flags = CLK_SET_RATE_PARENT,
841 static struct clk_regmap axg_clk81 = {
842 .data = &(struct clk_regmap_gate_data){
843 .offset = HHI_MPEG_CLK_CNTL,
846 .hw.init = &(struct clk_init_data){
848 .ops = &clk_regmap_gate_ops,
849 .parent_names = (const char *[]){ "mpeg_clk_div" },
851 .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
855 static const char * const axg_sd_emmc_clk0_parent_names[] = {
856 IN_PREFIX "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
859 * Following these parent clocks, we should also have had mpll2, mpll3
860 * and gp0_pll but these clocks are too precious to be used here. All
861 * the necessary rates for MMC and NAND operation can be acheived using
862 * xtal or fclk_div clocks
867 static struct clk_regmap axg_sd_emmc_b_clk0_sel = {
868 .data = &(struct clk_regmap_mux_data){
869 .offset = HHI_SD_EMMC_CLK_CNTL,
873 .hw.init = &(struct clk_init_data) {
874 .name = "sd_emmc_b_clk0_sel",
875 .ops = &clk_regmap_mux_ops,
876 .parent_names = axg_sd_emmc_clk0_parent_names,
877 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
878 .flags = CLK_SET_RATE_PARENT,
882 static struct clk_regmap axg_sd_emmc_b_clk0_div = {
883 .data = &(struct clk_regmap_div_data){
884 .offset = HHI_SD_EMMC_CLK_CNTL,
887 .flags = CLK_DIVIDER_ROUND_CLOSEST,
889 .hw.init = &(struct clk_init_data) {
890 .name = "sd_emmc_b_clk0_div",
891 .ops = &clk_regmap_divider_ops,
892 .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
894 .flags = CLK_SET_RATE_PARENT,
898 static struct clk_regmap axg_sd_emmc_b_clk0 = {
899 .data = &(struct clk_regmap_gate_data){
900 .offset = HHI_SD_EMMC_CLK_CNTL,
903 .hw.init = &(struct clk_init_data){
904 .name = "sd_emmc_b_clk0",
905 .ops = &clk_regmap_gate_ops,
906 .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
908 .flags = CLK_SET_RATE_PARENT,
912 /* EMMC/NAND clock */
913 static struct clk_regmap axg_sd_emmc_c_clk0_sel = {
914 .data = &(struct clk_regmap_mux_data){
915 .offset = HHI_NAND_CLK_CNTL,
919 .hw.init = &(struct clk_init_data) {
920 .name = "sd_emmc_c_clk0_sel",
921 .ops = &clk_regmap_mux_ops,
922 .parent_names = axg_sd_emmc_clk0_parent_names,
923 .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
924 .flags = CLK_SET_RATE_PARENT,
928 static struct clk_regmap axg_sd_emmc_c_clk0_div = {
929 .data = &(struct clk_regmap_div_data){
930 .offset = HHI_NAND_CLK_CNTL,
933 .flags = CLK_DIVIDER_ROUND_CLOSEST,
935 .hw.init = &(struct clk_init_data) {
936 .name = "sd_emmc_c_clk0_div",
937 .ops = &clk_regmap_divider_ops,
938 .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
940 .flags = CLK_SET_RATE_PARENT,
944 static struct clk_regmap axg_sd_emmc_c_clk0 = {
945 .data = &(struct clk_regmap_gate_data){
946 .offset = HHI_NAND_CLK_CNTL,
949 .hw.init = &(struct clk_init_data){
950 .name = "sd_emmc_c_clk0",
951 .ops = &clk_regmap_gate_ops,
952 .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
954 .flags = CLK_SET_RATE_PARENT,
958 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
959 9, 10, 11, 13, 14, };
960 static const char * const gen_clk_parent_names[] = {
961 IN_PREFIX "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
962 "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
965 static struct clk_regmap axg_gen_clk_sel = {
966 .data = &(struct clk_regmap_mux_data){
967 .offset = HHI_GEN_CLK_CNTL,
970 .table = mux_table_gen_clk,
972 .hw.init = &(struct clk_init_data){
973 .name = "gen_clk_sel",
974 .ops = &clk_regmap_mux_ops,
976 * bits 15:12 selects from 14 possible parents:
977 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
978 * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
979 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
981 .parent_names = gen_clk_parent_names,
982 .num_parents = ARRAY_SIZE(gen_clk_parent_names),
986 static struct clk_regmap axg_gen_clk_div = {
987 .data = &(struct clk_regmap_div_data){
988 .offset = HHI_GEN_CLK_CNTL,
992 .hw.init = &(struct clk_init_data){
993 .name = "gen_clk_div",
994 .ops = &clk_regmap_divider_ops,
995 .parent_names = (const char *[]){ "gen_clk_sel" },
997 .flags = CLK_SET_RATE_PARENT,
1001 static struct clk_regmap axg_gen_clk = {
1002 .data = &(struct clk_regmap_gate_data){
1003 .offset = HHI_GEN_CLK_CNTL,
1006 .hw.init = &(struct clk_init_data){
1008 .ops = &clk_regmap_gate_ops,
1009 .parent_names = (const char *[]){ "gen_clk_div" },
1011 .flags = CLK_SET_RATE_PARENT,
1015 /* Everything Else (EE) domain gates */
1016 static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
1017 static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
1018 static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
1019 static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
1020 static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
1021 static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
1022 static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
1023 static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
1024 static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
1025 static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
1026 static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
1027 static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
1028 static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
1029 static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
1030 static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
1031 static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
1032 static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
1033 static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
1034 static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
1035 static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
1037 static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
1038 static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
1039 static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
1040 static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
1041 static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
1042 static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
1043 static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
1044 static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
1045 static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
1046 static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
1047 static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
1049 static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
1050 static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
1051 static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
1052 static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
1053 static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
1054 static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
1055 static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
1056 static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
1057 static MESON_GATE(axg_mipi_enable, HHI_MIPI_CNTL0, 29);
1059 /* Always On (AO) domain gates */
1061 static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
1062 static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
1063 static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
1064 static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
1065 static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
1067 /* Array of all clocks provided by this provider */
1069 static struct clk_hw_onecell_data axg_hw_onecell_data = {
1071 [CLKID_SYS_PLL] = &axg_sys_pll.hw,
1072 [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
1073 [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
1074 [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
1075 [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
1076 [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
1077 [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
1078 [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
1079 [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
1080 [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
1081 [CLKID_CLK81] = &axg_clk81.hw,
1082 [CLKID_MPLL0] = &axg_mpll0.hw,
1083 [CLKID_MPLL1] = &axg_mpll1.hw,
1084 [CLKID_MPLL2] = &axg_mpll2.hw,
1085 [CLKID_MPLL3] = &axg_mpll3.hw,
1086 [CLKID_DDR] = &axg_ddr.hw,
1087 [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
1088 [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
1089 [CLKID_ISA] = &axg_isa.hw,
1090 [CLKID_PL301] = &axg_pl301.hw,
1091 [CLKID_PERIPHS] = &axg_periphs.hw,
1092 [CLKID_SPICC0] = &axg_spicc_0.hw,
1093 [CLKID_I2C] = &axg_i2c.hw,
1094 [CLKID_RNG0] = &axg_rng0.hw,
1095 [CLKID_UART0] = &axg_uart0.hw,
1096 [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
1097 [CLKID_SPICC1] = &axg_spicc_1.hw,
1098 [CLKID_PCIE_A] = &axg_pcie_a.hw,
1099 [CLKID_PCIE_B] = &axg_pcie_b.hw,
1100 [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
1101 [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
1102 [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
1103 [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
1104 [CLKID_DMA] = &axg_dma.hw,
1105 [CLKID_SPI] = &axg_spi.hw,
1106 [CLKID_AUDIO] = &axg_audio.hw,
1107 [CLKID_ETH] = &axg_eth_core.hw,
1108 [CLKID_UART1] = &axg_uart1.hw,
1109 [CLKID_G2D] = &axg_g2d.hw,
1110 [CLKID_USB0] = &axg_usb0.hw,
1111 [CLKID_USB1] = &axg_usb1.hw,
1112 [CLKID_RESET] = &axg_reset.hw,
1113 [CLKID_USB] = &axg_usb_general.hw,
1114 [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
1115 [CLKID_EFUSE] = &axg_efuse.hw,
1116 [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
1117 [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
1118 [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
1119 [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
1120 [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
1121 [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
1122 [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
1123 [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
1124 [CLKID_GIC] = &axg_gic.hw,
1125 [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
1126 [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
1127 [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
1128 [CLKID_AO_IFACE] = &axg_ao_iface.hw,
1129 [CLKID_AO_I2C] = &axg_ao_i2c.hw,
1130 [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
1131 [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
1132 [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
1133 [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
1134 [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
1135 [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
1136 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,
1137 [CLKID_MPLL1_DIV] = &axg_mpll1_div.hw,
1138 [CLKID_MPLL2_DIV] = &axg_mpll2_div.hw,
1139 [CLKID_MPLL3_DIV] = &axg_mpll3_div.hw,
1140 [CLKID_HIFI_PLL] = &axg_hifi_pll.hw,
1141 [CLKID_MPLL_PREDIV] = &axg_mpll_prediv.hw,
1142 [CLKID_FCLK_DIV2_DIV] = &axg_fclk_div2_div.hw,
1143 [CLKID_FCLK_DIV3_DIV] = &axg_fclk_div3_div.hw,
1144 [CLKID_FCLK_DIV4_DIV] = &axg_fclk_div4_div.hw,
1145 [CLKID_FCLK_DIV5_DIV] = &axg_fclk_div5_div.hw,
1146 [CLKID_FCLK_DIV7_DIV] = &axg_fclk_div7_div.hw,
1147 [CLKID_PCIE_PLL] = &axg_pcie_pll.hw,
1148 [CLKID_PCIE_MUX] = &axg_pcie_mux.hw,
1149 [CLKID_PCIE_REF] = &axg_pcie_ref.hw,
1150 [CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
1151 [CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
1152 [CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
1153 [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
1154 [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
1155 [CLKID_GEN_CLK] = &axg_gen_clk.hw,
1156 [CLKID_SYS_PLL_DCO] = &axg_sys_pll_dco.hw,
1157 [CLKID_FIXED_PLL_DCO] = &axg_fixed_pll_dco.hw,
1158 [CLKID_GP0_PLL_DCO] = &axg_gp0_pll_dco.hw,
1159 [CLKID_HIFI_PLL_DCO] = &axg_hifi_pll_dco.hw,
1160 [CLKID_PCIE_PLL_DCO] = &axg_pcie_pll_dco.hw,
1161 [CLKID_PCIE_PLL_OD] = &axg_pcie_pll_od.hw,
1167 /* Convenience table to populate regmap in .probe */
1168 static struct clk_regmap *const axg_clk_regmaps[] = {
1207 &axg_sec_ahb_ahb3_bridge,
1214 &axg_sd_emmc_b_clk0,
1215 &axg_sd_emmc_c_clk0,
1217 &axg_sd_emmc_b_clk0_div,
1218 &axg_sd_emmc_c_clk0_div,
1220 &axg_sd_emmc_b_clk0_sel,
1221 &axg_sd_emmc_c_clk0_sel,
1259 static const struct meson_eeclkc_data axg_clkc_data = {
1260 .regmap_clks = axg_clk_regmaps,
1261 .regmap_clk_num = ARRAY_SIZE(axg_clk_regmaps),
1262 .hw_onecell_data = &axg_hw_onecell_data,
1266 static const struct of_device_id clkc_match_table[] = {
1267 { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
1271 static struct platform_driver axg_driver = {
1272 .probe = meson_eeclkc_probe,
1275 .of_match_table = clkc_match_table,
1279 builtin_platform_driver(axg_driver);