1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
3 * Copyright (c) 2018 BayLibre, SAS.
4 * Author: Jerome Brunet <jbrunet@baylibre.com>
7 #ifndef __AXG_AUDIO_CLKC_H
8 #define __AXG_AUDIO_CLKC_H
11 * Audio Clock register offsets
13 * Register offsets from the datasheet must be multiplied by 4 before
14 * to get the right offset
16 #define AUDIO_CLK_GATE_EN 0x000
17 #define AUDIO_MCLK_A_CTRL 0x004
18 #define AUDIO_MCLK_B_CTRL 0x008
19 #define AUDIO_MCLK_C_CTRL 0x00C
20 #define AUDIO_MCLK_D_CTRL 0x010
21 #define AUDIO_MCLK_E_CTRL 0x014
22 #define AUDIO_MCLK_F_CTRL 0x018
23 #define AUDIO_MST_PAD_CTRL0 0x01c
24 #define AUDIO_MST_PAD_CTRL1 0x020
25 #define AUDIO_MST_A_SCLK_CTRL0 0x040
26 #define AUDIO_MST_A_SCLK_CTRL1 0x044
27 #define AUDIO_MST_B_SCLK_CTRL0 0x048
28 #define AUDIO_MST_B_SCLK_CTRL1 0x04C
29 #define AUDIO_MST_C_SCLK_CTRL0 0x050
30 #define AUDIO_MST_C_SCLK_CTRL1 0x054
31 #define AUDIO_MST_D_SCLK_CTRL0 0x058
32 #define AUDIO_MST_D_SCLK_CTRL1 0x05C
33 #define AUDIO_MST_E_SCLK_CTRL0 0x060
34 #define AUDIO_MST_E_SCLK_CTRL1 0x064
35 #define AUDIO_MST_F_SCLK_CTRL0 0x068
36 #define AUDIO_MST_F_SCLK_CTRL1 0x06C
37 #define AUDIO_CLK_TDMIN_A_CTRL 0x080
38 #define AUDIO_CLK_TDMIN_B_CTRL 0x084
39 #define AUDIO_CLK_TDMIN_C_CTRL 0x088
40 #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C
41 #define AUDIO_CLK_TDMOUT_A_CTRL 0x090
42 #define AUDIO_CLK_TDMOUT_B_CTRL 0x094
43 #define AUDIO_CLK_TDMOUT_C_CTRL 0x098
44 #define AUDIO_CLK_SPDIFIN_CTRL 0x09C
45 #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0
46 #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4
47 #define AUDIO_CLK_LOCKER_CTRL 0x0A8
48 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC
49 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0
50 #define AUDIO_CLK_SPDIFOUT_B_CTRL 0x0B4
54 * These indices are entirely contrived and do not map onto the hardware.
57 #define AUD_CLKID_MST_A_MCLK_SEL 59
58 #define AUD_CLKID_MST_B_MCLK_SEL 60
59 #define AUD_CLKID_MST_C_MCLK_SEL 61
60 #define AUD_CLKID_MST_D_MCLK_SEL 62
61 #define AUD_CLKID_MST_E_MCLK_SEL 63
62 #define AUD_CLKID_MST_F_MCLK_SEL 64
63 #define AUD_CLKID_MST_A_MCLK_DIV 65
64 #define AUD_CLKID_MST_B_MCLK_DIV 66
65 #define AUD_CLKID_MST_C_MCLK_DIV 67
66 #define AUD_CLKID_MST_D_MCLK_DIV 68
67 #define AUD_CLKID_MST_E_MCLK_DIV 69
68 #define AUD_CLKID_MST_F_MCLK_DIV 70
69 #define AUD_CLKID_SPDIFOUT_CLK_SEL 71
70 #define AUD_CLKID_SPDIFOUT_CLK_DIV 72
71 #define AUD_CLKID_SPDIFIN_CLK_SEL 73
72 #define AUD_CLKID_SPDIFIN_CLK_DIV 74
73 #define AUD_CLKID_PDM_DCLK_SEL 75
74 #define AUD_CLKID_PDM_DCLK_DIV 76
75 #define AUD_CLKID_PDM_SYSCLK_SEL 77
76 #define AUD_CLKID_PDM_SYSCLK_DIV 78
77 #define AUD_CLKID_MST_A_SCLK_PRE_EN 92
78 #define AUD_CLKID_MST_B_SCLK_PRE_EN 93
79 #define AUD_CLKID_MST_C_SCLK_PRE_EN 94
80 #define AUD_CLKID_MST_D_SCLK_PRE_EN 95
81 #define AUD_CLKID_MST_E_SCLK_PRE_EN 96
82 #define AUD_CLKID_MST_F_SCLK_PRE_EN 97
83 #define AUD_CLKID_MST_A_SCLK_DIV 98
84 #define AUD_CLKID_MST_B_SCLK_DIV 99
85 #define AUD_CLKID_MST_C_SCLK_DIV 100
86 #define AUD_CLKID_MST_D_SCLK_DIV 101
87 #define AUD_CLKID_MST_E_SCLK_DIV 102
88 #define AUD_CLKID_MST_F_SCLK_DIV 103
89 #define AUD_CLKID_MST_A_SCLK_POST_EN 104
90 #define AUD_CLKID_MST_B_SCLK_POST_EN 105
91 #define AUD_CLKID_MST_C_SCLK_POST_EN 106
92 #define AUD_CLKID_MST_D_SCLK_POST_EN 107
93 #define AUD_CLKID_MST_E_SCLK_POST_EN 108
94 #define AUD_CLKID_MST_F_SCLK_POST_EN 109
95 #define AUD_CLKID_MST_A_LRCLK_DIV 110
96 #define AUD_CLKID_MST_B_LRCLK_DIV 111
97 #define AUD_CLKID_MST_C_LRCLK_DIV 112
98 #define AUD_CLKID_MST_D_LRCLK_DIV 113
99 #define AUD_CLKID_MST_E_LRCLK_DIV 114
100 #define AUD_CLKID_MST_F_LRCLK_DIV 115
101 #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137
102 #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138
103 #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139
104 #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140
105 #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141
106 #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142
107 #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143
108 #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144
109 #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145
110 #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146
111 #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147
112 #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148
113 #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149
114 #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150
115 #define AUD_CLKID_SPDIFOUT_B_CLK_SEL 153
116 #define AUD_CLKID_SPDIFOUT_B_CLK_DIV 154
118 /* include the CLKIDs which are part of the DT bindings */
119 #include <dt-bindings/clock/axg-audio-clkc.h>
123 #endif /*__AXG_AUDIO_CLKC_H */