drivers/clk/meson/axg-audio.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright (c) 2018 BayLibre, SAS.
   4  * Author: Jerome Brunet <jbrunet@baylibre.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/init.h>
  10 #include <linux/of_device.h>
  11 #include <linux/module.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/regmap.h>
  14 #include <linux/reset.h>
  15 #include <linux/reset-controller.h>
  16 #include <linux/slab.h>
  17
  18 #include "axg-audio.h"
  19 #include "clk-regmap.h"
  20 #include "clk-phase.h"
  21 #include "sclk-div.h"
  22
  23 #define AUD_MST_IN_COUNT        8
  24 #define AUD_SLV_SCLK_COUNT      10
  25 #define AUD_SLV_LRCLK_COUNT     10
  26
  27 #define AUD_GATE(_name, _reg, _bit, _phws, _iflags)                     \
  28 struct clk_regmap aud_##_name = {                                       \
  29         .data = &(struct clk_regmap_gate_data){                         \
  30                 .offset = (_reg),                                       \
  31                 .bit_idx = (_bit),                                      \
  32         },                                                              \
  33         .hw.init = &(struct clk_init_data) {                            \
  34                 .name = "aud_"#_name,                                   \
  35                 .ops = &clk_regmap_gate_ops,                            \
  36                 .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
  37                 .num_parents = 1,                                       \
  38                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
  39         },                                                              \
  40 }
  41
  42 #define AUD_MUX(_name, _reg, _mask, _shift, _dflags, _pdata, _iflags)   \
  43 struct clk_regmap aud_##_name = {                                       \
  44         .data = &(struct clk_regmap_mux_data){                          \
  45                 .offset = (_reg),                                       \
  46                 .mask = (_mask),                                        \
  47                 .shift = (_shift),                                      \
  48                 .flags = (_dflags),                                     \
  49         },                                                              \
  50         .hw.init = &(struct clk_init_data){                             \
  51                 .name = "aud_"#_name,                                   \
  52                 .ops = &clk_regmap_mux_ops,                             \
  53                 .parent_data = _pdata,                                  \
  54                 .num_parents = ARRAY_SIZE(_pdata),                      \
  55                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
  56         },                                                              \
  57 }
  58
  59 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _phws, _iflags)   \
  60 struct clk_regmap aud_##_name = {                                       \
  61         .data = &(struct clk_regmap_div_data){                          \
  62                 .offset = (_reg),                                       \
  63                 .shift = (_shift),                                      \
  64                 .width = (_width),                                      \
  65                 .flags = (_dflags),                                     \
  66         },                                                              \
  67         .hw.init = &(struct clk_init_data){                             \
  68                 .name = "aud_"#_name,                                   \
  69                 .ops = &clk_regmap_divider_ops,                         \
  70                 .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
  71                 .num_parents = 1,                                       \
  72                 .flags = (_iflags),                                     \
  73         },                                                              \
  74 }
  75
  76 #define AUD_PCLK_GATE(_name, _bit)                              \
  77 struct clk_regmap aud_##_name = {                                       \
  78         .data = &(struct clk_regmap_gate_data){                         \
  79                 .offset = (AUDIO_CLK_GATE_EN),                          \
  80                 .bit_idx = (_bit),                                      \
  81         },                                                              \
  82         .hw.init = &(struct clk_init_data) {                            \
  83                 .name = "aud_"#_name,                                   \
  84                 .ops = &clk_regmap_gate_ops,                            \
  85                 .parent_data = &(const struct clk_parent_data) {        \
  86                         .fw_name = "pclk",                              \
  87                 },                                                      \
  88                 .num_parents = 1,                                       \
  89         },                                                              \
  90 }
  91 /* Audio peripheral clocks */
  92 static AUD_PCLK_GATE(ddr_arb,      0);
  93 static AUD_PCLK_GATE(pdm,          1);
  94 static AUD_PCLK_GATE(tdmin_a,      2);
  95 static AUD_PCLK_GATE(tdmin_b,      3);
  96 static AUD_PCLK_GATE(tdmin_c,      4);
  97 static AUD_PCLK_GATE(tdmin_lb,     5);
  98 static AUD_PCLK_GATE(tdmout_a,     6);
  99 static AUD_PCLK_GATE(tdmout_b,     7);
 100 static AUD_PCLK_GATE(tdmout_c,     8);
 101 static AUD_PCLK_GATE(frddr_a,      9);
 102 static AUD_PCLK_GATE(frddr_b,      10);
 103 static AUD_PCLK_GATE(frddr_c,      11);
 104 static AUD_PCLK_GATE(toddr_a,      12);
 105 static AUD_PCLK_GATE(toddr_b,      13);
 106 static AUD_PCLK_GATE(toddr_c,      14);
 107 static AUD_PCLK_GATE(loopback,     15);
 108 static AUD_PCLK_GATE(spdifin,      16);
 109 static AUD_PCLK_GATE(spdifout,     17);
 110 static AUD_PCLK_GATE(resample,     18);
 111 static AUD_PCLK_GATE(power_detect, 19);
 112 static AUD_PCLK_GATE(spdifout_b,   21);
 113
 114 /* Audio Master Clocks */
 115 static const struct clk_parent_data mst_mux_parent_data[] = {
 116         { .fw_name = "mst_in0", },
 117         { .fw_name = "mst_in1", },
 118         { .fw_name = "mst_in2", },
 119         { .fw_name = "mst_in3", },
 120         { .fw_name = "mst_in4", },
 121         { .fw_name = "mst_in5", },
 122         { .fw_name = "mst_in6", },
 123         { .fw_name = "mst_in7", },
 124 };
 125
 126 #define AUD_MST_MUX(_name, _reg, _flag)                         \
 127         AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag,              \
 128                 mst_mux_parent_data, 0)
 129
 130 #define AUD_MST_MCLK_MUX(_name, _reg)                           \
 131         AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
 132
 133 #define AUD_MST_SYS_MUX(_name, _reg)                            \
 134         AUD_MST_MUX(_name, _reg, 0)
 135
 136 static AUD_MST_MCLK_MUX(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
 137 static AUD_MST_MCLK_MUX(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
 138 static AUD_MST_MCLK_MUX(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
 139 static AUD_MST_MCLK_MUX(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
 140 static AUD_MST_MCLK_MUX(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
 141 static AUD_MST_MCLK_MUX(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
 142 static AUD_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 143 static AUD_MST_MCLK_MUX(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
 144 static AUD_MST_SYS_MUX(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
 145 static AUD_MST_SYS_MUX(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
 146 static AUD_MST_MCLK_MUX(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 147
 148 #define AUD_MST_DIV(_name, _reg, _flag)                         \
 149         AUD_DIV(_name##_div, _reg, 0, 16, _flag,                \
 150                     aud_##_name##_sel, CLK_SET_RATE_PARENT)     \
 151
 152 #define AUD_MST_MCLK_DIV(_name, _reg)                           \
 153         AUD_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
 154
 155 #define AUD_MST_SYS_DIV(_name, _reg)                            \
 156         AUD_MST_DIV(_name, _reg, 0)
 157
 158 static AUD_MST_MCLK_DIV(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
 159 static AUD_MST_MCLK_DIV(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
 160 static AUD_MST_MCLK_DIV(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
 161 static AUD_MST_MCLK_DIV(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
 162 static AUD_MST_MCLK_DIV(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
 163 static AUD_MST_MCLK_DIV(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
 164 static AUD_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 165 static AUD_MST_MCLK_DIV(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
 166 static AUD_MST_SYS_DIV(spdifin_clk,   AUDIO_CLK_SPDIFIN_CTRL);
 167 static AUD_MST_SYS_DIV(pdm_sysclk,    AUDIO_CLK_PDMIN_CTRL1);
 168 static AUD_MST_MCLK_DIV(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 169
 170 #define AUD_MST_MCLK_GATE(_name, _reg)                          \
 171         AUD_GATE(_name, _reg, 31,  aud_##_name##_div,           \
 172                  CLK_SET_RATE_PARENT)
 173
 174 static AUD_MST_MCLK_GATE(mst_a_mclk,   AUDIO_MCLK_A_CTRL);
 175 static AUD_MST_MCLK_GATE(mst_b_mclk,   AUDIO_MCLK_B_CTRL);
 176 static AUD_MST_MCLK_GATE(mst_c_mclk,   AUDIO_MCLK_C_CTRL);
 177 static AUD_MST_MCLK_GATE(mst_d_mclk,   AUDIO_MCLK_D_CTRL);
 178 static AUD_MST_MCLK_GATE(mst_e_mclk,   AUDIO_MCLK_E_CTRL);
 179 static AUD_MST_MCLK_GATE(mst_f_mclk,   AUDIO_MCLK_F_CTRL);
 180 static AUD_MST_MCLK_GATE(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
 181 static AUD_MST_MCLK_GATE(spdifin_clk,  AUDIO_CLK_SPDIFIN_CTRL);
 182 static AUD_MST_MCLK_GATE(pdm_dclk,     AUDIO_CLK_PDMIN_CTRL0);
 183 static AUD_MST_MCLK_GATE(pdm_sysclk,   AUDIO_CLK_PDMIN_CTRL1);
 184 static AUD_MST_MCLK_GATE(spdifout_b_clk, AUDIO_CLK_SPDIFOUT_B_CTRL);
 185
 186 /* Sample Clocks */
 187 #define AUD_MST_SCLK_PRE_EN(_name, _reg)                        \
 188         AUD_GATE(mst_##_name##_sclk_pre_en, _reg, 31,           \
 189                  aud_mst_##_name##_mclk, 0)
 190
 191 static AUD_MST_SCLK_PRE_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 192 static AUD_MST_SCLK_PRE_EN(b, AUDIO_MST_B_SCLK_CTRL0);
 193 static AUD_MST_SCLK_PRE_EN(c, AUDIO_MST_C_SCLK_CTRL0);
 194 static AUD_MST_SCLK_PRE_EN(d, AUDIO_MST_D_SCLK_CTRL0);
 195 static AUD_MST_SCLK_PRE_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 196 static AUD_MST_SCLK_PRE_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 197
 198 #define AUD_SCLK_DIV(_name, _reg, _div_shift, _div_width,               \
 199                          _hi_shift, _hi_width, _phws, _iflags)          \
 200 struct clk_regmap aud_##_name = {                                       \
 201         .data = &(struct meson_sclk_div_data) {                         \
 202                 .div = {                                                \
 203                         .reg_off = (_reg),                              \
 204                         .shift   = (_div_shift),                        \
 205                         .width   = (_div_width),                        \
 206                 },                                                      \
 207                 .hi = {                                                 \
 208                         .reg_off = (_reg),                              \
 209                         .shift   = (_hi_shift),                         \
 210                         .width   = (_hi_width),                         \
 211                 },                                                      \
 212         },                                                              \
 213         .hw.init = &(struct clk_init_data) {                            \
 214                 .name = "aud_"#_name,                                   \
 215                 .ops = &meson_sclk_div_ops,                             \
 216                 .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
 217                 .num_parents = 1,                                       \
 218                 .flags = (_iflags),                                     \
 219         },                                                              \
 220 }
 221
 222 #define AUD_MST_SCLK_DIV(_name, _reg)                                   \
 223         AUD_SCLK_DIV(mst_##_name##_sclk_div, _reg, 20, 10, 0, 0,        \
 224                      aud_mst_##_name##_sclk_pre_en,                     \
 225                      CLK_SET_RATE_PARENT)
 226
 227 static AUD_MST_SCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
 228 static AUD_MST_SCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
 229 static AUD_MST_SCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
 230 static AUD_MST_SCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
 231 static AUD_MST_SCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
 232 static AUD_MST_SCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 233
 234 #define AUD_MST_SCLK_POST_EN(_name, _reg)                               \
 235         AUD_GATE(mst_##_name##_sclk_post_en, _reg, 30,                  \
 236                  aud_mst_##_name##_sclk_div, CLK_SET_RATE_PARENT)
 237
 238 static AUD_MST_SCLK_POST_EN(a, AUDIO_MST_A_SCLK_CTRL0);
 239 static AUD_MST_SCLK_POST_EN(b, AUDIO_MST_B_SCLK_CTRL0);
 240 static AUD_MST_SCLK_POST_EN(c, AUDIO_MST_C_SCLK_CTRL0);
 241 static AUD_MST_SCLK_POST_EN(d, AUDIO_MST_D_SCLK_CTRL0);
 242 static AUD_MST_SCLK_POST_EN(e, AUDIO_MST_E_SCLK_CTRL0);
 243 static AUD_MST_SCLK_POST_EN(f, AUDIO_MST_F_SCLK_CTRL0);
 244
 245 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2,    \
 246                          _phws, _iflags)                                \
 247 struct clk_regmap aud_##_name = {                                       \
 248         .data = &(struct meson_clk_triphase_data) {                     \
 249                 .ph0 = {                                                \
 250                         .reg_off = (_reg),                              \
 251                         .shift   = (_shift0),                           \
 252                         .width   = (_width),                            \
 253                 },                                                      \
 254                 .ph1 = {                                                \
 255                         .reg_off = (_reg),                              \
 256                         .shift   = (_shift1),                           \
 257                         .width   = (_width),                            \
 258                 },                                                      \
 259                 .ph2 = {                                                \
 260                         .reg_off = (_reg),                              \
 261                         .shift   = (_shift2),                           \
 262                         .width   = (_width),                            \
 263                 },                                                      \
 264         },                                                              \
 265         .hw.init = &(struct clk_init_data) {                            \
 266                 .name = "aud_"#_name,                                   \
 267                 .ops = &meson_clk_triphase_ops,                         \
 268                 .parent_hws = (const struct clk_hw *[]) { &_phws.hw },  \
 269                 .num_parents = 1,                                       \
 270                 .flags = CLK_DUTY_CYCLE_PARENT | (_iflags),             \
 271         },                                                              \
 272 }
 273
 274 #define AUD_MST_SCLK(_name, _reg)                                       \
 275         AUD_TRIPHASE(mst_##_name##_sclk, _reg, 1, 0, 2, 4,              \
 276                      aud_mst_##_name##_sclk_post_en, CLK_SET_RATE_PARENT)
 277
 278 static AUD_MST_SCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 279 static AUD_MST_SCLK(b, AUDIO_MST_B_SCLK_CTRL1);
 280 static AUD_MST_SCLK(c, AUDIO_MST_C_SCLK_CTRL1);
 281 static AUD_MST_SCLK(d, AUDIO_MST_D_SCLK_CTRL1);
 282 static AUD_MST_SCLK(e, AUDIO_MST_E_SCLK_CTRL1);
 283 static AUD_MST_SCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 284
 285 #define AUD_MST_LRCLK_DIV(_name, _reg)                                  \
 286         AUD_SCLK_DIV(mst_##_name##_lrclk_div, _reg, 0, 10, 10, 10,      \
 287                      aud_mst_##_name##_sclk_post_en, 0)                 \
 288
 289 static AUD_MST_LRCLK_DIV(a, AUDIO_MST_A_SCLK_CTRL0);
 290 static AUD_MST_LRCLK_DIV(b, AUDIO_MST_B_SCLK_CTRL0);
 291 static AUD_MST_LRCLK_DIV(c, AUDIO_MST_C_SCLK_CTRL0);
 292 static AUD_MST_LRCLK_DIV(d, AUDIO_MST_D_SCLK_CTRL0);
 293 static AUD_MST_LRCLK_DIV(e, AUDIO_MST_E_SCLK_CTRL0);
 294 static AUD_MST_LRCLK_DIV(f, AUDIO_MST_F_SCLK_CTRL0);
 295
 296 #define AUD_MST_LRCLK(_name, _reg)                                      \
 297         AUD_TRIPHASE(mst_##_name##_lrclk, _reg, 1, 1, 3, 5,             \
 298                      aud_mst_##_name##_lrclk_div, CLK_SET_RATE_PARENT)
 299
 300 static AUD_MST_LRCLK(a, AUDIO_MST_A_SCLK_CTRL1);
 301 static AUD_MST_LRCLK(b, AUDIO_MST_B_SCLK_CTRL1);
 302 static AUD_MST_LRCLK(c, AUDIO_MST_C_SCLK_CTRL1);
 303 static AUD_MST_LRCLK(d, AUDIO_MST_D_SCLK_CTRL1);
 304 static AUD_MST_LRCLK(e, AUDIO_MST_E_SCLK_CTRL1);
 305 static AUD_MST_LRCLK(f, AUDIO_MST_F_SCLK_CTRL1);
 306
 307 static const struct clk_parent_data tdm_sclk_parent_data[] = {
 308         { .hw = &aud_mst_a_sclk.hw, },
 309         { .hw = &aud_mst_b_sclk.hw, },
 310         { .hw = &aud_mst_c_sclk.hw, },
 311         { .hw = &aud_mst_d_sclk.hw, },
 312         { .hw = &aud_mst_e_sclk.hw, },
 313         { .hw = &aud_mst_f_sclk.hw, },
 314         { .fw_name = "slv_sclk0", },
 315         { .fw_name = "slv_sclk1", },
 316         { .fw_name = "slv_sclk2", },
 317         { .fw_name = "slv_sclk3", },
 318         { .fw_name = "slv_sclk4", },
 319         { .fw_name = "slv_sclk5", },
 320         { .fw_name = "slv_sclk6", },
 321         { .fw_name = "slv_sclk7", },
 322         { .fw_name = "slv_sclk8", },
 323         { .fw_name = "slv_sclk9", },
 324 };
 325
 326 #define AUD_TDM_SCLK_MUX(_name, _reg)                           \
 327         AUD_MUX(tdm##_name##_sclk_sel, _reg, 0xf, 24,           \
 328                     CLK_MUX_ROUND_CLOSEST,                      \
 329                     tdm_sclk_parent_data, 0)
 330
 331 static AUD_TDM_SCLK_MUX(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 332 static AUD_TDM_SCLK_MUX(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
 333 static AUD_TDM_SCLK_MUX(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
 334 static AUD_TDM_SCLK_MUX(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 335 static AUD_TDM_SCLK_MUX(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 336 static AUD_TDM_SCLK_MUX(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 337 static AUD_TDM_SCLK_MUX(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 338
 339 #define AUD_TDM_SCLK_PRE_EN(_name, _reg)                                \
 340         AUD_GATE(tdm##_name##_sclk_pre_en, _reg, 31,                    \
 341                  aud_tdm##_name##_sclk_sel, CLK_SET_RATE_PARENT)
 342
 343 static AUD_TDM_SCLK_PRE_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 344 static AUD_TDM_SCLK_PRE_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
 345 static AUD_TDM_SCLK_PRE_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
 346 static AUD_TDM_SCLK_PRE_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 347 static AUD_TDM_SCLK_PRE_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 348 static AUD_TDM_SCLK_PRE_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 349 static AUD_TDM_SCLK_PRE_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 350
 351 #define AUD_TDM_SCLK_POST_EN(_name, _reg)                               \
 352         AUD_GATE(tdm##_name##_sclk_post_en, _reg, 30,                   \
 353                  aud_tdm##_name##_sclk_pre_en, CLK_SET_RATE_PARENT)
 354
 355 static AUD_TDM_SCLK_POST_EN(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 356 static AUD_TDM_SCLK_POST_EN(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
 357 static AUD_TDM_SCLK_POST_EN(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
 358 static AUD_TDM_SCLK_POST_EN(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 359 static AUD_TDM_SCLK_POST_EN(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 360 static AUD_TDM_SCLK_POST_EN(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 361 static AUD_TDM_SCLK_POST_EN(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 362
 363 #define AUD_TDM_SCLK(_name, _reg)                                       \
 364         struct clk_regmap aud_tdm##_name##_sclk = {                     \
 365         .data = &(struct meson_clk_phase_data) {                        \
 366                 .ph = {                                                 \
 367                         .reg_off = (_reg),                              \
 368                         .shift   = 29,                                  \
 369                         .width   = 1,                                   \
 370                 },                                                      \
 371         },                                                              \
 372         .hw.init = &(struct clk_init_data) {                            \
 373                 .name = "aud_tdm"#_name"_sclk",                         \
 374                 .ops = &meson_clk_phase_ops,                            \
 375                 .parent_hws = (const struct clk_hw *[]) {               \
 376                         &aud_tdm##_name##_sclk_post_en.hw               \
 377                 },                                                      \
 378                 .num_parents = 1,                                       \
 379                 .flags = CLK_DUTY_CYCLE_PARENT | CLK_SET_RATE_PARENT,   \
 380         },                                                              \
 381 }
 382
 383 static AUD_TDM_SCLK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 384 static AUD_TDM_SCLK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
 385 static AUD_TDM_SCLK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
 386 static AUD_TDM_SCLK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 387 static AUD_TDM_SCLK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 388 static AUD_TDM_SCLK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 389 static AUD_TDM_SCLK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 390
 391 static const struct clk_parent_data tdm_lrclk_parent_data[] = {
 392         { .hw = &aud_mst_a_lrclk.hw, },
 393         { .hw = &aud_mst_b_lrclk.hw, },
 394         { .hw = &aud_mst_c_lrclk.hw, },
 395         { .hw = &aud_mst_d_lrclk.hw, },
 396         { .hw = &aud_mst_e_lrclk.hw, },
 397         { .hw = &aud_mst_f_lrclk.hw, },
 398         { .fw_name = "slv_lrclk0", },
 399         { .fw_name = "slv_lrclk1", },
 400         { .fw_name = "slv_lrclk2", },
 401         { .fw_name = "slv_lrclk3", },
 402         { .fw_name = "slv_lrclk4", },
 403         { .fw_name = "slv_lrclk5", },
 404         { .fw_name = "slv_lrclk6", },
 405         { .fw_name = "slv_lrclk7", },
 406         { .fw_name = "slv_lrclk8", },
 407         { .fw_name = "slv_lrclk9", },
 408 };
 409
 410 #define AUD_TDM_LRLCK(_name, _reg)                      \
 411         AUD_MUX(tdm##_name##_lrclk, _reg, 0xf, 20,      \
 412                 CLK_MUX_ROUND_CLOSEST,                  \
 413                 tdm_lrclk_parent_data, 0)
 414
 415 static AUD_TDM_LRLCK(in_a,  AUDIO_CLK_TDMIN_A_CTRL);
 416 static AUD_TDM_LRLCK(in_b,  AUDIO_CLK_TDMIN_B_CTRL);
 417 static AUD_TDM_LRLCK(in_c,  AUDIO_CLK_TDMIN_C_CTRL);
 418 static AUD_TDM_LRLCK(in_lb, AUDIO_CLK_TDMIN_LB_CTRL);
 419 static AUD_TDM_LRLCK(out_a, AUDIO_CLK_TDMOUT_A_CTRL);
 420 static AUD_TDM_LRLCK(out_b, AUDIO_CLK_TDMOUT_B_CTRL);
 421 static AUD_TDM_LRLCK(out_c, AUDIO_CLK_TDMOUT_C_CTRL);
 422
 423 /* G12a Pad control */
 424 #define AUD_TDM_PAD_CTRL(_name, _reg, _shift, _parents)         \
 425         AUD_MUX(tdm_##_name, _reg, 0x7, _shift, 0, _parents,    \
 426                 CLK_SET_RATE_NO_REPARENT)
 427
 428 static const struct clk_parent_data mclk_pad_ctrl_parent_data[] = {
 429         { .hw = &aud_mst_a_mclk.hw },
 430         { .hw = &aud_mst_b_mclk.hw },
 431         { .hw = &aud_mst_c_mclk.hw },
 432         { .hw = &aud_mst_d_mclk.hw },
 433         { .hw = &aud_mst_e_mclk.hw },
 434         { .hw = &aud_mst_f_mclk.hw },
 435 };
 436
 437 static AUD_TDM_PAD_CTRL(mclk_pad_0, AUDIO_MST_PAD_CTRL0, 0,
 438                         mclk_pad_ctrl_parent_data);
 439 static AUD_TDM_PAD_CTRL(mclk_pad_1, AUDIO_MST_PAD_CTRL0, 4,
 440                         mclk_pad_ctrl_parent_data);
 441
 442 static const struct clk_parent_data lrclk_pad_ctrl_parent_data[] = {
 443         { .hw = &aud_mst_a_lrclk.hw },
 444         { .hw = &aud_mst_b_lrclk.hw },
 445         { .hw = &aud_mst_c_lrclk.hw },
 446         { .hw = &aud_mst_d_lrclk.hw },
 447         { .hw = &aud_mst_e_lrclk.hw },
 448         { .hw = &aud_mst_f_lrclk.hw },
 449 };
 450
 451 static AUD_TDM_PAD_CTRL(lrclk_pad_0, AUDIO_MST_PAD_CTRL1, 16,
 452                         lrclk_pad_ctrl_parent_data);
 453 static AUD_TDM_PAD_CTRL(lrclk_pad_1, AUDIO_MST_PAD_CTRL1, 20,
 454                         lrclk_pad_ctrl_parent_data);
 455 static AUD_TDM_PAD_CTRL(lrclk_pad_2, AUDIO_MST_PAD_CTRL1, 24,
 456                         lrclk_pad_ctrl_parent_data);
 457
 458 static const struct clk_parent_data sclk_pad_ctrl_parent_data[] = {
 459         { .hw = &aud_mst_a_sclk.hw },
 460         { .hw = &aud_mst_b_sclk.hw },
 461         { .hw = &aud_mst_c_sclk.hw },
 462         { .hw = &aud_mst_d_sclk.hw },
 463         { .hw = &aud_mst_e_sclk.hw },
 464         { .hw = &aud_mst_f_sclk.hw },
 465 };
 466
 467 static AUD_TDM_PAD_CTRL(sclk_pad_0, AUDIO_MST_PAD_CTRL1, 0,
 468                         sclk_pad_ctrl_parent_data);
 469 static AUD_TDM_PAD_CTRL(sclk_pad_1, AUDIO_MST_PAD_CTRL1, 4,
 470                         sclk_pad_ctrl_parent_data);
 471 static AUD_TDM_PAD_CTRL(sclk_pad_2, AUDIO_MST_PAD_CTRL1, 8,
 472                         sclk_pad_ctrl_parent_data);
 473
 474 /*
 475  * Array of all clocks provided by this provider
 476  * The input clocks of the controller will be populated at runtime
 477  */
 478 static struct clk_hw_onecell_data axg_audio_hw_onecell_data = {
 479         .hws = {
 480                 [AUD_CLKID_DDR_ARB]             = &aud_ddr_arb.hw,
 481                 [AUD_CLKID_PDM]                 = &aud_pdm.hw,
 482                 [AUD_CLKID_TDMIN_A]             = &aud_tdmin_a.hw,
 483                 [AUD_CLKID_TDMIN_B]             = &aud_tdmin_b.hw,
 484                 [AUD_CLKID_TDMIN_C]             = &aud_tdmin_c.hw,
 485                 [AUD_CLKID_TDMIN_LB]            = &aud_tdmin_lb.hw,
 486                 [AUD_CLKID_TDMOUT_A]            = &aud_tdmout_a.hw,
 487                 [AUD_CLKID_TDMOUT_B]            = &aud_tdmout_b.hw,
 488                 [AUD_CLKID_TDMOUT_C]            = &aud_tdmout_c.hw,
 489                 [AUD_CLKID_FRDDR_A]             = &aud_frddr_a.hw,
 490                 [AUD_CLKID_FRDDR_B]             = &aud_frddr_b.hw,
 491                 [AUD_CLKID_FRDDR_C]             = &aud_frddr_c.hw,
 492                 [AUD_CLKID_TODDR_A]             = &aud_toddr_a.hw,
 493                 [AUD_CLKID_TODDR_B]             = &aud_toddr_b.hw,
 494                 [AUD_CLKID_TODDR_C]             = &aud_toddr_c.hw,
 495                 [AUD_CLKID_LOOPBACK]            = &aud_loopback.hw,
 496                 [AUD_CLKID_SPDIFIN]             = &aud_spdifin.hw,
 497                 [AUD_CLKID_SPDIFOUT]            = &aud_spdifout.hw,
 498                 [AUD_CLKID_RESAMPLE]            = &aud_resample.hw,
 499                 [AUD_CLKID_POWER_DETECT]        = &aud_power_detect.hw,
 500                 [AUD_CLKID_MST_A_MCLK_SEL]      = &aud_mst_a_mclk_sel.hw,
 501                 [AUD_CLKID_MST_B_MCLK_SEL]      = &aud_mst_b_mclk_sel.hw,
 502                 [AUD_CLKID_MST_C_MCLK_SEL]      = &aud_mst_c_mclk_sel.hw,
 503                 [AUD_CLKID_MST_D_MCLK_SEL]      = &aud_mst_d_mclk_sel.hw,
 504                 [AUD_CLKID_MST_E_MCLK_SEL]      = &aud_mst_e_mclk_sel.hw,
 505                 [AUD_CLKID_MST_F_MCLK_SEL]      = &aud_mst_f_mclk_sel.hw,
 506                 [AUD_CLKID_MST_A_MCLK_DIV]      = &aud_mst_a_mclk_div.hw,
 507                 [AUD_CLKID_MST_B_MCLK_DIV]      = &aud_mst_b_mclk_div.hw,
 508                 [AUD_CLKID_MST_C_MCLK_DIV]      = &aud_mst_c_mclk_div.hw,
 509                 [AUD_CLKID_MST_D_MCLK_DIV]      = &aud_mst_d_mclk_div.hw,
 510                 [AUD_CLKID_MST_E_MCLK_DIV]      = &aud_mst_e_mclk_div.hw,
 511                 [AUD_CLKID_MST_F_MCLK_DIV]      = &aud_mst_f_mclk_div.hw,
 512                 [AUD_CLKID_MST_A_MCLK]          = &aud_mst_a_mclk.hw,
 513                 [AUD_CLKID_MST_B_MCLK]          = &aud_mst_b_mclk.hw,
 514                 [AUD_CLKID_MST_C_MCLK]          = &aud_mst_c_mclk.hw,
 515                 [AUD_CLKID_MST_D_MCLK]          = &aud_mst_d_mclk.hw,
 516                 [AUD_CLKID_MST_E_MCLK]          = &aud_mst_e_mclk.hw,
 517                 [AUD_CLKID_MST_F_MCLK]          = &aud_mst_f_mclk.hw,
 518                 [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &aud_spdifout_clk_sel.hw,
 519                 [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &aud_spdifout_clk_div.hw,
 520                 [AUD_CLKID_SPDIFOUT_CLK]        = &aud_spdifout_clk.hw,
 521                 [AUD_CLKID_SPDIFIN_CLK_SEL]     = &aud_spdifin_clk_sel.hw,
 522                 [AUD_CLKID_SPDIFIN_CLK_DIV]     = &aud_spdifin_clk_div.hw,
 523                 [AUD_CLKID_SPDIFIN_CLK]         = &aud_spdifin_clk.hw,
 524                 [AUD_CLKID_PDM_DCLK_SEL]        = &aud_pdm_dclk_sel.hw,
 525                 [AUD_CLKID_PDM_DCLK_DIV]        = &aud_pdm_dclk_div.hw,
 526                 [AUD_CLKID_PDM_DCLK]            = &aud_pdm_dclk.hw,
 527                 [AUD_CLKID_PDM_SYSCLK_SEL]      = &aud_pdm_sysclk_sel.hw,
 528                 [AUD_CLKID_PDM_SYSCLK_DIV]      = &aud_pdm_sysclk_div.hw,
 529                 [AUD_CLKID_PDM_SYSCLK]          = &aud_pdm_sysclk.hw,
 530                 [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &aud_mst_a_sclk_pre_en.hw,
 531                 [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &aud_mst_b_sclk_pre_en.hw,
 532                 [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &aud_mst_c_sclk_pre_en.hw,
 533                 [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &aud_mst_d_sclk_pre_en.hw,
 534                 [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &aud_mst_e_sclk_pre_en.hw,
 535                 [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &aud_mst_f_sclk_pre_en.hw,
 536                 [AUD_CLKID_MST_A_SCLK_DIV]      = &aud_mst_a_sclk_div.hw,
 537                 [AUD_CLKID_MST_B_SCLK_DIV]      = &aud_mst_b_sclk_div.hw,
 538                 [AUD_CLKID_MST_C_SCLK_DIV]      = &aud_mst_c_sclk_div.hw,
 539                 [AUD_CLKID_MST_D_SCLK_DIV]      = &aud_mst_d_sclk_div.hw,
 540                 [AUD_CLKID_MST_E_SCLK_DIV]      = &aud_mst_e_sclk_div.hw,
 541                 [AUD_CLKID_MST_F_SCLK_DIV]      = &aud_mst_f_sclk_div.hw,
 542                 [AUD_CLKID_MST_A_SCLK_POST_EN]  = &aud_mst_a_sclk_post_en.hw,
 543                 [AUD_CLKID_MST_B_SCLK_POST_EN]  = &aud_mst_b_sclk_post_en.hw,
 544                 [AUD_CLKID_MST_C_SCLK_POST_EN]  = &aud_mst_c_sclk_post_en.hw,
 545                 [AUD_CLKID_MST_D_SCLK_POST_EN]  = &aud_mst_d_sclk_post_en.hw,
 546                 [AUD_CLKID_MST_E_SCLK_POST_EN]  = &aud_mst_e_sclk_post_en.hw,
 547                 [AUD_CLKID_MST_F_SCLK_POST_EN]  = &aud_mst_f_sclk_post_en.hw,
 548                 [AUD_CLKID_MST_A_SCLK]          = &aud_mst_a_sclk.hw,
 549                 [AUD_CLKID_MST_B_SCLK]          = &aud_mst_b_sclk.hw,
 550                 [AUD_CLKID_MST_C_SCLK]          = &aud_mst_c_sclk.hw,
 551                 [AUD_CLKID_MST_D_SCLK]          = &aud_mst_d_sclk.hw,
 552                 [AUD_CLKID_MST_E_SCLK]          = &aud_mst_e_sclk.hw,
 553                 [AUD_CLKID_MST_F_SCLK]          = &aud_mst_f_sclk.hw,
 554                 [AUD_CLKID_MST_A_LRCLK_DIV]     = &aud_mst_a_lrclk_div.hw,
 555                 [AUD_CLKID_MST_B_LRCLK_DIV]     = &aud_mst_b_lrclk_div.hw,
 556                 [AUD_CLKID_MST_C_LRCLK_DIV]     = &aud_mst_c_lrclk_div.hw,
 557                 [AUD_CLKID_MST_D_LRCLK_DIV]     = &aud_mst_d_lrclk_div.hw,
 558                 [AUD_CLKID_MST_E_LRCLK_DIV]     = &aud_mst_e_lrclk_div.hw,
 559                 [AUD_CLKID_MST_F_LRCLK_DIV]     = &aud_mst_f_lrclk_div.hw,
 560                 [AUD_CLKID_MST_A_LRCLK]         = &aud_mst_a_lrclk.hw,
 561                 [AUD_CLKID_MST_B_LRCLK]         = &aud_mst_b_lrclk.hw,
 562                 [AUD_CLKID_MST_C_LRCLK]         = &aud_mst_c_lrclk.hw,
 563                 [AUD_CLKID_MST_D_LRCLK]         = &aud_mst_d_lrclk.hw,
 564                 [AUD_CLKID_MST_E_LRCLK]         = &aud_mst_e_lrclk.hw,
 565                 [AUD_CLKID_MST_F_LRCLK]         = &aud_mst_f_lrclk.hw,
 566                 [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &aud_tdmin_a_sclk_sel.hw,
 567                 [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &aud_tdmin_b_sclk_sel.hw,
 568                 [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &aud_tdmin_c_sclk_sel.hw,
 569                 [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &aud_tdmin_lb_sclk_sel.hw,
 570                 [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &aud_tdmout_a_sclk_sel.hw,
 571                 [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &aud_tdmout_b_sclk_sel.hw,
 572                 [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &aud_tdmout_c_sclk_sel.hw,
 573                 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
 574                 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
 575                 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
 576                 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
 577                 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
 578                 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
 579                 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
 580                 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
 581                 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
 582                 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
 583                 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
 584                 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
 585                 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
 586                 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
 587                 [AUD_CLKID_TDMIN_A_SCLK]        = &aud_tdmin_a_sclk.hw,
 588                 [AUD_CLKID_TDMIN_B_SCLK]        = &aud_tdmin_b_sclk.hw,
 589                 [AUD_CLKID_TDMIN_C_SCLK]        = &aud_tdmin_c_sclk.hw,
 590                 [AUD_CLKID_TDMIN_LB_SCLK]       = &aud_tdmin_lb_sclk.hw,
 591                 [AUD_CLKID_TDMOUT_A_SCLK]       = &aud_tdmout_a_sclk.hw,
 592                 [AUD_CLKID_TDMOUT_B_SCLK]       = &aud_tdmout_b_sclk.hw,
 593                 [AUD_CLKID_TDMOUT_C_SCLK]       = &aud_tdmout_c_sclk.hw,
 594                 [AUD_CLKID_TDMIN_A_LRCLK]       = &aud_tdmin_a_lrclk.hw,
 595                 [AUD_CLKID_TDMIN_B_LRCLK]       = &aud_tdmin_b_lrclk.hw,
 596                 [AUD_CLKID_TDMIN_C_LRCLK]       = &aud_tdmin_c_lrclk.hw,
 597                 [AUD_CLKID_TDMIN_LB_LRCLK]      = &aud_tdmin_lb_lrclk.hw,
 598                 [AUD_CLKID_TDMOUT_A_LRCLK]      = &aud_tdmout_a_lrclk.hw,
 599                 [AUD_CLKID_TDMOUT_B_LRCLK]      = &aud_tdmout_b_lrclk.hw,
 600                 [AUD_CLKID_TDMOUT_C_LRCLK]      = &aud_tdmout_c_lrclk.hw,
 601                 [NR_CLKS] = NULL,
 602         },
 603         .num = NR_CLKS,
 604 };
 605
 606 /*
 607  * Array of all G12A clocks provided by this provider
 608  * The input clocks of the controller will be populated at runtime
 609  */
 610 static struct clk_hw_onecell_data g12a_audio_hw_onecell_data = {
 611         .hws = {
 612                 [AUD_CLKID_DDR_ARB]             = &aud_ddr_arb.hw,
 613                 [AUD_CLKID_PDM]                 = &aud_pdm.hw,
 614                 [AUD_CLKID_TDMIN_A]             = &aud_tdmin_a.hw,
 615                 [AUD_CLKID_TDMIN_B]             = &aud_tdmin_b.hw,
 616                 [AUD_CLKID_TDMIN_C]             = &aud_tdmin_c.hw,
 617                 [AUD_CLKID_TDMIN_LB]            = &aud_tdmin_lb.hw,
 618                 [AUD_CLKID_TDMOUT_A]            = &aud_tdmout_a.hw,
 619                 [AUD_CLKID_TDMOUT_B]            = &aud_tdmout_b.hw,
 620                 [AUD_CLKID_TDMOUT_C]            = &aud_tdmout_c.hw,
 621                 [AUD_CLKID_FRDDR_A]             = &aud_frddr_a.hw,
 622                 [AUD_CLKID_FRDDR_B]             = &aud_frddr_b.hw,
 623                 [AUD_CLKID_FRDDR_C]             = &aud_frddr_c.hw,
 624                 [AUD_CLKID_TODDR_A]             = &aud_toddr_a.hw,
 625                 [AUD_CLKID_TODDR_B]             = &aud_toddr_b.hw,
 626                 [AUD_CLKID_TODDR_C]             = &aud_toddr_c.hw,
 627                 [AUD_CLKID_LOOPBACK]            = &aud_loopback.hw,
 628                 [AUD_CLKID_SPDIFIN]             = &aud_spdifin.hw,
 629                 [AUD_CLKID_SPDIFOUT]            = &aud_spdifout.hw,
 630                 [AUD_CLKID_RESAMPLE]            = &aud_resample.hw,
 631                 [AUD_CLKID_POWER_DETECT]        = &aud_power_detect.hw,
 632                 [AUD_CLKID_SPDIFOUT_B]          = &aud_spdifout_b.hw,
 633                 [AUD_CLKID_MST_A_MCLK_SEL]      = &aud_mst_a_mclk_sel.hw,
 634                 [AUD_CLKID_MST_B_MCLK_SEL]      = &aud_mst_b_mclk_sel.hw,
 635                 [AUD_CLKID_MST_C_MCLK_SEL]      = &aud_mst_c_mclk_sel.hw,
 636                 [AUD_CLKID_MST_D_MCLK_SEL]      = &aud_mst_d_mclk_sel.hw,
 637                 [AUD_CLKID_MST_E_MCLK_SEL]      = &aud_mst_e_mclk_sel.hw,
 638                 [AUD_CLKID_MST_F_MCLK_SEL]      = &aud_mst_f_mclk_sel.hw,
 639                 [AUD_CLKID_MST_A_MCLK_DIV]      = &aud_mst_a_mclk_div.hw,
 640                 [AUD_CLKID_MST_B_MCLK_DIV]      = &aud_mst_b_mclk_div.hw,
 641                 [AUD_CLKID_MST_C_MCLK_DIV]      = &aud_mst_c_mclk_div.hw,
 642                 [AUD_CLKID_MST_D_MCLK_DIV]      = &aud_mst_d_mclk_div.hw,
 643                 [AUD_CLKID_MST_E_MCLK_DIV]      = &aud_mst_e_mclk_div.hw,
 644                 [AUD_CLKID_MST_F_MCLK_DIV]      = &aud_mst_f_mclk_div.hw,
 645                 [AUD_CLKID_MST_A_MCLK]          = &aud_mst_a_mclk.hw,
 646                 [AUD_CLKID_MST_B_MCLK]          = &aud_mst_b_mclk.hw,
 647                 [AUD_CLKID_MST_C_MCLK]          = &aud_mst_c_mclk.hw,
 648                 [AUD_CLKID_MST_D_MCLK]          = &aud_mst_d_mclk.hw,
 649                 [AUD_CLKID_MST_E_MCLK]          = &aud_mst_e_mclk.hw,
 650                 [AUD_CLKID_MST_F_MCLK]          = &aud_mst_f_mclk.hw,
 651                 [AUD_CLKID_SPDIFOUT_CLK_SEL]    = &aud_spdifout_clk_sel.hw,
 652                 [AUD_CLKID_SPDIFOUT_CLK_DIV]    = &aud_spdifout_clk_div.hw,
 653                 [AUD_CLKID_SPDIFOUT_CLK]        = &aud_spdifout_clk.hw,
 654                 [AUD_CLKID_SPDIFOUT_B_CLK_SEL]  = &aud_spdifout_b_clk_sel.hw,
 655                 [AUD_CLKID_SPDIFOUT_B_CLK_DIV]  = &aud_spdifout_b_clk_div.hw,
 656                 [AUD_CLKID_SPDIFOUT_B_CLK]      = &aud_spdifout_b_clk.hw,
 657                 [AUD_CLKID_SPDIFIN_CLK_SEL]     = &aud_spdifin_clk_sel.hw,
 658                 [AUD_CLKID_SPDIFIN_CLK_DIV]     = &aud_spdifin_clk_div.hw,
 659                 [AUD_CLKID_SPDIFIN_CLK]         = &aud_spdifin_clk.hw,
 660                 [AUD_CLKID_PDM_DCLK_SEL]        = &aud_pdm_dclk_sel.hw,
 661                 [AUD_CLKID_PDM_DCLK_DIV]        = &aud_pdm_dclk_div.hw,
 662                 [AUD_CLKID_PDM_DCLK]            = &aud_pdm_dclk.hw,
 663                 [AUD_CLKID_PDM_SYSCLK_SEL]      = &aud_pdm_sysclk_sel.hw,
 664                 [AUD_CLKID_PDM_SYSCLK_DIV]      = &aud_pdm_sysclk_div.hw,
 665                 [AUD_CLKID_PDM_SYSCLK]          = &aud_pdm_sysclk.hw,
 666                 [AUD_CLKID_MST_A_SCLK_PRE_EN]   = &aud_mst_a_sclk_pre_en.hw,
 667                 [AUD_CLKID_MST_B_SCLK_PRE_EN]   = &aud_mst_b_sclk_pre_en.hw,
 668                 [AUD_CLKID_MST_C_SCLK_PRE_EN]   = &aud_mst_c_sclk_pre_en.hw,
 669                 [AUD_CLKID_MST_D_SCLK_PRE_EN]   = &aud_mst_d_sclk_pre_en.hw,
 670                 [AUD_CLKID_MST_E_SCLK_PRE_EN]   = &aud_mst_e_sclk_pre_en.hw,
 671                 [AUD_CLKID_MST_F_SCLK_PRE_EN]   = &aud_mst_f_sclk_pre_en.hw,
 672                 [AUD_CLKID_MST_A_SCLK_DIV]      = &aud_mst_a_sclk_div.hw,
 673                 [AUD_CLKID_MST_B_SCLK_DIV]      = &aud_mst_b_sclk_div.hw,
 674                 [AUD_CLKID_MST_C_SCLK_DIV]      = &aud_mst_c_sclk_div.hw,
 675                 [AUD_CLKID_MST_D_SCLK_DIV]      = &aud_mst_d_sclk_div.hw,
 676                 [AUD_CLKID_MST_E_SCLK_DIV]      = &aud_mst_e_sclk_div.hw,
 677                 [AUD_CLKID_MST_F_SCLK_DIV]      = &aud_mst_f_sclk_div.hw,
 678                 [AUD_CLKID_MST_A_SCLK_POST_EN]  = &aud_mst_a_sclk_post_en.hw,
 679                 [AUD_CLKID_MST_B_SCLK_POST_EN]  = &aud_mst_b_sclk_post_en.hw,
 680                 [AUD_CLKID_MST_C_SCLK_POST_EN]  = &aud_mst_c_sclk_post_en.hw,
 681                 [AUD_CLKID_MST_D_SCLK_POST_EN]  = &aud_mst_d_sclk_post_en.hw,
 682                 [AUD_CLKID_MST_E_SCLK_POST_EN]  = &aud_mst_e_sclk_post_en.hw,
 683                 [AUD_CLKID_MST_F_SCLK_POST_EN]  = &aud_mst_f_sclk_post_en.hw,
 684                 [AUD_CLKID_MST_A_SCLK]          = &aud_mst_a_sclk.hw,
 685                 [AUD_CLKID_MST_B_SCLK]          = &aud_mst_b_sclk.hw,
 686                 [AUD_CLKID_MST_C_SCLK]          = &aud_mst_c_sclk.hw,
 687                 [AUD_CLKID_MST_D_SCLK]          = &aud_mst_d_sclk.hw,
 688                 [AUD_CLKID_MST_E_SCLK]          = &aud_mst_e_sclk.hw,
 689                 [AUD_CLKID_MST_F_SCLK]          = &aud_mst_f_sclk.hw,
 690                 [AUD_CLKID_MST_A_LRCLK_DIV]     = &aud_mst_a_lrclk_div.hw,
 691                 [AUD_CLKID_MST_B_LRCLK_DIV]     = &aud_mst_b_lrclk_div.hw,
 692                 [AUD_CLKID_MST_C_LRCLK_DIV]     = &aud_mst_c_lrclk_div.hw,
 693                 [AUD_CLKID_MST_D_LRCLK_DIV]     = &aud_mst_d_lrclk_div.hw,
 694                 [AUD_CLKID_MST_E_LRCLK_DIV]     = &aud_mst_e_lrclk_div.hw,
 695                 [AUD_CLKID_MST_F_LRCLK_DIV]     = &aud_mst_f_lrclk_div.hw,
 696                 [AUD_CLKID_MST_A_LRCLK]         = &aud_mst_a_lrclk.hw,
 697                 [AUD_CLKID_MST_B_LRCLK]         = &aud_mst_b_lrclk.hw,
 698                 [AUD_CLKID_MST_C_LRCLK]         = &aud_mst_c_lrclk.hw,
 699                 [AUD_CLKID_MST_D_LRCLK]         = &aud_mst_d_lrclk.hw,
 700                 [AUD_CLKID_MST_E_LRCLK]         = &aud_mst_e_lrclk.hw,
 701                 [AUD_CLKID_MST_F_LRCLK]         = &aud_mst_f_lrclk.hw,
 702                 [AUD_CLKID_TDMIN_A_SCLK_SEL]    = &aud_tdmin_a_sclk_sel.hw,
 703                 [AUD_CLKID_TDMIN_B_SCLK_SEL]    = &aud_tdmin_b_sclk_sel.hw,
 704                 [AUD_CLKID_TDMIN_C_SCLK_SEL]    = &aud_tdmin_c_sclk_sel.hw,
 705                 [AUD_CLKID_TDMIN_LB_SCLK_SEL]   = &aud_tdmin_lb_sclk_sel.hw,
 706                 [AUD_CLKID_TDMOUT_A_SCLK_SEL]   = &aud_tdmout_a_sclk_sel.hw,
 707                 [AUD_CLKID_TDMOUT_B_SCLK_SEL]   = &aud_tdmout_b_sclk_sel.hw,
 708                 [AUD_CLKID_TDMOUT_C_SCLK_SEL]   = &aud_tdmout_c_sclk_sel.hw,
 709                 [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &aud_tdmin_a_sclk_pre_en.hw,
 710                 [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &aud_tdmin_b_sclk_pre_en.hw,
 711                 [AUD_CLKID_TDMIN_C_SCLK_PRE_EN] = &aud_tdmin_c_sclk_pre_en.hw,
 712                 [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &aud_tdmin_lb_sclk_pre_en.hw,
 713                 [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &aud_tdmout_a_sclk_pre_en.hw,
 714                 [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &aud_tdmout_b_sclk_pre_en.hw,
 715                 [AUD_CLKID_TDMOUT_C_SCLK_PRE_EN] = &aud_tdmout_c_sclk_pre_en.hw,
 716                 [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &aud_tdmin_a_sclk_post_en.hw,
 717                 [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &aud_tdmin_b_sclk_post_en.hw,
 718                 [AUD_CLKID_TDMIN_C_SCLK_POST_EN] = &aud_tdmin_c_sclk_post_en.hw,
 719                 [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &aud_tdmin_lb_sclk_post_en.hw,
 720                 [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &aud_tdmout_a_sclk_post_en.hw,
 721                 [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &aud_tdmout_b_sclk_post_en.hw,
 722                 [AUD_CLKID_TDMOUT_C_SCLK_POST_EN] = &aud_tdmout_c_sclk_post_en.hw,
 723                 [AUD_CLKID_TDMIN_A_SCLK]        = &aud_tdmin_a_sclk.hw,
 724                 [AUD_CLKID_TDMIN_B_SCLK]        = &aud_tdmin_b_sclk.hw,
 725                 [AUD_CLKID_TDMIN_C_SCLK]        = &aud_tdmin_c_sclk.hw,
 726                 [AUD_CLKID_TDMIN_LB_SCLK]       = &aud_tdmin_lb_sclk.hw,
 727                 [AUD_CLKID_TDMOUT_A_SCLK]       = &aud_tdmout_a_sclk.hw,
 728                 [AUD_CLKID_TDMOUT_B_SCLK]       = &aud_tdmout_b_sclk.hw,
 729                 [AUD_CLKID_TDMOUT_C_SCLK]       = &aud_tdmout_c_sclk.hw,
 730                 [AUD_CLKID_TDMIN_A_LRCLK]       = &aud_tdmin_a_lrclk.hw,
 731                 [AUD_CLKID_TDMIN_B_LRCLK]       = &aud_tdmin_b_lrclk.hw,
 732                 [AUD_CLKID_TDMIN_C_LRCLK]       = &aud_tdmin_c_lrclk.hw,
 733                 [AUD_CLKID_TDMIN_LB_LRCLK]      = &aud_tdmin_lb_lrclk.hw,
 734                 [AUD_CLKID_TDMOUT_A_LRCLK]      = &aud_tdmout_a_lrclk.hw,
 735                 [AUD_CLKID_TDMOUT_B_LRCLK]      = &aud_tdmout_b_lrclk.hw,
 736                 [AUD_CLKID_TDMOUT_C_LRCLK]      = &aud_tdmout_c_lrclk.hw,
 737                 [AUD_CLKID_TDM_MCLK_PAD0]       = &aud_tdm_mclk_pad_0.hw,
 738                 [AUD_CLKID_TDM_MCLK_PAD1]       = &aud_tdm_mclk_pad_1.hw,
 739                 [AUD_CLKID_TDM_LRCLK_PAD0]      = &aud_tdm_lrclk_pad_0.hw,
 740                 [AUD_CLKID_TDM_LRCLK_PAD1]      = &aud_tdm_lrclk_pad_1.hw,
 741                 [AUD_CLKID_TDM_LRCLK_PAD2]      = &aud_tdm_lrclk_pad_2.hw,
 742                 [AUD_CLKID_TDM_SCLK_PAD0]       = &aud_tdm_sclk_pad_0.hw,
 743                 [AUD_CLKID_TDM_SCLK_PAD1]       = &aud_tdm_sclk_pad_1.hw,
 744                 [AUD_CLKID_TDM_SCLK_PAD2]       = &aud_tdm_sclk_pad_2.hw,
 745                 [NR_CLKS] = NULL,
 746         },
 747         .num = NR_CLKS,
 748 };
 749
 750 /* Convenience table to populate regmap in .probe()
 751  * Note that this table is shared between both AXG and G12A,
 752  * with spdifout_b clocks being exclusive to G12A. Since those
 753  * clocks are not declared within the AXG onecell table, we do not
 754  * feel the need to have separate AXG/G12A regmap tables.
 755  */
 756 static struct clk_regmap *const aud_clk_regmaps[] = {
 757         &aud_ddr_arb,
 758         &aud_pdm,
 759         &aud_tdmin_a,
 760         &aud_tdmin_b,
 761         &aud_tdmin_c,
 762         &aud_tdmin_lb,
 763         &aud_tdmout_a,
 764         &aud_tdmout_b,
 765         &aud_tdmout_c,
 766         &aud_frddr_a,
 767         &aud_frddr_b,
 768         &aud_frddr_c,
 769         &aud_toddr_a,
 770         &aud_toddr_b,
 771         &aud_toddr_c,
 772         &aud_loopback,
 773         &aud_spdifin,
 774         &aud_spdifout,
 775         &aud_resample,
 776         &aud_power_detect,
 777         &aud_spdifout_b,
 778         &aud_mst_a_mclk_sel,
 779         &aud_mst_b_mclk_sel,
 780         &aud_mst_c_mclk_sel,
 781         &aud_mst_d_mclk_sel,
 782         &aud_mst_e_mclk_sel,
 783         &aud_mst_f_mclk_sel,
 784         &aud_mst_a_mclk_div,
 785         &aud_mst_b_mclk_div,
 786         &aud_mst_c_mclk_div,
 787         &aud_mst_d_mclk_div,
 788         &aud_mst_e_mclk_div,
 789         &aud_mst_f_mclk_div,
 790         &aud_mst_a_mclk,
 791         &aud_mst_b_mclk,
 792         &aud_mst_c_mclk,
 793         &aud_mst_d_mclk,
 794         &aud_mst_e_mclk,
 795         &aud_mst_f_mclk,
 796         &aud_spdifout_clk_sel,
 797         &aud_spdifout_clk_div,
 798         &aud_spdifout_clk,
 799         &aud_spdifin_clk_sel,
 800         &aud_spdifin_clk_div,
 801         &aud_spdifin_clk,
 802         &aud_pdm_dclk_sel,
 803         &aud_pdm_dclk_div,
 804         &aud_pdm_dclk,
 805         &aud_pdm_sysclk_sel,
 806         &aud_pdm_sysclk_div,
 807         &aud_pdm_sysclk,
 808         &aud_mst_a_sclk_pre_en,
 809         &aud_mst_b_sclk_pre_en,
 810         &aud_mst_c_sclk_pre_en,
 811         &aud_mst_d_sclk_pre_en,
 812         &aud_mst_e_sclk_pre_en,
 813         &aud_mst_f_sclk_pre_en,
 814         &aud_mst_a_sclk_div,
 815         &aud_mst_b_sclk_div,
 816         &aud_mst_c_sclk_div,
 817         &aud_mst_d_sclk_div,
 818         &aud_mst_e_sclk_div,
 819         &aud_mst_f_sclk_div,
 820         &aud_mst_a_sclk_post_en,
 821         &aud_mst_b_sclk_post_en,
 822         &aud_mst_c_sclk_post_en,
 823         &aud_mst_d_sclk_post_en,
 824         &aud_mst_e_sclk_post_en,
 825         &aud_mst_f_sclk_post_en,
 826         &aud_mst_a_sclk,
 827         &aud_mst_b_sclk,
 828         &aud_mst_c_sclk,
 829         &aud_mst_d_sclk,
 830         &aud_mst_e_sclk,
 831         &aud_mst_f_sclk,
 832         &aud_mst_a_lrclk_div,
 833         &aud_mst_b_lrclk_div,
 834         &aud_mst_c_lrclk_div,
 835         &aud_mst_d_lrclk_div,
 836         &aud_mst_e_lrclk_div,
 837         &aud_mst_f_lrclk_div,
 838         &aud_mst_a_lrclk,
 839         &aud_mst_b_lrclk,
 840         &aud_mst_c_lrclk,
 841         &aud_mst_d_lrclk,
 842         &aud_mst_e_lrclk,
 843         &aud_mst_f_lrclk,
 844         &aud_tdmin_a_sclk_sel,
 845         &aud_tdmin_b_sclk_sel,
 846         &aud_tdmin_c_sclk_sel,
 847         &aud_tdmin_lb_sclk_sel,
 848         &aud_tdmout_a_sclk_sel,
 849         &aud_tdmout_b_sclk_sel,
 850         &aud_tdmout_c_sclk_sel,
 851         &aud_tdmin_a_sclk_pre_en,
 852         &aud_tdmin_b_sclk_pre_en,
 853         &aud_tdmin_c_sclk_pre_en,
 854         &aud_tdmin_lb_sclk_pre_en,
 855         &aud_tdmout_a_sclk_pre_en,
 856         &aud_tdmout_b_sclk_pre_en,
 857         &aud_tdmout_c_sclk_pre_en,
 858         &aud_tdmin_a_sclk_post_en,
 859         &aud_tdmin_b_sclk_post_en,
 860         &aud_tdmin_c_sclk_post_en,
 861         &aud_tdmin_lb_sclk_post_en,
 862         &aud_tdmout_a_sclk_post_en,
 863         &aud_tdmout_b_sclk_post_en,
 864         &aud_tdmout_c_sclk_post_en,
 865         &aud_tdmin_a_sclk,
 866         &aud_tdmin_b_sclk,
 867         &aud_tdmin_c_sclk,
 868         &aud_tdmin_lb_sclk,
 869         &aud_tdmout_a_sclk,
 870         &aud_tdmout_b_sclk,
 871         &aud_tdmout_c_sclk,
 872         &aud_tdmin_a_lrclk,
 873         &aud_tdmin_b_lrclk,
 874         &aud_tdmin_c_lrclk,
 875         &aud_tdmin_lb_lrclk,
 876         &aud_tdmout_a_lrclk,
 877         &aud_tdmout_b_lrclk,
 878         &aud_tdmout_c_lrclk,
 879         &aud_spdifout_b_clk_sel,
 880         &aud_spdifout_b_clk_div,
 881         &aud_spdifout_b_clk,
 882         &aud_tdm_mclk_pad_0,
 883         &aud_tdm_mclk_pad_1,
 884         &aud_tdm_lrclk_pad_0,
 885         &aud_tdm_lrclk_pad_1,
 886         &aud_tdm_lrclk_pad_2,
 887         &aud_tdm_sclk_pad_0,
 888         &aud_tdm_sclk_pad_1,
 889         &aud_tdm_sclk_pad_2,
 890 };
 891
 892 static int devm_clk_get_enable(struct device *dev, char *id)
 893 {
 894         struct clk *clk;
 895         int ret;
 896
 897         clk = devm_clk_get(dev, id);
 898         if (IS_ERR(clk)) {
 899                 ret = PTR_ERR(clk);
 900                 if (ret != -EPROBE_DEFER)
 901                         dev_err(dev, "failed to get %s", id);
 902                 return ret;
 903         }
 904
 905         ret = clk_prepare_enable(clk);
 906         if (ret) {
 907                 dev_err(dev, "failed to enable %s", id);
 908                 return ret;
 909         }
 910
 911         ret = devm_add_action_or_reset(dev,
 912                                        (void(*)(void *))clk_disable_unprepare,
 913                                        clk);
 914         if (ret) {
 915                 dev_err(dev, "failed to add reset action on %s", id);
 916                 return ret;
 917         }
 918
 919         return 0;
 920 }
 921
 922 struct axg_audio_reset_data {
 923         struct reset_controller_dev rstc;
 924         struct regmap *map;
 925         unsigned int offset;
 926 };
 927
 928 static void axg_audio_reset_reg_and_bit(struct axg_audio_reset_data *rst,
 929                                         unsigned long id,
 930                                         unsigned int *reg,
 931                                         unsigned int *bit)
 932 {
 933         unsigned int stride = regmap_get_reg_stride(rst->map);
 934
 935         *reg = (id / (stride * BITS_PER_BYTE)) * stride;
 936         *reg += rst->offset;
 937         *bit = id % (stride * BITS_PER_BYTE);
 938 }
 939
 940 static int axg_audio_reset_update(struct reset_controller_dev *rcdev,
 941                                 unsigned long id, bool assert)
 942 {
 943         struct axg_audio_reset_data *rst =
 944                 container_of(rcdev, struct axg_audio_reset_data, rstc);
 945         unsigned int offset, bit;
 946
 947         axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
 948
 949         regmap_update_bits(rst->map, offset, BIT(bit),
 950                         assert ? BIT(bit) : 0);
 951
 952         return 0;
 953 }
 954
 955 static int axg_audio_reset_status(struct reset_controller_dev *rcdev,
 956                                 unsigned long id)
 957 {
 958         struct axg_audio_reset_data *rst =
 959                 container_of(rcdev, struct axg_audio_reset_data, rstc);
 960         unsigned int val, offset, bit;
 961
 962         axg_audio_reset_reg_and_bit(rst, id, &offset, &bit);
 963
 964         regmap_read(rst->map, offset, &val);
 965
 966         return !!(val & BIT(bit));
 967 }
 968
 969 static int axg_audio_reset_assert(struct reset_controller_dev *rcdev,
 970                                 unsigned long id)
 971 {
 972         return axg_audio_reset_update(rcdev, id, true);
 973 }
 974
 975 static int axg_audio_reset_deassert(struct reset_controller_dev *rcdev,
 976                                 unsigned long id)
 977 {
 978         return axg_audio_reset_update(rcdev, id, false);
 979 }
 980
 981 static int axg_audio_reset_toggle(struct reset_controller_dev *rcdev,
 982                                 unsigned long id)
 983 {
 984         int ret;
 985
 986         ret = axg_audio_reset_assert(rcdev, id);
 987         if (ret)
 988                 return ret;
 989
 990         return axg_audio_reset_deassert(rcdev, id);
 991 }
 992
 993 static const struct reset_control_ops axg_audio_rstc_ops = {
 994         .assert = axg_audio_reset_assert,
 995         .deassert = axg_audio_reset_deassert,
 996         .reset = axg_audio_reset_toggle,
 997         .status = axg_audio_reset_status,
 998 };
 999
1000 static const struct regmap_config axg_audio_regmap_cfg = {
1001         .reg_bits       = 32,
1002         .val_bits       = 32,
1003         .reg_stride     = 4,
1004         .max_register   = AUDIO_CLK_PDMIN_CTRL1,
1005 };
1006
1007 struct audioclk_data {
1008         struct clk_hw_onecell_data *hw_onecell_data;
1009         unsigned int reset_offset;
1010         unsigned int reset_num;
1011 };
1012
1013 static int axg_audio_clkc_probe(struct platform_device *pdev)
1014 {
1015         struct device *dev = &pdev->dev;
1016         const struct audioclk_data *data;
1017         struct axg_audio_reset_data *rst;
1018         struct regmap *map;
1019         struct resource *res;
1020         void __iomem *regs;
1021         struct clk_hw *hw;
1022         int ret, i;
1023
1024         data = of_device_get_match_data(dev);
1025         if (!data)
1026                 return -EINVAL;
1027
1028         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1029         regs = devm_ioremap_resource(dev, res);
1030         if (IS_ERR(regs))
1031                 return PTR_ERR(regs);
1032
1033         map = devm_regmap_init_mmio(dev, regs, &axg_audio_regmap_cfg);
1034         if (IS_ERR(map)) {
1035                 dev_err(dev, "failed to init regmap: %ld\n", PTR_ERR(map));
1036                 return PTR_ERR(map);
1037         }
1038
1039         /* Get the mandatory peripheral clock */
1040         ret = devm_clk_get_enable(dev, "pclk");
1041         if (ret)
1042                 return ret;
1043
1044         ret = device_reset(dev);
1045         if (ret) {
1046                 dev_err(dev, "failed to reset device\n");
1047                 return ret;
1048         }
1049
1050         /* Populate regmap for the regmap backed clocks */
1051         for (i = 0; i < ARRAY_SIZE(aud_clk_regmaps); i++)
1052                 aud_clk_regmaps[i]->map = map;
1053
1054         /* Take care to skip the registered input clocks */
1055         for (i = AUD_CLKID_DDR_ARB; i < data->hw_onecell_data->num; i++) {
1056                 hw = data->hw_onecell_data->hws[i];
1057                 /* array might be sparse */
1058                 if (!hw)
1059                         continue;
1060
1061                 ret = devm_clk_hw_register(dev, hw);
1062                 if (ret) {
1063                         dev_err(dev, "failed to register clock %s\n",
1064                                 hw->init->name);
1065                         return ret;
1066                 }
1067         }
1068
1069         ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
1070                                         data->hw_onecell_data);
1071         if (ret)
1072                 return ret;
1073
1074         /* Stop here if there is no reset */
1075         if (!data->reset_num)
1076                 return 0;
1077
1078         rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
1079         if (!rst)
1080                 return -ENOMEM;
1081
1082         rst->map = map;
1083         rst->offset = data->reset_offset;
1084         rst->rstc.nr_resets = data->reset_num;
1085         rst->rstc.ops = &axg_audio_rstc_ops;
1086         rst->rstc.of_node = dev->of_node;
1087         rst->rstc.owner = THIS_MODULE;
1088
1089         return devm_reset_controller_register(dev, &rst->rstc);
1090 }
1091
1092 static const struct audioclk_data axg_audioclk_data = {
1093         .hw_onecell_data = &axg_audio_hw_onecell_data,
1094 };
1095
1096 static const struct audioclk_data g12a_audioclk_data = {
1097         .hw_onecell_data = &g12a_audio_hw_onecell_data,
1098         .reset_offset = AUDIO_SW_RESET,
1099         .reset_num = 26,
1100 };
1101
1102 static const struct of_device_id clkc_match_table[] = {
1103         {
1104                 .compatible = "amlogic,axg-audio-clkc",
1105                 .data = &axg_audioclk_data
1106         }, {
1107                 .compatible = "amlogic,g12a-audio-clkc",
1108                 .data = &g12a_audioclk_data
1109         }, {}
1110 };
1111 MODULE_DEVICE_TABLE(of, clkc_match_table);
1112
1113 static struct platform_driver axg_audio_driver = {
1114         .probe          = axg_audio_clkc_probe,
1115         .driver         = {
1116                 .name   = "axg-audio-clkc",
1117                 .of_match_table = clkc_match_table,
1118         },
1119 };
1120 module_platform_driver(axg_audio_driver);
1121
1122 MODULE_DESCRIPTION("Amlogic AXG/G12A Audio Clock driver");
1123 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
1124 MODULE_LICENSE("GPL v2");