2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: James Liao <jamesjj.liao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef __DRV_CLK_MTK_H
16 #define __DRV_CLK_MTK_H
18 #include <linux/regmap.h>
19 #include <linux/bitops.h>
20 #include <linux/clk-provider.h>
23 struct clk_onecell_data;
25 #define MAX_MUX_GATE_BIT 31
26 #define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
28 #define MHZ (1000 * 1000)
30 struct mtk_fixed_clk {
37 #define FIXED_CLK(_id, _name, _parent, _rate) { \
44 void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
45 int num, struct clk_onecell_data *clk_data);
47 struct mtk_fixed_factor {
50 const char *parent_name;
55 #define FACTOR(_id, _name, _parent, _mult, _div) { \
58 .parent_name = _parent, \
63 void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
64 int num, struct clk_onecell_data *clk_data);
66 struct mtk_composite {
69 const char * const *parent_names;
77 signed char mux_shift;
78 signed char mux_width;
79 signed char gate_shift;
81 signed char divider_shift;
82 signed char divider_width;
86 signed char num_parents;
89 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \
90 _width, _gate, _flags, _muxflags) { \
94 .mux_shift = _shift, \
95 .mux_width = _width, \
97 .gate_shift = _gate, \
98 .divider_shift = -1, \
99 .parent_names = _parents, \
100 .num_parents = ARRAY_SIZE(_parents), \
102 .mux_flags = _muxflags, \
106 * In case the rate change propagation to parent clocks is undesirable,
107 * this macro allows to specify the clock flags manually.
109 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
111 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \
112 _shift, _width, _gate, _flags, 0)
115 * Unless necessary, all MUX_GATE clocks propagate rate changes to their
116 * parent clock by default.
118 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
119 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
120 _gate, CLK_SET_RATE_PARENT)
122 #define MUX(_id, _name, _parents, _reg, _shift, _width) \
123 MUX_FLAGS(_id, _name, _parents, _reg, \
124 _shift, _width, CLK_SET_RATE_PARENT)
126 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \
130 .mux_shift = _shift, \
131 .mux_width = _width, \
133 .divider_shift = -1, \
134 .parent_names = _parents, \
135 .num_parents = ARRAY_SIZE(_parents), \
139 #define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
140 _div_width, _div_shift) { \
144 .divider_reg = _div_reg, \
145 .divider_shift = _div_shift, \
146 .divider_width = _div_width, \
147 .gate_reg = _gate_reg, \
148 .gate_shift = _gate_shift, \
153 struct clk *mtk_clk_register_composite(const struct mtk_composite *mc,
154 void __iomem *base, spinlock_t *lock);
156 void mtk_clk_register_composites(const struct mtk_composite *mcs,
157 int num, void __iomem *base, spinlock_t *lock,
158 struct clk_onecell_data *clk_data);
160 struct mtk_gate_regs {
169 const char *parent_name;
170 const struct mtk_gate_regs *regs;
172 const struct clk_ops *ops;
176 int mtk_clk_register_gates(struct device_node *node,
177 const struct mtk_gate *clks, int num,
178 struct clk_onecell_data *clk_data);
180 struct mtk_clk_divider {
183 const char *parent_name;
187 unsigned char div_shift;
188 unsigned char div_width;
189 unsigned char clk_divider_flags;
190 const struct clk_div_table *clk_div_table;
193 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
196 .parent_name = _parent, \
198 .div_shift = _shift, \
199 .div_width = _width, \
202 void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
203 int num, void __iomem *base, spinlock_t *lock,
204 struct clk_onecell_data *clk_data);
206 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
208 #define HAVE_RST_BAR BIT(0)
209 #define PLL_AO BIT(1)
211 struct mtk_pll_div_table {
216 struct mtk_pll_data {
224 uint32_t tuner_en_reg;
225 uint8_t tuner_en_bit;
228 const struct clk_ops *ops;
236 uint32_t pcw_chg_reg;
237 const struct mtk_pll_div_table *div_table;
238 const char *parent_name;
241 void mtk_clk_register_plls(struct device_node *node,
242 const struct mtk_pll_data *plls, int num_plls,
243 struct clk_onecell_data *clk_data);
245 struct clk *mtk_clk_register_ref2usb_tx(const char *name,
246 const char *parent_name, void __iomem *reg);
248 void mtk_register_reset_controller(struct device_node *np,
249 unsigned int num_regs, int regofs);
251 #endif /* __DRV_CLK_MTK_H */