drivers/clk/mediatek/clk-mt8516.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2019 MediaTek Inc.
   4  * Author: James Liao <jamesjj.liao@mediatek.com>
   5  *         Fabien Parent <fparent@baylibre.com>
   6  */
   7
   8 #include <linux/delay.h>
   9 #include <linux/of.h>
  10 #include <linux/of_address.h>
  11 #include <linux/slab.h>
  12 #include <linux/mfd/syscon.h>
  13
  14 #include "clk-mtk.h"
  15 #include "clk-gate.h"
  16
  17 #include <dt-bindings/clock/mt8516-clk.h>
  18
  19 static DEFINE_SPINLOCK(mt8516_clk_lock);
  20
  21 static const struct mtk_fixed_clk fixed_clks[] __initconst = {
  22         FIXED_CLK(CLK_TOP_CLK_NULL, "clk_null", NULL, 0),
  23         FIXED_CLK(CLK_TOP_I2S_INFRA_BCK, "i2s_infra_bck", "clk_null", 26000000),
  24         FIXED_CLK(CLK_TOP_MEMPLL, "mempll", "clk26m", 800000000),
  25 };
  26
  27 static const struct mtk_fixed_factor top_divs[] __initconst = {
  28         FACTOR(CLK_TOP_DMPLL, "dmpll_ck", "mempll", 1, 1),
  29         FACTOR(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2),
  30         FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
  31         FACTOR(CLK_TOP_MAINPLL_D8, "mainpll_d8", "mainpll", 1, 8),
  32         FACTOR(CLK_TOP_MAINPLL_D16, "mainpll_d16", "mainpll", 1, 16),
  33         FACTOR(CLK_TOP_MAINPLL_D11, "mainpll_d11", "mainpll", 1, 11),
  34         FACTOR(CLK_TOP_MAINPLL_D22, "mainpll_d22", "mainpll", 1, 22),
  35         FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
  36         FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
  37         FACTOR(CLK_TOP_MAINPLL_D12, "mainpll_d12", "mainpll", 1, 12),
  38         FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
  39         FACTOR(CLK_TOP_MAINPLL_D10, "mainpll_d10", "mainpll", 1, 10),
  40         FACTOR(CLK_TOP_MAINPLL_D20, "mainpll_d20", "mainpll", 1, 20),
  41         FACTOR(CLK_TOP_MAINPLL_D40, "mainpll_d40", "mainpll", 1, 40),
  42         FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
  43         FACTOR(CLK_TOP_MAINPLL_D14, "mainpll_d14", "mainpll", 1, 14),
  44         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
  45         FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
  46         FACTOR(CLK_TOP_UNIVPLL_D8, "univpll_d8", "univpll", 1, 8),
  47         FACTOR(CLK_TOP_UNIVPLL_D16, "univpll_d16", "univpll", 1, 16),
  48         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
  49         FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
  50         FACTOR(CLK_TOP_UNIVPLL_D12, "univpll_d12", "univpll", 1, 12),
  51         FACTOR(CLK_TOP_UNIVPLL_D24, "univpll_d24", "univpll", 1, 24),
  52         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
  53         FACTOR(CLK_TOP_UNIVPLL_D20, "univpll_d20", "univpll", 1, 20),
  54         FACTOR(CLK_TOP_MMPLL380M, "mmpll380m", "mmpll", 1, 1),
  55         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  56         FACTOR(CLK_TOP_MMPLL_200M, "mmpll_200m", "mmpll", 1, 3),
  57         FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
  58         FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
  59         FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
  60         FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "rg_apll1_d2_en", 1, 2),
  61         FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "rg_apll1_d4_en", 1, 2),
  62         FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1, 1),
  63         FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1, 2),
  64         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "rg_apll2_d2_en", 1, 2),
  65         FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "rg_apll2_d4_en", 1, 2),
  66         FACTOR(CLK_TOP_CLK26M, "clk26m_ck", "clk26m", 1, 1),
  67         FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "clk26m", 1, 2),
  68         FACTOR(CLK_TOP_AHB_INFRA_D2, "ahb_infra_d2", "ahb_infra_sel", 1, 2),
  69         FACTOR(CLK_TOP_NFI1X, "nfi1x_ck", "nfi2x_pad_sel", 1, 2),
  70         FACTOR(CLK_TOP_ETH_D2, "eth_d2_ck", "eth_sel", 1, 2),
  71 };
  72
  73 static const char * const uart0_parents[] __initconst = {
  74         "clk26m_ck",
  75         "univpll_d24"
  76 };
  77
  78 static const char * const ahb_infra_parents[] __initconst = {
  79         "clk_null",
  80         "clk26m_ck",
  81         "mainpll_d11",
  82         "clk_null",
  83         "mainpll_d12",
  84         "clk_null",
  85         "clk_null",
  86         "clk_null",
  87         "clk_null",
  88         "clk_null",
  89         "clk_null",
  90         "clk_null",
  91         "mainpll_d10"
  92 };
  93
  94 static const char * const msdc0_parents[] __initconst = {
  95         "clk26m_ck",
  96         "univpll_d6",
  97         "mainpll_d8",
  98         "univpll_d8",
  99         "mainpll_d16",
 100         "mmpll_200m",
 101         "mainpll_d12",
 102         "mmpll_d2"
 103 };
 104
 105 static const char * const uart1_parents[] __initconst = {
 106         "clk26m_ck",
 107         "univpll_d24"
 108 };
 109
 110 static const char * const msdc1_parents[] __initconst = {
 111         "clk26m_ck",
 112         "univpll_d6",
 113         "mainpll_d8",
 114         "univpll_d8",
 115         "mainpll_d16",
 116         "mmpll_200m",
 117         "mainpll_d12",
 118         "mmpll_d2"
 119 };
 120
 121 static const char * const pmicspi_parents[] __initconst = {
 122         "univpll_d20",
 123         "usb_phy48m_ck",
 124         "univpll_d16",
 125         "clk26m_ck"
 126 };
 127
 128 static const char * const qaxi_aud26m_parents[] __initconst = {
 129         "clk26m_ck",
 130         "ahb_infra_sel"
 131 };
 132
 133 static const char * const aud_intbus_parents[] __initconst = {
 134         "clk_null",
 135         "clk26m_ck",
 136         "mainpll_d22",
 137         "clk_null",
 138         "mainpll_d11"
 139 };
 140
 141 static const char * const nfi2x_pad_parents[] __initconst = {
 142         "clk_null",
 143         "clk_null",
 144         "clk_null",
 145         "clk_null",
 146         "clk_null",
 147         "clk_null",
 148         "clk_null",
 149         "clk_null",
 150         "clk26m_ck",
 151         "clk_null",
 152         "clk_null",
 153         "clk_null",
 154         "clk_null",
 155         "clk_null",
 156         "clk_null",
 157         "clk_null",
 158         "clk_null",
 159         "mainpll_d12",
 160         "mainpll_d8",
 161         "clk_null",
 162         "mainpll_d6",
 163         "clk_null",
 164         "clk_null",
 165         "clk_null",
 166         "clk_null",
 167         "clk_null",
 168         "clk_null",
 169         "clk_null",
 170         "clk_null",
 171         "clk_null",
 172         "clk_null",
 173         "clk_null",
 174         "mainpll_d4",
 175         "clk_null",
 176         "clk_null",
 177         "clk_null",
 178         "clk_null",
 179         "clk_null",
 180         "clk_null",
 181         "clk_null",
 182         "clk_null",
 183         "clk_null",
 184         "clk_null",
 185         "clk_null",
 186         "clk_null",
 187         "clk_null",
 188         "clk_null",
 189         "clk_null",
 190         "clk_null",
 191         "clk_null",
 192         "clk_null",
 193         "clk_null",
 194         "clk_null",
 195         "clk_null",
 196         "clk_null",
 197         "clk_null",
 198         "clk_null",
 199         "clk_null",
 200         "clk_null",
 201         "clk_null",
 202         "clk_null",
 203         "clk_null",
 204         "clk_null",
 205         "clk_null",
 206         "clk_null",
 207         "clk_null",
 208         "clk_null",
 209         "clk_null",
 210         "clk_null",
 211         "clk_null",
 212         "clk_null",
 213         "clk_null",
 214         "clk_null",
 215         "clk_null",
 216         "clk_null",
 217         "clk_null",
 218         "clk_null",
 219         "clk_null",
 220         "clk_null",
 221         "clk_null",
 222         "clk_null",
 223         "mainpll_d10",
 224         "mainpll_d7",
 225         "clk_null",
 226         "mainpll_d5"
 227 };
 228
 229 static const char * const nfi1x_pad_parents[] __initconst = {
 230         "ahb_infra_sel",
 231         "nfi1x_ck"
 232 };
 233
 234 static const char * const ddrphycfg_parents[] __initconst = {
 235         "clk26m_ck",
 236         "mainpll_d16"
 237 };
 238
 239 static const char * const usb_78m_parents[] __initconst = {
 240         "clk_null",
 241         "clk26m_ck",
 242         "univpll_d16",
 243         "clk_null",
 244         "mainpll_d20"
 245 };
 246
 247 static const char * const spinor_parents[] __initconst = {
 248         "clk26m_d2",
 249         "clk26m_ck",
 250         "mainpll_d40",
 251         "univpll_d24",
 252         "univpll_d20",
 253         "mainpll_d20",
 254         "mainpll_d16",
 255         "univpll_d12"
 256 };
 257
 258 static const char * const msdc2_parents[] __initconst = {
 259         "clk26m_ck",
 260         "univpll_d6",
 261         "mainpll_d8",
 262         "univpll_d8",
 263         "mainpll_d16",
 264         "mmpll_200m",
 265         "mainpll_d12",
 266         "mmpll_d2"
 267 };
 268
 269 static const char * const eth_parents[] __initconst = {
 270         "clk26m_ck",
 271         "mainpll_d40",
 272         "univpll_d24",
 273         "univpll_d20",
 274         "mainpll_d20"
 275 };
 276
 277 static const char * const aud1_parents[] __initconst = {
 278         "clk26m_ck",
 279         "apll1_ck"
 280 };
 281
 282 static const char * const aud2_parents[] __initconst = {
 283         "clk26m_ck",
 284         "apll2_ck"
 285 };
 286
 287 static const char * const aud_engen1_parents[] __initconst = {
 288         "clk26m_ck",
 289         "rg_apll1_d2_en",
 290         "rg_apll1_d4_en",
 291         "rg_apll1_d8_en"
 292 };
 293
 294 static const char * const aud_engen2_parents[] __initconst = {
 295         "clk26m_ck",
 296         "rg_apll2_d2_en",
 297         "rg_apll2_d4_en",
 298         "rg_apll2_d8_en"
 299 };
 300
 301 static const char * const i2c_parents[] __initconst = {
 302         "clk26m_ck",
 303         "univpll_d20",
 304         "univpll_d16",
 305         "univpll_d12"
 306 };
 307
 308 static const char * const aud_i2s0_m_parents[] __initconst = {
 309         "rg_aud1",
 310         "rg_aud2"
 311 };
 312
 313 static const char * const pwm_parents[] __initconst = {
 314         "clk26m_ck",
 315         "univpll_d12"
 316 };
 317
 318 static const char * const spi_parents[] __initconst = {
 319         "clk26m_ck",
 320         "univpll_d12",
 321         "univpll_d8",
 322         "univpll_d6"
 323 };
 324
 325 static const char * const aud_spdifin_parents[] __initconst = {
 326         "clk26m_ck",
 327         "univpll_d2"
 328 };
 329
 330 static const char * const uart2_parents[] __initconst = {
 331         "clk26m_ck",
 332         "univpll_d24"
 333 };
 334
 335 static const char * const bsi_parents[] __initconst = {
 336         "clk26m_ck",
 337         "mainpll_d10",
 338         "mainpll_d12",
 339         "mainpll_d20"
 340 };
 341
 342 static const char * const dbg_atclk_parents[] __initconst = {
 343         "clk_null",
 344         "clk26m_ck",
 345         "mainpll_d5",
 346         "clk_null",
 347         "univpll_d5"
 348 };
 349
 350 static const char * const csw_nfiecc_parents[] __initconst = {
 351         "clk_null",
 352         "mainpll_d7",
 353         "mainpll_d6",
 354         "clk_null",
 355         "mainpll_d5"
 356 };
 357
 358 static const char * const nfiecc_parents[] __initconst = {
 359         "clk_null",
 360         "nfi2x_pad_sel",
 361         "mainpll_d4",
 362         "clk_null",
 363         "csw_nfiecc_sel"
 364 };
 365
 366 static struct mtk_composite top_muxes[] __initdata = {
 367         /* CLK_MUX_SEL0 */
 368         MUX(CLK_TOP_UART0_SEL, "uart0_sel", uart0_parents,
 369                 0x000, 0, 1),
 370         MUX(CLK_TOP_AHB_INFRA_SEL, "ahb_infra_sel", ahb_infra_parents,
 371                 0x000, 4, 4),
 372         MUX(CLK_TOP_MSDC0_SEL, "msdc0_sel", msdc0_parents,
 373                 0x000, 11, 3),
 374         MUX(CLK_TOP_UART1_SEL, "uart1_sel", uart1_parents,
 375                 0x000, 19, 1),
 376         MUX(CLK_TOP_MSDC1_SEL, "msdc1_sel", msdc1_parents,
 377                 0x000, 20, 3),
 378         MUX(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
 379                 0x000, 24, 2),
 380         MUX(CLK_TOP_QAXI_AUD26M_SEL, "qaxi_aud26m_sel", qaxi_aud26m_parents,
 381                 0x000, 26, 1),
 382         MUX(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 383                 0x000, 27, 3),
 384         /* CLK_MUX_SEL1 */
 385         MUX(CLK_TOP_NFI2X_PAD_SEL, "nfi2x_pad_sel", nfi2x_pad_parents,
 386                 0x004, 0, 7),
 387         MUX(CLK_TOP_NFI1X_PAD_SEL, "nfi1x_pad_sel", nfi1x_pad_parents,
 388                 0x004, 7, 1),
 389         MUX(CLK_TOP_USB_78M_SEL, "usb_78m_sel", usb_78m_parents,
 390                 0x004, 20, 3),
 391         /* CLK_MUX_SEL8 */
 392         MUX(CLK_TOP_SPINOR_SEL, "spinor_sel", spinor_parents,
 393                 0x040, 0, 3),
 394         MUX(CLK_TOP_MSDC2_SEL, "msdc2_sel", msdc2_parents,
 395                 0x040, 3, 3),
 396         MUX(CLK_TOP_ETH_SEL, "eth_sel", eth_parents,
 397                 0x040, 6, 3),
 398         MUX(CLK_TOP_AUD1_SEL, "aud1_sel", aud1_parents,
 399                 0x040, 22, 1),
 400         MUX(CLK_TOP_AUD2_SEL, "aud2_sel", aud2_parents,
 401                 0x040, 23, 1),
 402         MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
 403                 0x040, 24, 2),
 404         MUX(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel", aud_engen2_parents,
 405                 0x040, 26, 2),
 406         MUX(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents,
 407                 0x040, 28, 2),
 408         /* CLK_SEL_9 */
 409         MUX(CLK_TOP_AUD_I2S0_M_SEL, "aud_i2s0_m_sel", aud_i2s0_m_parents,
 410                 0x044, 12, 1),
 411         MUX(CLK_TOP_AUD_I2S1_M_SEL, "aud_i2s1_m_sel", aud_i2s0_m_parents,
 412                 0x044, 13, 1),
 413         MUX(CLK_TOP_AUD_I2S2_M_SEL, "aud_i2s2_m_sel", aud_i2s0_m_parents,
 414                 0x044, 14, 1),
 415         MUX(CLK_TOP_AUD_I2S3_M_SEL, "aud_i2s3_m_sel", aud_i2s0_m_parents,
 416                 0x044, 15, 1),
 417         MUX(CLK_TOP_AUD_I2S4_M_SEL, "aud_i2s4_m_sel", aud_i2s0_m_parents,
 418                 0x044, 16, 1),
 419         MUX(CLK_TOP_AUD_I2S5_M_SEL, "aud_i2s5_m_sel", aud_i2s0_m_parents,
 420                 0x044, 17, 1),
 421         MUX(CLK_TOP_AUD_SPDIF_B_SEL, "aud_spdif_b_sel", aud_i2s0_m_parents,
 422                 0x044, 18, 1),
 423         /* CLK_MUX_SEL13 */
 424         MUX(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
 425                 0x07c, 0, 1),
 426         MUX(CLK_TOP_SPI_SEL, "spi_sel", spi_parents,
 427                 0x07c, 1, 2),
 428         MUX(CLK_TOP_AUD_SPDIFIN_SEL, "aud_spdifin_sel", aud_spdifin_parents,
 429                 0x07c, 3, 1),
 430         MUX(CLK_TOP_UART2_SEL, "uart2_sel", uart2_parents,
 431                 0x07c, 4, 1),
 432         MUX(CLK_TOP_BSI_SEL, "bsi_sel", bsi_parents,
 433                 0x07c, 5, 2),
 434         MUX(CLK_TOP_DBG_ATCLK_SEL, "dbg_atclk_sel", dbg_atclk_parents,
 435                 0x07c, 7, 3),
 436         MUX(CLK_TOP_CSW_NFIECC_SEL, "csw_nfiecc_sel", csw_nfiecc_parents,
 437                 0x07c, 10, 3),
 438         MUX(CLK_TOP_NFIECC_SEL, "nfiecc_sel", nfiecc_parents,
 439                 0x07c, 13, 3),
 440 };
 441
 442 static const char * const ifr_mux1_parents[] __initconst = {
 443         "clk26m_ck",
 444         "armpll",
 445         "univpll",
 446         "mainpll_d2"
 447 };
 448
 449 static const char * const ifr_eth_25m_parents[] __initconst = {
 450         "eth_d2_ck",
 451         "rg_eth"
 452 };
 453
 454 static const char * const ifr_i2c0_parents[] __initconst = {
 455         "ahb_infra_d2",
 456         "rg_i2c"
 457 };
 458
 459 static const struct mtk_composite ifr_muxes[] __initconst = {
 460         MUX(CLK_IFR_MUX1_SEL, "ifr_mux1_sel", ifr_mux1_parents, 0x000,
 461                 2, 2),
 462         MUX(CLK_IFR_ETH_25M_SEL, "ifr_eth_25m_sel", ifr_eth_25m_parents, 0x080,
 463                 0, 1),
 464         MUX(CLK_IFR_I2C0_SEL, "ifr_i2c0_sel", ifr_i2c0_parents, 0x080,
 465                 1, 1),
 466         MUX(CLK_IFR_I2C1_SEL, "ifr_i2c1_sel", ifr_i2c0_parents, 0x080,
 467                 2, 1),
 468         MUX(CLK_IFR_I2C2_SEL, "ifr_i2c2_sel", ifr_i2c0_parents, 0x080,
 469                 3, 1),
 470 };
 471
 472 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) {    \
 473                 .id = _id,                                      \
 474                 .name = _name,                                  \
 475                 .parent_name = _parent,                         \
 476                 .div_reg = _reg,                                \
 477                 .div_shift = _shift,                            \
 478                 .div_width = _width,                            \
 479 }
 480
 481 static const struct mtk_clk_divider top_adj_divs[] = {
 482         DIV_ADJ(CLK_TOP_APLL12_CK_DIV0, "apll12_ck_div0", "aud_i2s0_m_sel",
 483                 0x0048, 0, 8),
 484         DIV_ADJ(CLK_TOP_APLL12_CK_DIV1, "apll12_ck_div1", "aud_i2s1_m_sel",
 485                 0x0048, 8, 8),
 486         DIV_ADJ(CLK_TOP_APLL12_CK_DIV2, "apll12_ck_div2", "aud_i2s2_m_sel",
 487                 0x0048, 16, 8),
 488         DIV_ADJ(CLK_TOP_APLL12_CK_DIV3, "apll12_ck_div3", "aud_i2s3_m_sel",
 489                 0x0048, 24, 8),
 490         DIV_ADJ(CLK_TOP_APLL12_CK_DIV4, "apll12_ck_div4", "aud_i2s4_m_sel",
 491                 0x004c, 0, 8),
 492         DIV_ADJ(CLK_TOP_APLL12_CK_DIV4B, "apll12_ck_div4b", "apll12_div4",
 493                 0x004c, 8, 8),
 494         DIV_ADJ(CLK_TOP_APLL12_CK_DIV5, "apll12_ck_div5", "aud_i2s5_m_sel",
 495                 0x004c, 16, 8),
 496         DIV_ADJ(CLK_TOP_APLL12_CK_DIV5B, "apll12_ck_div5b", "apll12_div5",
 497                 0x004c, 24, 8),
 498         DIV_ADJ(CLK_TOP_APLL12_CK_DIV6, "apll12_ck_div6", "aud_spdif_b_sel",
 499                 0x0078, 0, 8),
 500 };
 501
 502 static const struct mtk_gate_regs top1_cg_regs = {
 503         .set_ofs = 0x54,
 504         .clr_ofs = 0x84,
 505         .sta_ofs = 0x24,
 506 };
 507
 508 static const struct mtk_gate_regs top2_cg_regs = {
 509         .set_ofs = 0x6c,
 510         .clr_ofs = 0x9c,
 511         .sta_ofs = 0x3c,
 512 };
 513
 514 static const struct mtk_gate_regs top3_cg_regs = {
 515         .set_ofs = 0xa0,
 516         .clr_ofs = 0xb0,
 517         .sta_ofs = 0x70,
 518 };
 519
 520 static const struct mtk_gate_regs top4_cg_regs = {
 521         .set_ofs = 0xa4,
 522         .clr_ofs = 0xb4,
 523         .sta_ofs = 0x74,
 524 };
 525
 526 static const struct mtk_gate_regs top5_cg_regs = {
 527         .set_ofs = 0x44,
 528         .clr_ofs = 0x44,
 529         .sta_ofs = 0x44,
 530 };
 531
 532 #define GATE_TOP1(_id, _name, _parent, _shift) {        \
 533                 .id = _id,                              \
 534                 .name = _name,                          \
 535                 .parent_name = _parent,                 \
 536                 .regs = &top1_cg_regs,                  \
 537                 .shift = _shift,                        \
 538                 .ops = &mtk_clk_gate_ops_setclr,        \
 539         }
 540
 541 #define GATE_TOP2(_id, _name, _parent, _shift) {        \
 542                 .id = _id,                              \
 543                 .name = _name,                          \
 544                 .parent_name = _parent,                 \
 545                 .regs = &top2_cg_regs,                  \
 546                 .shift = _shift,                        \
 547                 .ops = &mtk_clk_gate_ops_setclr,        \
 548         }
 549
 550 #define GATE_TOP2_I(_id, _name, _parent, _shift) {      \
 551                 .id = _id,                              \
 552                 .name = _name,                          \
 553                 .parent_name = _parent,                 \
 554                 .regs = &top2_cg_regs,                  \
 555                 .shift = _shift,                        \
 556                 .ops = &mtk_clk_gate_ops_setclr_inv,    \
 557         }
 558
 559 #define GATE_TOP3(_id, _name, _parent, _shift) {        \
 560                 .id = _id,                              \
 561                 .name = _name,                          \
 562                 .parent_name = _parent,                 \
 563                 .regs = &top3_cg_regs,                  \
 564                 .shift = _shift,                        \
 565                 .ops = &mtk_clk_gate_ops_setclr,        \
 566         }
 567
 568 #define GATE_TOP4_I(_id, _name, _parent, _shift) {      \
 569                 .id = _id,                              \
 570                 .name = _name,                          \
 571                 .parent_name = _parent,                 \
 572                 .regs = &top4_cg_regs,                  \
 573                 .shift = _shift,                        \
 574                 .ops = &mtk_clk_gate_ops_setclr_inv,    \
 575         }
 576
 577 #define GATE_TOP5(_id, _name, _parent, _shift) {        \
 578                 .id = _id,                              \
 579                 .name = _name,                          \
 580                 .parent_name = _parent,                 \
 581                 .regs = &top5_cg_regs,                  \
 582                 .shift = _shift,                        \
 583                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 584         }
 585
 586 static const struct mtk_gate top_clks[] __initconst = {
 587         /* TOP1 */
 588         GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
 589         GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
 590         GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
 591         GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
 592         GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
 593         GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
 594         GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
 595         GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
 596         GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
 597         GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
 598         GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
 599         GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
 600         GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
 601         GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
 602         GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
 603         GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
 604         GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
 605         GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
 606         GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
 607         GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
 608         GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
 609         GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
 610         GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
 611         GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
 612         GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
 613         GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
 614         GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
 615         GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
 616         GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
 617         GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),
 618         /* TOP2 */
 619         GATE_TOP2(CLK_TOP_MSDC2, "msdc2", "ahb_infra_sel", 0),
 620         GATE_TOP2(CLK_TOP_RBIST, "rbist", "univpll_d12", 1),
 621         GATE_TOP2(CLK_TOP_NFI_BUS, "nfi_bus", "ahb_infra_sel", 2),
 622         GATE_TOP2(CLK_TOP_GCE, "gce", "ahb_infra_sel", 4),
 623         GATE_TOP2(CLK_TOP_TRNG, "trng", "ahb_infra_sel", 5),
 624         GATE_TOP2(CLK_TOP_SEJ_13M, "sej_13m", "clk26m_ck", 6),
 625         GATE_TOP2(CLK_TOP_AES, "aes", "ahb_infra_sel", 7),
 626         GATE_TOP2(CLK_TOP_PWM_B, "pwm_b", "rg_pwm_infra", 8),
 627         GATE_TOP2(CLK_TOP_PWM1_FB, "pwm1_fb", "rg_pwm_infra", 9),
 628         GATE_TOP2(CLK_TOP_PWM2_FB, "pwm2_fb", "rg_pwm_infra", 10),
 629         GATE_TOP2(CLK_TOP_PWM3_FB, "pwm3_fb", "rg_pwm_infra", 11),
 630         GATE_TOP2(CLK_TOP_PWM4_FB, "pwm4_fb", "rg_pwm_infra", 12),
 631         GATE_TOP2(CLK_TOP_PWM5_FB, "pwm5_fb", "rg_pwm_infra", 13),
 632         GATE_TOP2(CLK_TOP_USB_1P, "usb_1p", "usb_78m", 14),
 633         GATE_TOP2(CLK_TOP_FLASHIF_FREERUN, "flashif_freerun", "ahb_infra_sel",
 634                 15),
 635         GATE_TOP2(CLK_TOP_66M_ETH, "eth_66m", "ahb_infra_d2", 19),
 636         GATE_TOP2(CLK_TOP_133M_ETH, "eth_133m", "ahb_infra_sel", 20),
 637         GATE_TOP2(CLK_TOP_FETH_25M, "feth_25m", "ifr_eth_25m_sel", 21),
 638         GATE_TOP2(CLK_TOP_FETH_50M, "feth_50m", "rg_eth", 22),
 639         GATE_TOP2(CLK_TOP_FLASHIF_AXI, "flashif_axi", "ahb_infra_sel", 23),
 640         GATE_TOP2(CLK_TOP_USBIF, "usbif", "ahb_infra_sel", 24),
 641         GATE_TOP2(CLK_TOP_UART2, "uart2", "rg_uart2", 25),
 642         GATE_TOP2(CLK_TOP_BSI, "bsi", "ahb_infra_sel", 26),
 643         GATE_TOP2_I(CLK_TOP_MSDC0_INFRA, "msdc0_infra", "msdc0", 28),
 644         GATE_TOP2_I(CLK_TOP_MSDC1_INFRA, "msdc1_infra", "msdc1", 29),
 645         GATE_TOP2_I(CLK_TOP_MSDC2_INFRA, "msdc2_infra", "rg_msdc2", 30),
 646         GATE_TOP2(CLK_TOP_USB_78M, "usb_78m", "usb_78m_sel", 31),
 647         /* TOP3 */
 648         GATE_TOP3(CLK_TOP_RG_SPINOR, "rg_spinor", "spinor_sel", 0),
 649         GATE_TOP3(CLK_TOP_RG_MSDC2, "rg_msdc2", "msdc2_sel", 1),
 650         GATE_TOP3(CLK_TOP_RG_ETH, "rg_eth", "eth_sel", 2),
 651         GATE_TOP3(CLK_TOP_RG_AUD1, "rg_aud1", "aud1_sel", 8),
 652         GATE_TOP3(CLK_TOP_RG_AUD2, "rg_aud2", "aud2_sel", 9),
 653         GATE_TOP3(CLK_TOP_RG_AUD_ENGEN1, "rg_aud_engen1", "aud_engen1_sel", 10),
 654         GATE_TOP3(CLK_TOP_RG_AUD_ENGEN2, "rg_aud_engen2", "aud_engen2_sel", 11),
 655         GATE_TOP3(CLK_TOP_RG_I2C, "rg_i2c", "i2c_sel", 12),
 656         GATE_TOP3(CLK_TOP_RG_PWM_INFRA, "rg_pwm_infra", "pwm_sel", 13),
 657         GATE_TOP3(CLK_TOP_RG_AUD_SPDIF_IN, "rg_aud_spdif_in", "aud_spdifin_sel",
 658                 14),
 659         GATE_TOP3(CLK_TOP_RG_UART2, "rg_uart2", "uart2_sel", 15),
 660         GATE_TOP3(CLK_TOP_RG_BSI, "rg_bsi", "bsi_sel", 16),
 661         GATE_TOP3(CLK_TOP_RG_DBG_ATCLK, "rg_dbg_atclk", "dbg_atclk_sel", 17),
 662         GATE_TOP3(CLK_TOP_RG_NFIECC, "rg_nfiecc", "nfiecc_sel", 18),
 663         /* TOP4 */
 664         GATE_TOP4_I(CLK_TOP_RG_APLL1_D2_EN, "rg_apll1_d2_en", "apll1_d2", 8),
 665         GATE_TOP4_I(CLK_TOP_RG_APLL1_D4_EN, "rg_apll1_d4_en", "apll1_d4", 9),
 666         GATE_TOP4_I(CLK_TOP_RG_APLL1_D8_EN, "rg_apll1_d8_en", "apll1_d8", 10),
 667         GATE_TOP4_I(CLK_TOP_RG_APLL2_D2_EN, "rg_apll2_d2_en", "apll2_d2", 11),
 668         GATE_TOP4_I(CLK_TOP_RG_APLL2_D4_EN, "rg_apll2_d4_en", "apll2_d4", 12),
 669         GATE_TOP4_I(CLK_TOP_RG_APLL2_D8_EN, "rg_apll2_d8_en", "apll2_d8", 13),
 670         /* TOP5 */
 671         GATE_TOP5(CLK_TOP_APLL12_DIV0, "apll12_div0", "apll12_ck_div0", 0),
 672         GATE_TOP5(CLK_TOP_APLL12_DIV1, "apll12_div1", "apll12_ck_div1", 1),
 673         GATE_TOP5(CLK_TOP_APLL12_DIV2, "apll12_div2", "apll12_ck_div2", 2),
 674         GATE_TOP5(CLK_TOP_APLL12_DIV3, "apll12_div3", "apll12_ck_div3", 3),
 675         GATE_TOP5(CLK_TOP_APLL12_DIV4, "apll12_div4", "apll12_ck_div4", 4),
 676         GATE_TOP5(CLK_TOP_APLL12_DIV4B, "apll12_div4b", "apll12_ck_div4b", 5),
 677         GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
 678         GATE_TOP5(CLK_TOP_APLL12_DIV5B, "apll12_div5b", "apll12_ck_div5b", 7),
 679         GATE_TOP5(CLK_TOP_APLL12_DIV6, "apll12_div6", "apll12_ck_div6", 8),
 680 };
 681
 682 static void __init mtk_topckgen_init(struct device_node *node)
 683 {
 684         struct clk_onecell_data *clk_data;
 685         int r;
 686         void __iomem *base;
 687
 688         base = of_iomap(node, 0);
 689         if (!base) {
 690                 pr_err("%s(): ioremap failed\n", __func__);
 691                 return;
 692         }
 693
 694         clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 695
 696         mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
 697                                     clk_data);
 698         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), clk_data);
 699
 700         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 701         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 702                 &mt8516_clk_lock, clk_data);
 703         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
 704                                 base, &mt8516_clk_lock, clk_data);
 705
 706         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 707         if (r)
 708                 pr_err("%s(): could not register clock provider: %d\n",
 709                         __func__, r);
 710 }
 711 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8516-topckgen", mtk_topckgen_init);
 712
 713 static void __init mtk_infracfg_init(struct device_node *node)
 714 {
 715         struct clk_onecell_data *clk_data;
 716         int r;
 717         void __iomem *base;
 718
 719         base = of_iomap(node, 0);
 720         if (!base) {
 721                 pr_err("%s(): ioremap failed\n", __func__);
 722                 return;
 723         }
 724
 725         clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
 726
 727         mtk_clk_register_composites(ifr_muxes, ARRAY_SIZE(ifr_muxes), base,
 728                 &mt8516_clk_lock, clk_data);
 729
 730         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 731         if (r)
 732                 pr_err("%s(): could not register clock provider: %d\n",
 733                         __func__, r);
 734 }
 735 CLK_OF_DECLARE(mtk_infracfg, "mediatek,mt8516-infracfg", mtk_infracfg_init);
 736
 737 #define MT8516_PLL_FMAX         (1502UL * MHZ)
 738
 739 #define CON0_MT8516_RST_BAR     BIT(27)
 740
 741 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,   \
 742                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 743                         _pcw_shift, _div_table) {                       \
 744                 .id = _id,                                              \
 745                 .name = _name,                                          \
 746                 .reg = _reg,                                            \
 747                 .pwr_reg = _pwr_reg,                                    \
 748                 .en_mask = _en_mask,                                    \
 749                 .flags = _flags,                                        \
 750                 .rst_bar_mask = CON0_MT8516_RST_BAR,                    \
 751                 .fmax = MT8516_PLL_FMAX,                                \
 752                 .pcwbits = _pcwbits,                                    \
 753                 .pd_reg = _pd_reg,                                      \
 754                 .pd_shift = _pd_shift,                                  \
 755                 .tuner_reg = _tuner_reg,                                \
 756                 .pcw_reg = _pcw_reg,                                    \
 757                 .pcw_shift = _pcw_shift,                                \
 758                 .div_table = _div_table,                                \
 759         }
 760
 761 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
 762                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg,       \
 763                         _pcw_shift)                                     \
 764                 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
 765                         _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
 766                         NULL)
 767
 768 static const struct mtk_pll_div_table mmpll_div_table[] = {
 769         { .div = 0, .freq = MT8516_PLL_FMAX },
 770         { .div = 1, .freq = 1000000000 },
 771         { .div = 2, .freq = 604500000 },
 772         { .div = 3, .freq = 253500000 },
 773         { .div = 4, .freq = 126750000 },
 774         { } /* sentinel */
 775 };
 776
 777 static const struct mtk_pll_data plls[] = {
 778         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0100, 0x0110, 0x00000001, 0,
 779                 21, 0x0104, 24, 0, 0x0104, 0),
 780         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0120, 0x0130, 0x00000001,
 781                 HAVE_RST_BAR, 21, 0x0124, 24, 0, 0x0124, 0),
 782         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0140, 0x0150, 0x30000001,
 783                 HAVE_RST_BAR, 7, 0x0144, 24, 0, 0x0144, 0),
 784         PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0160, 0x0170, 0x00000001, 0,
 785                 21, 0x0164, 24, 0, 0x0164, 0, mmpll_div_table),
 786         PLL(CLK_APMIXED_APLL1, "apll1", 0x0180, 0x0190, 0x00000001, 0,
 787                 31, 0x0180, 1, 0x0194, 0x0184, 0),
 788         PLL(CLK_APMIXED_APLL2, "apll2", 0x01A0, 0x01B0, 0x00000001, 0,
 789                 31, 0x01A0, 1, 0x01B4, 0x01A4, 0),
 790 };
 791
 792 static void __init mtk_apmixedsys_init(struct device_node *node)
 793 {
 794         struct clk_onecell_data *clk_data;
 795         void __iomem *base;
 796         int r;
 797
 798         base = of_iomap(node, 0);
 799         if (!base) {
 800                 pr_err("%s(): ioremap failed\n", __func__);
 801                 return;
 802         }
 803
 804         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
 805
 806         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 807
 808         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 809         if (r)
 810                 pr_err("%s(): could not register clock provider: %d\n",
 811                         __func__, r);
 812
 813 }
 814 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8516-apmixedsys",
 815                 mtk_apmixedsys_init);