drivers/clk/mediatek/clk-mt8135.c

   1 /*
   2  * Copyright (c) 2014 MediaTek Inc.
   3  * Author: James Liao <jamesjj.liao@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/slab.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <dt-bindings/clock/mt8135-clk.h>
  20
  21 #include "clk-mtk.h"
  22 #include "clk-gate.h"
  23
  24 static DEFINE_SPINLOCK(mt8135_clk_lock);
  25
  26 static const struct mtk_fixed_factor root_clk_alias[] __initconst = {
  27         FACTOR(CLK_TOP_DSI0_LNTC_DSICLK, "dsi0_lntc_dsiclk", "clk_null", 1, 1),
  28         FACTOR(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_clkdig_cts", "clk_null", 1, 1),
  29         FACTOR(CLK_TOP_CLKPH_MCK, "clkph_mck", "clk_null", 1, 1),
  30         FACTOR(CLK_TOP_CPUM_TCK_IN, "cpum_tck_in", "clk_null", 1, 1),
  31 };
  32
  33 static const struct mtk_fixed_factor top_divs[] __initconst = {
  34         FACTOR(CLK_TOP_MAINPLL_806M, "mainpll_806m", "mainpll", 1, 2),
  35         FACTOR(CLK_TOP_MAINPLL_537P3M, "mainpll_537p3m", "mainpll", 1, 3),
  36         FACTOR(CLK_TOP_MAINPLL_322P4M, "mainpll_322p4m", "mainpll", 1, 5),
  37         FACTOR(CLK_TOP_MAINPLL_230P3M, "mainpll_230p3m", "mainpll", 1, 7),
  38
  39         FACTOR(CLK_TOP_UNIVPLL_624M, "univpll_624m", "univpll", 1, 2),
  40         FACTOR(CLK_TOP_UNIVPLL_416M, "univpll_416m", "univpll", 1, 3),
  41         FACTOR(CLK_TOP_UNIVPLL_249P6M, "univpll_249p6m", "univpll", 1, 5),
  42         FACTOR(CLK_TOP_UNIVPLL_178P3M, "univpll_178p3m", "univpll", 1, 7),
  43         FACTOR(CLK_TOP_UNIVPLL_48M, "univpll_48m", "univpll", 1, 26),
  44
  45         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
  46         FACTOR(CLK_TOP_MMPLL_D3, "mmpll_d3", "mmpll", 1, 3),
  47         FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
  48         FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
  49         FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll_d2", 1, 2),
  50         FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll_d3", 1, 2),
  51
  52         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll_806m", 1, 1),
  53         FACTOR(CLK_TOP_SYSPLL_D4, "syspll_d4", "mainpll_806m", 1, 2),
  54         FACTOR(CLK_TOP_SYSPLL_D6, "syspll_d6", "mainpll_806m", 1, 3),
  55         FACTOR(CLK_TOP_SYSPLL_D8, "syspll_d8", "mainpll_806m", 1, 4),
  56         FACTOR(CLK_TOP_SYSPLL_D10, "syspll_d10", "mainpll_806m", 1, 5),
  57         FACTOR(CLK_TOP_SYSPLL_D12, "syspll_d12", "mainpll_806m", 1, 6),
  58         FACTOR(CLK_TOP_SYSPLL_D16, "syspll_d16", "mainpll_806m", 1, 8),
  59         FACTOR(CLK_TOP_SYSPLL_D24, "syspll_d24", "mainpll_806m", 1, 12),
  60
  61         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll_537p3m", 1, 1),
  62
  63         FACTOR(CLK_TOP_SYSPLL_D2P5, "syspll_d2p5", "mainpll_322p4m", 2, 1),
  64         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll_322p4m", 1, 1),
  65
  66         FACTOR(CLK_TOP_SYSPLL_D3P5, "syspll_d3p5", "mainpll_230p3m", 2, 1),
  67
  68         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_624m", 1, 2),
  69         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_624m", 1, 4),
  70         FACTOR(CLK_TOP_UNIVPLL1_D6, "univpll1_d6", "univpll_624m", 1, 6),
  71         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_624m", 1, 8),
  72         FACTOR(CLK_TOP_UNIVPLL1_D10, "univpll1_d10", "univpll_624m", 1, 10),
  73
  74         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_416m", 1, 2),
  75         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_416m", 1, 4),
  76         FACTOR(CLK_TOP_UNIVPLL2_D6, "univpll2_d6", "univpll_416m", 1, 6),
  77         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_416m", 1, 8),
  78
  79         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_416m", 1, 1),
  80         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_249p6m", 1, 1),
  81         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_178p3m", 1, 1),
  82         FACTOR(CLK_TOP_UNIVPLL_D10, "univpll_d10", "univpll_249p6m", 1, 2),
  83         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_48m", 1, 1),
  84
  85         FACTOR(CLK_TOP_APLL, "apll_ck", "audpll", 1, 1),
  86         FACTOR(CLK_TOP_APLL_D4, "apll_d4", "audpll", 1, 4),
  87         FACTOR(CLK_TOP_APLL_D8, "apll_d8", "audpll", 1, 8),
  88         FACTOR(CLK_TOP_APLL_D16, "apll_d16", "audpll", 1, 16),
  89         FACTOR(CLK_TOP_APLL_D24, "apll_d24", "audpll", 1, 24),
  90
  91         FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll", 1, 2),
  92         FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll", 1, 4),
  93         FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll", 1, 8),
  94
  95         FACTOR(CLK_TOP_LVDSTX_CLKDIG_CT, "lvdstx_clkdig_cts", "lvdspll", 1, 1),
  96         FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix_ck", "lvdspll", 1, 1),
  97
  98         FACTOR(CLK_TOP_TVHDMI_H, "tvhdmi_h_ck", "tvdpll", 1, 1),
  99
 100         FACTOR(CLK_TOP_HDMITX_CLKDIG_D2, "hdmitx_clkdig_d2", "hdmitx_clkdig_cts", 1, 2),
 101         FACTOR(CLK_TOP_HDMITX_CLKDIG_D3, "hdmitx_clkdig_d3", "hdmitx_clkdig_cts", 1, 3),
 102
 103         FACTOR(CLK_TOP_TVHDMI_D2, "tvhdmi_d2", "tvhdmi_h_ck", 1, 2),
 104         FACTOR(CLK_TOP_TVHDMI_D4, "tvhdmi_d4", "tvhdmi_h_ck", 1, 4),
 105
 106         FACTOR(CLK_TOP_MEMPLL_MCK_D4, "mempll_mck_d4", "clkph_mck", 1, 4),
 107 };
 108
 109 static const char * const axi_parents[] __initconst = {
 110         "clk26m",
 111         "syspll_d3",
 112         "syspll_d4",
 113         "syspll_d6",
 114         "univpll_d5",
 115         "univpll2_d2",
 116         "syspll_d3p5"
 117 };
 118
 119 static const char * const smi_parents[] __initconst = {
 120         "clk26m",
 121         "clkph_mck",
 122         "syspll_d2p5",
 123         "syspll_d3",
 124         "syspll_d8",
 125         "univpll_d5",
 126         "univpll1_d2",
 127         "univpll1_d6",
 128         "mmpll_d3",
 129         "mmpll_d4",
 130         "mmpll_d5",
 131         "mmpll_d6",
 132         "mmpll_d7",
 133         "vdecpll",
 134         "lvdspll"
 135 };
 136
 137 static const char * const mfg_parents[] __initconst = {
 138         "clk26m",
 139         "univpll1_d4",
 140         "syspll_d2",
 141         "syspll_d2p5",
 142         "syspll_d3",
 143         "univpll_d5",
 144         "univpll1_d2",
 145         "mmpll_d2",
 146         "mmpll_d3",
 147         "mmpll_d4",
 148         "mmpll_d5",
 149         "mmpll_d6",
 150         "mmpll_d7"
 151 };
 152
 153 static const char * const irda_parents[] __initconst = {
 154         "clk26m",
 155         "univpll2_d8",
 156         "univpll1_d6"
 157 };
 158
 159 static const char * const cam_parents[] __initconst = {
 160         "clk26m",
 161         "syspll_d3",
 162         "syspll_d3p5",
 163         "syspll_d4",
 164         "univpll_d5",
 165         "univpll2_d2",
 166         "univpll_d7",
 167         "univpll1_d4"
 168 };
 169
 170 static const char * const aud_intbus_parents[] __initconst = {
 171         "clk26m",
 172         "syspll_d6",
 173         "univpll_d10"
 174 };
 175
 176 static const char * const jpg_parents[] __initconst = {
 177         "clk26m",
 178         "syspll_d5",
 179         "syspll_d4",
 180         "syspll_d3",
 181         "univpll_d7",
 182         "univpll2_d2",
 183         "univpll_d5"
 184 };
 185
 186 static const char * const disp_parents[] __initconst = {
 187         "clk26m",
 188         "syspll_d3p5",
 189         "syspll_d3",
 190         "univpll2_d2",
 191         "univpll_d5",
 192         "univpll1_d2",
 193         "lvdspll",
 194         "vdecpll"
 195 };
 196
 197 static const char * const msdc30_parents[] __initconst = {
 198         "clk26m",
 199         "syspll_d6",
 200         "syspll_d5",
 201         "univpll1_d4",
 202         "univpll2_d4",
 203         "msdcpll"
 204 };
 205
 206 static const char * const usb20_parents[] __initconst = {
 207         "clk26m",
 208         "univpll2_d6",
 209         "univpll1_d10"
 210 };
 211
 212 static const char * const venc_parents[] __initconst = {
 213         "clk26m",
 214         "syspll_d3",
 215         "syspll_d8",
 216         "univpll_d5",
 217         "univpll1_d6",
 218         "mmpll_d4",
 219         "mmpll_d5",
 220         "mmpll_d6"
 221 };
 222
 223 static const char * const spi_parents[] __initconst = {
 224         "clk26m",
 225         "syspll_d6",
 226         "syspll_d8",
 227         "syspll_d10",
 228         "univpll1_d6",
 229         "univpll1_d8"
 230 };
 231
 232 static const char * const uart_parents[] __initconst = {
 233         "clk26m",
 234         "univpll2_d8"
 235 };
 236
 237 static const char * const mem_parents[] __initconst = {
 238         "clk26m",
 239         "clkph_mck"
 240 };
 241
 242 static const char * const camtg_parents[] __initconst = {
 243         "clk26m",
 244         "univpll_d26",
 245         "univpll1_d6",
 246         "syspll_d16",
 247         "syspll_d8"
 248 };
 249
 250 static const char * const audio_parents[] __initconst = {
 251         "clk26m",
 252         "syspll_d24"
 253 };
 254
 255 static const char * const fix_parents[] __initconst = {
 256         "rtc32k",
 257         "clk26m",
 258         "univpll_d5",
 259         "univpll_d7",
 260         "univpll1_d2",
 261         "univpll1_d4",
 262         "univpll1_d6",
 263         "univpll1_d8"
 264 };
 265
 266 static const char * const vdec_parents[] __initconst = {
 267         "clk26m",
 268         "vdecpll",
 269         "clkph_mck",
 270         "syspll_d2p5",
 271         "syspll_d3",
 272         "syspll_d3p5",
 273         "syspll_d4",
 274         "syspll_d5",
 275         "syspll_d6",
 276         "syspll_d8",
 277         "univpll1_d2",
 278         "univpll2_d2",
 279         "univpll_d7",
 280         "univpll_d10",
 281         "univpll2_d4",
 282         "lvdspll"
 283 };
 284
 285 static const char * const ddrphycfg_parents[] __initconst = {
 286         "clk26m",
 287         "axi_sel",
 288         "syspll_d12"
 289 };
 290
 291 static const char * const dpilvds_parents[] __initconst = {
 292         "clk26m",
 293         "lvdspll",
 294         "lvdspll_d2",
 295         "lvdspll_d4",
 296         "lvdspll_d8"
 297 };
 298
 299 static const char * const pmicspi_parents[] __initconst = {
 300         "clk26m",
 301         "univpll2_d6",
 302         "syspll_d8",
 303         "syspll_d10",
 304         "univpll1_d10",
 305         "mempll_mck_d4",
 306         "univpll_d26",
 307         "syspll_d24"
 308 };
 309
 310 static const char * const smi_mfg_as_parents[] __initconst = {
 311         "clk26m",
 312         "smi_sel",
 313         "mfg_sel",
 314         "mem_sel"
 315 };
 316
 317 static const char * const gcpu_parents[] __initconst = {
 318         "clk26m",
 319         "syspll_d4",
 320         "univpll_d7",
 321         "syspll_d5",
 322         "syspll_d6"
 323 };
 324
 325 static const char * const dpi1_parents[] __initconst = {
 326         "clk26m",
 327         "tvhdmi_h_ck",
 328         "tvhdmi_d2",
 329         "tvhdmi_d4"
 330 };
 331
 332 static const char * const cci_parents[] __initconst = {
 333         "clk26m",
 334         "mainpll_537p3m",
 335         "univpll_d3",
 336         "syspll_d2p5",
 337         "syspll_d3",
 338         "syspll_d5"
 339 };
 340
 341 static const char * const apll_parents[] __initconst = {
 342         "clk26m",
 343         "apll_ck",
 344         "apll_d4",
 345         "apll_d8",
 346         "apll_d16",
 347         "apll_d24"
 348 };
 349
 350 static const char * const hdmipll_parents[] __initconst = {
 351         "clk26m",
 352         "hdmitx_clkdig_cts",
 353         "hdmitx_clkdig_d2",
 354         "hdmitx_clkdig_d3"
 355 };
 356
 357 static const struct mtk_composite top_muxes[] __initconst = {
 358         /* CLK_CFG_0 */
 359         MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 360                 0x0140, 0, 3, INVALID_MUX_GATE_BIT),
 361         MUX_GATE(CLK_TOP_SMI_SEL, "smi_sel", smi_parents, 0x0140, 8, 4, 15),
 362         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0140, 16, 4, 23),
 363         MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x0140, 24, 2, 31),
 364         /* CLK_CFG_1 */
 365         MUX_GATE(CLK_TOP_CAM_SEL, "cam_sel", cam_parents, 0x0144, 0, 3, 7),
 366         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
 367                 0x0144, 8, 2, 15),
 368         MUX_GATE(CLK_TOP_JPG_SEL, "jpg_sel", jpg_parents, 0x0144, 16, 3, 23),
 369         MUX_GATE(CLK_TOP_DISP_SEL, "disp_sel", disp_parents, 0x0144, 24, 3, 31),
 370         /* CLK_CFG_2 */
 371         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
 372         MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
 373         MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x0148, 16, 3, 23),
 374         MUX_GATE(CLK_TOP_MSDC30_4_SEL, "msdc30_4_sel", msdc30_parents, 0x0148, 24, 3, 31),
 375         /* CLK_CFG_3 */
 376         MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x014c, 0, 2, 7),
 377         /* CLK_CFG_4 */
 378         MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel", venc_parents, 0x0150, 8, 3, 15),
 379         MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x0150, 16, 3, 23),
 380         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
 381         /* CLK_CFG_6 */
 382         MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
 383         MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0158, 8, 3, 15),
 384         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents, 0x0158, 24, 2, 31),
 385         /* CLK_CFG_7 */
 386         MUX_GATE(CLK_TOP_FIX_SEL, "fix_sel", fix_parents, 0x015c, 0, 3, 7),
 387         MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x015c, 8, 4, 15),
 388         MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents,
 389                 0x015c, 16, 2, 23),
 390         MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel", dpilvds_parents, 0x015c, 24, 3, 31),
 391         /* CLK_CFG_8 */
 392         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0164, 0, 3, 7),
 393         MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0164, 8, 3, 15),
 394         MUX_GATE(CLK_TOP_SMI_MFG_AS_SEL, "smi_mfg_as_sel", smi_mfg_as_parents,
 395                 0x0164, 16, 2, 23),
 396         MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel", gcpu_parents, 0x0164, 24, 3, 31),
 397         /* CLK_CFG_9 */
 398         MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0168, 0, 2, 7),
 399         MUX_GATE(CLK_TOP_CCI_SEL, "cci_sel", cci_parents, 0x0168, 8, 3, 15),
 400         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0168, 16, 3, 23),
 401         MUX_GATE(CLK_TOP_HDMIPLL_SEL, "hdmipll_sel", hdmipll_parents, 0x0168, 24, 2, 31),
 402 };
 403
 404 static const struct mtk_gate_regs infra_cg_regs = {
 405         .set_ofs = 0x0040,
 406         .clr_ofs = 0x0044,
 407         .sta_ofs = 0x0048,
 408 };
 409
 410 #define GATE_ICG(_id, _name, _parent, _shift) { \
 411                 .id = _id,                                      \
 412                 .name = _name,                                  \
 413                 .parent_name = _parent,                         \
 414                 .regs = &infra_cg_regs,                         \
 415                 .shift = _shift,                                \
 416                 .ops = &mtk_clk_gate_ops_setclr,                \
 417         }
 418
 419 static const struct mtk_gate infra_clks[] __initconst = {
 420         GATE_ICG(CLK_INFRA_PMIC_WRAP, "pmic_wrap_ck", "axi_sel", 23),
 421         GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
 422         GATE_ICG(CLK_INFRA_CCIF1_AP_CTRL, "ccif1_ap_ctrl", "axi_sel", 21),
 423         GATE_ICG(CLK_INFRA_CCIF0_AP_CTRL, "ccif0_ap_ctrl", "axi_sel", 20),
 424         GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
 425         GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "cpum_tck_in", 15),
 426         GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
 427         GATE_ICG(CLK_INFRA_MFGAXI, "mfgaxi_ck", "axi_sel", 7),
 428         GATE_ICG(CLK_INFRA_DEVAPC, "devapc_ck", "axi_sel", 6),
 429         GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "aud_intbus_sel", 5),
 430         GATE_ICG(CLK_INFRA_MFG_BUS, "mfg_bus_ck", "axi_sel", 2),
 431         GATE_ICG(CLK_INFRA_SMI, "smi_ck", "smi_sel", 1),
 432         GATE_ICG(CLK_INFRA_DBGCLK, "dbgclk_ck", "axi_sel", 0),
 433 };
 434
 435 static const struct mtk_gate_regs peri0_cg_regs = {
 436         .set_ofs = 0x0008,
 437         .clr_ofs = 0x0010,
 438         .sta_ofs = 0x0018,
 439 };
 440
 441 static const struct mtk_gate_regs peri1_cg_regs = {
 442         .set_ofs = 0x000c,
 443         .clr_ofs = 0x0014,
 444         .sta_ofs = 0x001c,
 445 };
 446
 447 #define GATE_PERI0(_id, _name, _parent, _shift) {       \
 448                 .id = _id,                                      \
 449                 .name = _name,                                  \
 450                 .parent_name = _parent,                         \
 451                 .regs = &peri0_cg_regs,                         \
 452                 .shift = _shift,                                \
 453                 .ops = &mtk_clk_gate_ops_setclr,                \
 454         }
 455
 456 #define GATE_PERI1(_id, _name, _parent, _shift) {       \
 457                 .id = _id,                                      \
 458                 .name = _name,                                  \
 459                 .parent_name = _parent,                         \
 460                 .regs = &peri1_cg_regs,                         \
 461                 .shift = _shift,                                \
 462                 .ops = &mtk_clk_gate_ops_setclr,                \
 463         }
 464
 465 static const struct mtk_gate peri_gates[] __initconst = {
 466         /* PERI0 */
 467         GATE_PERI0(CLK_PERI_I2C5, "i2c5_ck", "axi_sel", 31),
 468         GATE_PERI0(CLK_PERI_I2C4, "i2c4_ck", "axi_sel", 30),
 469         GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "axi_sel", 29),
 470         GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 28),
 471         GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 27),
 472         GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 26),
 473         GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 25),
 474         GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 24),
 475         GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 23),
 476         GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
 477         GATE_PERI0(CLK_PERI_IRDA, "irda_ck", "irda_sel", 21),
 478         GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 20),
 479         GATE_PERI0(CLK_PERI_MD_HIF, "md_hif_ck", "axi_sel", 19),
 480         GATE_PERI0(CLK_PERI_AP_HIF, "ap_hif_ck", "axi_sel", 18),
 481         GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_4_sel", 17),
 482         GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_3_sel", 16),
 483         GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_2_sel", 15),
 484         GATE_PERI0(CLK_PERI_MSDC20_2, "msdc20_2_ck", "msdc30_1_sel", 14),
 485         GATE_PERI0(CLK_PERI_MSDC20_1, "msdc20_1_ck", "msdc30_0_sel", 13),
 486         GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
 487         GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
 488         GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
 489         GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
 490         GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
 491         GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
 492         GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
 493         GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
 494         GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
 495         GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
 496         GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
 497         GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
 498         GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "axi_sel", 0),
 499         /* PERI1 */
 500         GATE_PERI1(CLK_PERI_USBSLV, "usbslv_ck", "axi_sel", 8),
 501         GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 7),
 502         GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 6),
 503         GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "gcpu_sel", 5),
 504         GATE_PERI1(CLK_PERI_FHCTL, "fhctl_ck", "clk26m", 4),
 505         GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi_sel", 3),
 506         GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 2),
 507         GATE_PERI1(CLK_PERI_PERI_PWRAP, "peri_pwrap_ck", "axi_sel", 1),
 508         GATE_PERI1(CLK_PERI_I2C6, "i2c6_ck", "axi_sel", 0),
 509 };
 510
 511 static const char * const uart_ck_sel_parents[] __initconst = {
 512         "clk26m",
 513         "uart_sel",
 514 };
 515
 516 static const struct mtk_composite peri_clks[] __initconst = {
 517         MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
 518         MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
 519         MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
 520         MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
 521 };
 522
 523 static void __init mtk_topckgen_init(struct device_node *node)
 524 {
 525         struct clk_onecell_data *clk_data;
 526         void __iomem *base;
 527         int r;
 528
 529         base = of_iomap(node, 0);
 530         if (!base) {
 531                 pr_err("%s(): ioremap failed\n", __func__);
 532                 return;
 533         }
 534
 535         clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 536
 537         mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
 538         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
 539         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
 540                         &mt8135_clk_lock, clk_data);
 541
 542         clk_prepare_enable(clk_data->clks[CLK_TOP_CCI_SEL]);
 543
 544         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 545         if (r)
 546                 pr_err("%s(): could not register clock provider: %d\n",
 547                         __func__, r);
 548 }
 549 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8135-topckgen", mtk_topckgen_init);
 550
 551 static void __init mtk_infrasys_init(struct device_node *node)
 552 {
 553         struct clk_onecell_data *clk_data;
 554         int r;
 555
 556         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
 557
 558         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
 559                                                 clk_data);
 560
 561         clk_prepare_enable(clk_data->clks[CLK_INFRA_M4U]);
 562
 563         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 564         if (r)
 565                 pr_err("%s(): could not register clock provider: %d\n",
 566                         __func__, r);
 567
 568         mtk_register_reset_controller(node, 2, 0x30);
 569 }
 570 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
 571
 572 static void __init mtk_pericfg_init(struct device_node *node)
 573 {
 574         struct clk_onecell_data *clk_data;
 575         int r;
 576         void __iomem *base;
 577
 578         base = of_iomap(node, 0);
 579         if (!base) {
 580                 pr_err("%s(): ioremap failed\n", __func__);
 581                 return;
 582         }
 583
 584         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
 585
 586         mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
 587                                                 clk_data);
 588         mtk_clk_register_composites(peri_clks, ARRAY_SIZE(peri_clks), base,
 589                         &mt8135_clk_lock, clk_data);
 590
 591         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 592         if (r)
 593                 pr_err("%s(): could not register clock provider: %d\n",
 594                         __func__, r);
 595
 596         mtk_register_reset_controller(node, 2, 0);
 597 }
 598 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
 599
 600 #define MT8135_PLL_FMAX         (2000 * MHZ)
 601 #define CON0_MT8135_RST_BAR     BIT(27)
 602
 603 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
 604                 .id = _id,                                              \
 605                 .name = _name,                                          \
 606                 .reg = _reg,                                            \
 607                 .pwr_reg = _pwr_reg,                                    \
 608                 .en_mask = _en_mask,                                    \
 609                 .flags = _flags,                                        \
 610                 .rst_bar_mask = CON0_MT8135_RST_BAR,                    \
 611                 .fmax = MT8135_PLL_FMAX,                                \
 612                 .pcwbits = _pcwbits,                                    \
 613                 .pd_reg = _pd_reg,                                      \
 614                 .pd_shift = _pd_shift,                                  \
 615                 .tuner_reg = _tuner_reg,                                \
 616                 .pcw_reg = _pcw_reg,                                    \
 617                 .pcw_shift = _pcw_shift,                                \
 618         }
 619
 620 static const struct mtk_pll_data plls[] = {
 621         PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
 622         PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
 623         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x220, 0),
 624         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x238, 9),
 625         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, 0),
 626         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
 627         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
 628         PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8,       0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
 629         PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
 630         PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x304, 0x31c,       0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x308, 0),
 631 };
 632
 633 static void __init mtk_apmixedsys_init(struct device_node *node)
 634 {
 635         struct clk_onecell_data *clk_data;
 636
 637         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
 638         if (!clk_data)
 639                 return;
 640
 641         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 642 }
 643 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8135-apmixedsys",
 644                 mtk_apmixedsys_init);