1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 MediaTek Inc.
4 * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>
7 #include <linux/clk-provider.h>
8 #include <linux/platform_device.h>
13 #include <dt-bindings/clock/mt6797-clk.h>
15 static const struct mtk_gate_regs vdec0_cg_regs = {
21 static const struct mtk_gate_regs vdec1_cg_regs = {
27 #define GATE_VDEC0(_id, _name, _parent, _shift) { \
30 .parent_name = _parent, \
31 .regs = &vdec0_cg_regs, \
33 .ops = &mtk_clk_gate_ops_setclr_inv, \
36 #define GATE_VDEC1(_id, _name, _parent, _shift) { \
39 .parent_name = _parent, \
40 .regs = &vdec1_cg_regs, \
42 .ops = &mtk_clk_gate_ops_setclr_inv, \
45 static const struct mtk_gate vdec_clks[] = {
46 GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),
47 GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),
48 GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
49 GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),
52 static const struct of_device_id of_match_clk_mt6797_vdec[] = {
53 { .compatible = "mediatek,mt6797-vdecsys", },
57 static int clk_mt6797_vdec_probe(struct platform_device *pdev)
59 struct clk_onecell_data *clk_data;
61 struct device_node *node = pdev->dev.of_node;
63 clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
65 mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
68 r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
71 "could not register clock provider: %s: %d\n",
77 static struct platform_driver clk_mt6797_vdec_drv = {
78 .probe = clk_mt6797_vdec_probe,
80 .name = "clk-mt6797-vdec",
81 .of_match_table = of_match_clk_mt6797_vdec,
85 builtin_platform_driver(clk_mt6797_vdec_drv);