drivers/clk/mediatek/clk-mt6765.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018 MediaTek Inc.
   4  * Author: Owen Chen <owen.chen@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/of.h>
   9 #include <linux/of_address.h>
  10 #include <linux/slab.h>
  11 #include <linux/mfd/syscon.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14
  15 #include "clk-gate.h"
  16 #include "clk-mtk.h"
  17 #include "clk-mux.h"
  18 #include "clk-pll.h"
  19
  20 #include <dt-bindings/clock/mt6765-clk.h>
  21
  22 /*fmeter div select 4*/
  23 #define _DIV4_ 1
  24
  25 static DEFINE_SPINLOCK(mt6765_clk_lock);
  26
  27 /* Total 12 subsys */
  28 static void __iomem *cksys_base;
  29 static void __iomem *apmixed_base;
  30
  31 /* CKSYS */
  32 #define CLK_SCP_CFG_0           (cksys_base + 0x200)
  33 #define CLK_SCP_CFG_1           (cksys_base + 0x204)
  34
  35 /* CG */
  36 #define AP_PLL_CON3             (apmixed_base + 0x0C)
  37 #define PLLON_CON0              (apmixed_base + 0x44)
  38 #define PLLON_CON1              (apmixed_base + 0x48)
  39
  40 /* clk cfg update */
  41 #define CLK_CFG_0               0x40
  42 #define CLK_CFG_0_SET           0x44
  43 #define CLK_CFG_0_CLR           0x48
  44 #define CLK_CFG_1               0x50
  45 #define CLK_CFG_1_SET           0x54
  46 #define CLK_CFG_1_CLR           0x58
  47 #define CLK_CFG_2               0x60
  48 #define CLK_CFG_2_SET           0x64
  49 #define CLK_CFG_2_CLR           0x68
  50 #define CLK_CFG_3               0x70
  51 #define CLK_CFG_3_SET           0x74
  52 #define CLK_CFG_3_CLR           0x78
  53 #define CLK_CFG_4               0x80
  54 #define CLK_CFG_4_SET           0x84
  55 #define CLK_CFG_4_CLR           0x88
  56 #define CLK_CFG_5               0x90
  57 #define CLK_CFG_5_SET           0x94
  58 #define CLK_CFG_5_CLR           0x98
  59 #define CLK_CFG_6               0xa0
  60 #define CLK_CFG_6_SET           0xa4
  61 #define CLK_CFG_6_CLR           0xa8
  62 #define CLK_CFG_7               0xb0
  63 #define CLK_CFG_7_SET           0xb4
  64 #define CLK_CFG_7_CLR           0xb8
  65 #define CLK_CFG_8               0xc0
  66 #define CLK_CFG_8_SET           0xc4
  67 #define CLK_CFG_8_CLR           0xc8
  68 #define CLK_CFG_9               0xd0
  69 #define CLK_CFG_9_SET           0xd4
  70 #define CLK_CFG_9_CLR           0xd8
  71 #define CLK_CFG_10              0xe0
  72 #define CLK_CFG_10_SET          0xe4
  73 #define CLK_CFG_10_CLR          0xe8
  74 #define CLK_CFG_UPDATE          0x004
  75
  76 static const struct mtk_fixed_clk fixed_clks[] = {
  77         FIXED_CLK(CLK_TOP_F_FRTC, "f_frtc_ck", "clk32k", 32768),
  78         FIXED_CLK(CLK_TOP_CLK26M, "clk_26m_ck", "clk26m", 26000000),
  79         FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 466000000),
  80 };
  81
  82 static const struct mtk_fixed_factor top_divs[] = {
  83         FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
  84         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
  85         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
  86         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
  87         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
  88         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
  89         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
  90         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
  91         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
  92         FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
  93         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
  94         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
  95         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
  96         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
  97         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
  98         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
  99         FACTOR(CLK_TOP_UNIVPLL, "univpll", "univ2pll", 1, 2),
 100         FACTOR(CLK_TOP_USB20_192M, "usb20_192m_ck", "univpll", 2, 13),
 101         FACTOR(CLK_TOP_USB20_192M_D4, "usb20_192m_d4", "usb20_192m_ck", 1, 4),
 102         FACTOR(CLK_TOP_USB20_192M_D8, "usb20_192m_d8", "usb20_192m_ck", 1, 8),
 103         FACTOR(CLK_TOP_USB20_192M_D16,
 104                "usb20_192m_d16", "usb20_192m_ck", 1, 16),
 105         FACTOR(CLK_TOP_USB20_192M_D32,
 106                "usb20_192m_d32", "usb20_192m_ck", 1, 32),
 107         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
 108         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
 109         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
 110         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
 111         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
 112         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
 113         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
 114         FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
 115         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
 116         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
 117         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
 118         FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
 119         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1, 2),
 120         FACTOR(CLK_TOP_MPLL, "mpll_ck", "mpll", 1, 1),
 121         FACTOR(CLK_TOP_DA_MPLL_104M_DIV, "mpll_104m_div", "mpll_ck", 1, 2),
 122         FACTOR(CLK_TOP_DA_MPLL_52M_DIV, "mpll_52m_div", "mpll_ck", 1, 4),
 123         FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
 124         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
 125         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1, 2),
 126         FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1, 1),
 127         FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1, 2),
 128         FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1, 4),
 129         FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1, 8),
 130         FACTOR(CLK_TOP_ULPOSC1, "ulposc1_ck", "ulposc1", 1, 1),
 131         FACTOR(CLK_TOP_ULPOSC1_D2, "ulposc1_d2", "ulposc1_ck", 1, 2),
 132         FACTOR(CLK_TOP_ULPOSC1_D4, "ulposc1_d4", "ulposc1_ck", 1, 4),
 133         FACTOR(CLK_TOP_ULPOSC1_D8, "ulposc1_d8", "ulposc1_ck", 1, 8),
 134         FACTOR(CLK_TOP_ULPOSC1_D16, "ulposc1_d16", "ulposc1_ck", 1, 16),
 135         FACTOR(CLK_TOP_ULPOSC1_D32, "ulposc1_d32", "ulposc1_ck", 1, 32),
 136         FACTOR(CLK_TOP_F_F26M, "f_f26m_ck", "clk_26m_ck", 1, 1),
 137         FACTOR(CLK_TOP_AXI, "axi_ck", "axi_sel", 1, 1),
 138         FACTOR(CLK_TOP_MM, "mm_ck", "mm_sel", 1, 1),
 139         FACTOR(CLK_TOP_SCP, "scp_ck", "scp_sel", 1, 1),
 140         FACTOR(CLK_TOP_MFG, "mfg_ck", "mfg_sel", 1, 1),
 141         FACTOR(CLK_TOP_F_FUART, "f_fuart_ck", "uart_sel", 1, 1),
 142         FACTOR(CLK_TOP_SPI, "spi_ck", "spi_sel", 1, 1),
 143         FACTOR(CLK_TOP_MSDC50_0, "msdc50_0_ck", "msdc50_0_sel", 1, 1),
 144         FACTOR(CLK_TOP_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 1, 1),
 145         FACTOR(CLK_TOP_AUDIO, "audio_ck", "audio_sel", 1, 1),
 146         FACTOR(CLK_TOP_AUD_1, "aud_1_ck", "aud_1_sel", 1, 1),
 147         FACTOR(CLK_TOP_AUD_ENGEN1, "aud_engen1_ck", "aud_engen1_sel", 1, 1),
 148         FACTOR(CLK_TOP_F_FDISP_PWM, "f_fdisp_pwm_ck", "disp_pwm_sel", 1, 1),
 149         FACTOR(CLK_TOP_SSPM, "sspm_ck", "sspm_sel", 1, 1),
 150         FACTOR(CLK_TOP_DXCC, "dxcc_ck", "dxcc_sel", 1, 1),
 151         FACTOR(CLK_TOP_I2C, "i2c_ck", "i2c_sel", 1, 1),
 152         FACTOR(CLK_TOP_F_FPWM, "f_fpwm_ck", "pwm_sel", 1, 1),
 153         FACTOR(CLK_TOP_F_FSENINF, "f_fseninf_ck", "seninf_sel", 1, 1),
 154         FACTOR(CLK_TOP_AES_FDE, "aes_fde_ck", "aes_fde_sel", 1, 1),
 155         FACTOR(CLK_TOP_F_BIST2FPC, "f_bist2fpc_ck", "univpll2_d2", 1, 1),
 156         FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),
 157         FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL1, "arm_div_pll1", "syspll_ck", 1, 1),
 158         FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL2, "arm_div_pll2", "univpll_d2", 1, 1),
 159         FACTOR(CLK_TOP_DA_USB20_48M_DIV,
 160                "usb20_48m_div", "usb20_192m_d4", 1, 1),
 161         FACTOR(CLK_TOP_DA_UNIV_48M_DIV, "univ_48m_div", "usb20_192m_d4", 1, 1),
 162 };
 163
 164 static const char * const axi_parents[] = {
 165         "clk26m",
 166         "syspll_d7",
 167         "syspll1_d4",
 168         "syspll3_d2"
 169 };
 170
 171 static const char * const mem_parents[] = {
 172         "clk26m",
 173         "dmpll_ck",
 174         "apll1_ck"
 175 };
 176
 177 static const char * const mm_parents[] = {
 178         "clk26m",
 179         "mmpll_ck",
 180         "syspll1_d2",
 181         "syspll_d5",
 182         "syspll1_d4",
 183         "univpll_d5",
 184         "univpll1_d2",
 185         "mmpll_d2"
 186 };
 187
 188 static const char * const scp_parents[] = {
 189         "clk26m",
 190         "syspll4_d2",
 191         "univpll2_d2",
 192         "syspll1_d2",
 193         "univpll1_d2",
 194         "syspll_d3",
 195         "univpll_d3"
 196 };
 197
 198 static const char * const mfg_parents[] = {
 199         "clk26m",
 200         "mfgpll_ck",
 201         "syspll_d3",
 202         "univpll_d3"
 203 };
 204
 205 static const char * const atb_parents[] = {
 206         "clk26m",
 207         "syspll1_d4",
 208         "syspll1_d2"
 209 };
 210
 211 static const char * const camtg_parents[] = {
 212         "clk26m",
 213         "usb20_192m_d8",
 214         "univpll2_d8",
 215         "usb20_192m_d4",
 216         "univpll2_d32",
 217         "usb20_192m_d16",
 218         "usb20_192m_d32"
 219 };
 220
 221 static const char * const uart_parents[] = {
 222         "clk26m",
 223         "univpll2_d8"
 224 };
 225
 226 static const char * const spi_parents[] = {
 227         "clk26m",
 228         "syspll3_d2",
 229         "syspll4_d2",
 230         "syspll2_d4"
 231 };
 232
 233 static const char * const msdc5hclk_parents[] = {
 234         "clk26m",
 235         "syspll1_d2",
 236         "univpll1_d4",
 237         "syspll2_d2"
 238 };
 239
 240 static const char * const msdc50_0_parents[] = {
 241         "clk26m",
 242         "msdcpll_ck",
 243         "syspll2_d2",
 244         "syspll4_d2",
 245         "univpll1_d2",
 246         "syspll1_d2",
 247         "univpll_d5",
 248         "univpll1_d4"
 249 };
 250
 251 static const char * const msdc30_1_parents[] = {
 252         "clk26m",
 253         "msdcpll_d2",
 254         "univpll2_d2",
 255         "syspll2_d2",
 256         "syspll1_d4",
 257         "univpll1_d4",
 258         "usb20_192m_d4",
 259         "syspll2_d4"
 260 };
 261
 262 static const char * const audio_parents[] = {
 263         "clk26m",
 264         "syspll3_d4",
 265         "syspll4_d4",
 266         "syspll1_d16"
 267 };
 268
 269 static const char * const aud_intbus_parents[] = {
 270         "clk26m",
 271         "syspll1_d4",
 272         "syspll4_d2"
 273 };
 274
 275 static const char * const aud_1_parents[] = {
 276         "clk26m",
 277         "apll1_ck"
 278 };
 279
 280 static const char * const aud_engen1_parents[] = {
 281         "clk26m",
 282         "apll1_d2",
 283         "apll1_d4",
 284         "apll1_d8"
 285 };
 286
 287 static const char * const disp_pwm_parents[] = {
 288         "clk26m",
 289         "univpll2_d4",
 290         "ulposc1_d2",
 291         "ulposc1_d8"
 292 };
 293
 294 static const char * const sspm_parents[] = {
 295         "clk26m",
 296         "syspll1_d2",
 297         "syspll_d3"
 298 };
 299
 300 static const char * const dxcc_parents[] = {
 301         "clk26m",
 302         "syspll1_d2",
 303         "syspll1_d4",
 304         "syspll1_d8"
 305 };
 306
 307 static const char * const usb_top_parents[] = {
 308         "clk26m",
 309         "univpll3_d4"
 310 };
 311
 312 static const char * const spm_parents[] = {
 313         "clk26m",
 314         "syspll1_d8"
 315 };
 316
 317 static const char * const i2c_parents[] = {
 318         "clk26m",
 319         "univpll3_d4",
 320         "univpll3_d2",
 321         "syspll1_d8",
 322         "syspll2_d8"
 323 };
 324
 325 static const char * const pwm_parents[] = {
 326         "clk26m",
 327         "univpll3_d4",
 328         "syspll1_d8"
 329 };
 330
 331 static const char * const seninf_parents[] = {
 332         "clk26m",
 333         "univpll1_d4",
 334         "univpll1_d2",
 335         "univpll2_d2"
 336 };
 337
 338 static const char * const aes_fde_parents[] = {
 339         "clk26m",
 340         "msdcpll_ck",
 341         "univpll_d3",
 342         "univpll2_d2",
 343         "univpll1_d2",
 344         "syspll1_d2"
 345 };
 346
 347 static const char * const ulposc_parents[] = {
 348         "clk26m",
 349         "ulposc1_d4",
 350         "ulposc1_d8",
 351         "ulposc1_d16",
 352         "ulposc1_d32"
 353 };
 354
 355 static const char * const camtm_parents[] = {
 356         "clk26m",
 357         "univpll1_d4",
 358         "univpll1_d2",
 359         "univpll2_d2"
 360 };
 361
 362 #define INVALID_UPDATE_REG 0xFFFFFFFF
 363 #define INVALID_UPDATE_SHIFT -1
 364 #define INVALID_MUX_GATE -1
 365
 366 static const struct mtk_mux top_muxes[] = {
 367         /* CLK_CFG_0 */
 368         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
 369                               CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
 370                               0, 2, 7, CLK_CFG_UPDATE, 0, CLK_IS_CRITICAL),
 371         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
 372                               CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
 373                               8, 2, 15, CLK_CFG_UPDATE, 1, CLK_IS_CRITICAL),
 374         MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
 375                         CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
 376                         CLK_CFG_UPDATE, 2),
 377         MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
 378                         CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
 379                         CLK_CFG_UPDATE, 3),
 380         /* CLK_CFG_1 */
 381         MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, CLK_CFG_1,
 382                         CLK_CFG_1_SET, CLK_CFG_1_CLR, 0, 2, 7,
 383                         CLK_CFG_UPDATE, 4),
 384         MUX_GATE_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, CLK_CFG_1,
 385                         CLK_CFG_1_SET, CLK_CFG_1_CLR, 8, 2, 15,
 386                         CLK_CFG_UPDATE, 5),
 387         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
 388                         camtg_parents, CLK_CFG_1, CLK_CFG_1_SET,
 389                         CLK_CFG_1_CLR, 16, 3, 23, CLK_CFG_UPDATE, 6),
 390         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG1_SEL, "camtg1_sel", camtg_parents,
 391                         CLK_CFG_1, CLK_CFG_1_SET, CLK_CFG_1_CLR,
 392                         24, 3, 31, CLK_CFG_UPDATE, 7),
 393         /* CLK_CFG_2 */
 394         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG2_SEL, "camtg2_sel",
 395                         camtg_parents, CLK_CFG_2, CLK_CFG_2_SET,
 396                         CLK_CFG_2_CLR, 0, 3, 7, CLK_CFG_UPDATE, 8),
 397         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG3_SEL, "camtg3_sel", camtg_parents,
 398                         CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR,
 399                         8, 3, 15, CLK_CFG_UPDATE, 9),
 400         MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
 401                         CLK_CFG_2, CLK_CFG_2_SET, CLK_CFG_2_CLR, 16, 1, 23,
 402                         CLK_CFG_UPDATE, 10),
 403         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, CLK_CFG_2,
 404                         CLK_CFG_2_SET, CLK_CFG_2_CLR, 24, 2, 31,
 405                         CLK_CFG_UPDATE, 11),
 406         /* CLK_CFG_3 */
 407         MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk",
 408                         msdc5hclk_parents, CLK_CFG_3, CLK_CFG_3_SET,
 409                         CLK_CFG_3_CLR, 0, 2, 7, CLK_CFG_UPDATE, 12),
 410         MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
 411                         msdc50_0_parents, CLK_CFG_3, CLK_CFG_3_SET,
 412                         CLK_CFG_3_CLR, 8, 3, 15, CLK_CFG_UPDATE, 13),
 413         MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
 414                         msdc30_1_parents, CLK_CFG_3, CLK_CFG_3_SET,
 415                         CLK_CFG_3_CLR, 16, 3, 23, CLK_CFG_UPDATE, 14),
 416         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_SEL, "audio_sel", audio_parents,
 417                         CLK_CFG_3, CLK_CFG_3_SET, CLK_CFG_3_CLR,
 418                         24, 2, 31, CLK_CFG_UPDATE, 15),
 419         /* CLK_CFG_4 */
 420         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
 421                         aud_intbus_parents, CLK_CFG_4, CLK_CFG_4_SET,
 422                         CLK_CFG_4_CLR, 0, 2, 7, CLK_CFG_UPDATE, 16),
 423         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents,
 424                         CLK_CFG_4, CLK_CFG_4_SET, CLK_CFG_4_CLR,
 425                         8, 1, 15, CLK_CFG_UPDATE, 17),
 426         MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
 427                         aud_engen1_parents, CLK_CFG_4, CLK_CFG_4_SET,
 428                         CLK_CFG_4_CLR, 16, 2, 23, CLK_CFG_UPDATE, 18),
 429         MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
 430                         disp_pwm_parents, CLK_CFG_4, CLK_CFG_4_SET,
 431                         CLK_CFG_4_CLR, 24, 2, 31, CLK_CFG_UPDATE, 19),
 432         /* CLK_CFG_5 */
 433         MUX_GATE_CLR_SET_UPD(CLK_TOP_SSPM_SEL, "sspm_sel", sspm_parents,
 434                         CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 0, 2, 7,
 435                         CLK_CFG_UPDATE, 20),
 436         MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel", dxcc_parents,
 437                         CLK_CFG_5, CLK_CFG_5_SET, CLK_CFG_5_CLR, 8, 2, 15,
 438                         CLK_CFG_UPDATE, 21),
 439         MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_SEL, "usb_top_sel",
 440                         usb_top_parents, CLK_CFG_5, CLK_CFG_5_SET,
 441                         CLK_CFG_5_CLR, 16, 1, 23, CLK_CFG_UPDATE, 22),
 442         MUX_GATE_CLR_SET_UPD(CLK_TOP_SPM_SEL, "spm_sel", spm_parents, CLK_CFG_5,
 443                         CLK_CFG_5_SET, CLK_CFG_5_CLR, 24, 1, 31,
 444                         CLK_CFG_UPDATE, 23),
 445         /* CLK_CFG_6 */
 446         MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, CLK_CFG_6,
 447                         CLK_CFG_6_SET, CLK_CFG_6_CLR, 0, 3, 7, CLK_CFG_UPDATE,
 448                         24),
 449         MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, CLK_CFG_6,
 450                         CLK_CFG_6_SET, CLK_CFG_6_CLR, 8, 2, 15, CLK_CFG_UPDATE,
 451                         25),
 452         MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel", seninf_parents,
 453                         CLK_CFG_6, CLK_CFG_6_SET, CLK_CFG_6_CLR, 16, 2, 23,
 454                         CLK_CFG_UPDATE, 26),
 455         MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_FDE_SEL, "aes_fde_sel",
 456                         aes_fde_parents, CLK_CFG_6, CLK_CFG_6_SET,
 457                         CLK_CFG_6_CLR, 24, 3, 31, CLK_CFG_UPDATE, 27),
 458         /* CLK_CFG_7 */
 459         MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_PWRAP_ULPOSC_SEL, "ulposc_sel",
 460                               ulposc_parents, CLK_CFG_7, CLK_CFG_7_SET,
 461                               CLK_CFG_7_CLR, 0, 3, 7, CLK_CFG_UPDATE, 28,
 462                               CLK_IS_CRITICAL),
 463         MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel", camtm_parents,
 464                         CLK_CFG_7, CLK_CFG_7_SET, CLK_CFG_7_CLR, 8, 2, 15,
 465                         CLK_CFG_UPDATE, 29),
 466 };
 467
 468 static const struct mtk_gate_regs top0_cg_regs = {
 469         .set_ofs = 0x0,
 470         .clr_ofs = 0x0,
 471         .sta_ofs = 0x0,
 472 };
 473
 474 static const struct mtk_gate_regs top1_cg_regs = {
 475         .set_ofs = 0x104,
 476         .clr_ofs = 0x104,
 477         .sta_ofs = 0x104,
 478 };
 479
 480 static const struct mtk_gate_regs top2_cg_regs = {
 481         .set_ofs = 0x320,
 482         .clr_ofs = 0x320,
 483         .sta_ofs = 0x320,
 484 };
 485
 486 #define GATE_TOP0(_id, _name, _parent, _shift) {        \
 487                 .id = _id,                              \
 488                 .name = _name,                          \
 489                 .parent_name = _parent,                 \
 490                 .regs = &top0_cg_regs,                  \
 491                 .shift = _shift,                        \
 492                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 493         }
 494
 495 #define GATE_TOP1(_id, _name, _parent, _shift) {        \
 496                 .id = _id,                              \
 497                 .name = _name,                          \
 498                 .parent_name = _parent,                 \
 499                 .regs = &top1_cg_regs,                  \
 500                 .shift = _shift,                        \
 501                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 502         }
 503
 504 #define GATE_TOP2(_id, _name, _parent, _shift) {        \
 505                 .id = _id,                              \
 506                 .name = _name,                          \
 507                 .parent_name = _parent,                 \
 508                 .regs = &top2_cg_regs,                  \
 509                 .shift = _shift,                        \
 510                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 511         }
 512
 513 static const struct mtk_gate top_clks[] = {
 514         /* TOP0 */
 515         GATE_TOP0(CLK_TOP_MD_32K, "md_32k", "f_frtc_ck", 8),
 516         GATE_TOP0(CLK_TOP_MD_26M, "md_26m", "f_f26m_ck", 9),
 517         GATE_TOP0(CLK_TOP_MD2_32K, "md2_32k", "f_frtc_ck", 10),
 518         GATE_TOP0(CLK_TOP_MD2_26M, "md2_26m", "f_f26m_ck", 11),
 519         /* TOP1 */
 520         GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL0_EN,
 521                   "arm_div_pll0_en", "arm_div_pll0", 3),
 522         GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL1_EN,
 523                   "arm_div_pll1_en", "arm_div_pll1", 4),
 524         GATE_TOP1(CLK_TOP_ARMPLL_DIVIDER_PLL2_EN,
 525                   "arm_div_pll2_en", "arm_div_pll2", 5),
 526         GATE_TOP1(CLK_TOP_FMEM_OCC_DRC_EN, "drc_en", "univpll2_d2", 6),
 527         GATE_TOP1(CLK_TOP_USB20_48M_EN, "usb20_48m_en", "usb20_48m_div", 8),
 528         GATE_TOP1(CLK_TOP_UNIVPLL_48M_EN, "univpll_48m_en", "univ_48m_div", 9),
 529         GATE_TOP1(CLK_TOP_F_UFS_MP_SAP_CFG_EN, "ufs_sap", "f_f26m_ck", 12),
 530         GATE_TOP1(CLK_TOP_F_BIST2FPC_EN, "bist2fpc", "f_bist2fpc_ck", 16),
 531         /* TOP2 */
 532         GATE_TOP2(CLK_TOP_APLL12_DIV0, "apll12_div0", "aud_1_ck", 2),
 533         GATE_TOP2(CLK_TOP_APLL12_DIV1, "apll12_div1", "aud_1_ck", 3),
 534         GATE_TOP2(CLK_TOP_APLL12_DIV2, "apll12_div2", "aud_1_ck", 4),
 535         GATE_TOP2(CLK_TOP_APLL12_DIV3, "apll12_div3", "aud_1_ck", 5),
 536 };
 537
 538 static const struct mtk_gate_regs ifr2_cg_regs = {
 539         .set_ofs = 0x80,
 540         .clr_ofs = 0x84,
 541         .sta_ofs = 0x90,
 542 };
 543
 544 static const struct mtk_gate_regs ifr3_cg_regs = {
 545         .set_ofs = 0x88,
 546         .clr_ofs = 0x8c,
 547         .sta_ofs = 0x94,
 548 };
 549
 550 static const struct mtk_gate_regs ifr4_cg_regs = {
 551         .set_ofs = 0xa4,
 552         .clr_ofs = 0xa8,
 553         .sta_ofs = 0xac,
 554 };
 555
 556 static const struct mtk_gate_regs ifr5_cg_regs = {
 557         .set_ofs = 0xc0,
 558         .clr_ofs = 0xc4,
 559         .sta_ofs = 0xc8,
 560 };
 561
 562 #define GATE_IFR2(_id, _name, _parent, _shift) {        \
 563                 .id = _id,                              \
 564                 .name = _name,                          \
 565                 .parent_name = _parent,                 \
 566                 .regs = &ifr2_cg_regs,                  \
 567                 .shift = _shift,                        \
 568                 .ops = &mtk_clk_gate_ops_setclr,        \
 569         }
 570
 571 #define GATE_IFR3(_id, _name, _parent, _shift) {        \
 572                 .id = _id,                              \
 573                 .name = _name,                          \
 574                 .parent_name = _parent,                 \
 575                 .regs = &ifr3_cg_regs,                  \
 576                 .shift = _shift,                        \
 577                 .ops = &mtk_clk_gate_ops_setclr,        \
 578         }
 579
 580 #define GATE_IFR4(_id, _name, _parent, _shift) {        \
 581                 .id = _id,                              \
 582                 .name = _name,                          \
 583                 .parent_name = _parent,                 \
 584                 .regs = &ifr4_cg_regs,                  \
 585                 .shift = _shift,                        \
 586                 .ops = &mtk_clk_gate_ops_setclr,        \
 587         }
 588
 589 #define GATE_IFR5(_id, _name, _parent, _shift) {        \
 590                 .id = _id,                              \
 591                 .name = _name,                          \
 592                 .parent_name = _parent,                 \
 593                 .regs = &ifr5_cg_regs,                  \
 594                 .shift = _shift,                        \
 595                 .ops = &mtk_clk_gate_ops_setclr,        \
 596         }
 597
 598 static const struct mtk_gate ifr_clks[] = {
 599         /* INFRA_TOPAXI */
 600         /* INFRA PERI */
 601         /* INFRA mode 0 */
 602         GATE_IFR2(CLK_IFR_ICUSB, "ifr_icusb", "axi_ck", 8),
 603         GATE_IFR2(CLK_IFR_GCE, "ifr_gce", "axi_ck", 9),
 604         GATE_IFR2(CLK_IFR_THERM, "ifr_therm", "axi_ck", 10),
 605         GATE_IFR2(CLK_IFR_I2C_AP, "ifr_i2c_ap", "i2c_ck", 11),
 606         GATE_IFR2(CLK_IFR_I2C_CCU, "ifr_i2c_ccu", "i2c_ck", 12),
 607         GATE_IFR2(CLK_IFR_I2C_SSPM, "ifr_i2c_sspm", "i2c_ck", 13),
 608         GATE_IFR2(CLK_IFR_I2C_RSV, "ifr_i2c_rsv", "i2c_ck", 14),
 609         GATE_IFR2(CLK_IFR_PWM_HCLK, "ifr_pwm_hclk", "axi_ck", 15),
 610         GATE_IFR2(CLK_IFR_PWM1, "ifr_pwm1", "f_fpwm_ck", 16),
 611         GATE_IFR2(CLK_IFR_PWM2, "ifr_pwm2", "f_fpwm_ck", 17),
 612         GATE_IFR2(CLK_IFR_PWM3, "ifr_pwm3", "f_fpwm_ck", 18),
 613         GATE_IFR2(CLK_IFR_PWM4, "ifr_pwm4", "f_fpwm_ck", 19),
 614         GATE_IFR2(CLK_IFR_PWM5, "ifr_pwm5", "f_fpwm_ck", 20),
 615         GATE_IFR2(CLK_IFR_PWM, "ifr_pwm", "f_fpwm_ck", 21),
 616         GATE_IFR2(CLK_IFR_UART0, "ifr_uart0", "f_fuart_ck", 22),
 617         GATE_IFR2(CLK_IFR_UART1, "ifr_uart1", "f_fuart_ck", 23),
 618         GATE_IFR2(CLK_IFR_GCE_26M, "ifr_gce_26m", "f_f26m_ck", 27),
 619         GATE_IFR2(CLK_IFR_CQ_DMA_FPC, "ifr_dma", "axi_ck", 28),
 620         GATE_IFR2(CLK_IFR_BTIF, "ifr_btif", "axi_ck", 31),
 621         /* INFRA mode 1 */
 622         GATE_IFR3(CLK_IFR_SPI0, "ifr_spi0", "spi_ck", 1),
 623         GATE_IFR3(CLK_IFR_MSDC0, "ifr_msdc0", "msdc5hclk", 2),
 624         GATE_IFR3(CLK_IFR_MSDC1, "ifr_msdc1", "axi_ck", 4),
 625         GATE_IFR3(CLK_IFR_TRNG, "ifr_trng", "axi_ck", 9),
 626         GATE_IFR3(CLK_IFR_AUXADC, "ifr_auxadc", "f_f26m_ck", 10),
 627         GATE_IFR3(CLK_IFR_CCIF1_AP, "ifr_ccif1_ap", "axi_ck", 12),
 628         GATE_IFR3(CLK_IFR_CCIF1_MD, "ifr_ccif1_md", "axi_ck", 13),
 629         GATE_IFR3(CLK_IFR_AUXADC_MD, "ifr_auxadc_md", "f_f26m_ck", 14),
 630         GATE_IFR3(CLK_IFR_AP_DMA, "ifr_ap_dma", "axi_ck", 18),
 631         GATE_IFR3(CLK_IFR_DEVICE_APC, "ifr_dapc", "axi_ck", 20),
 632         GATE_IFR3(CLK_IFR_CCIF_AP, "ifr_ccif_ap", "axi_ck", 23),
 633         GATE_IFR3(CLK_IFR_AUDIO, "ifr_audio", "axi_ck", 25),
 634         GATE_IFR3(CLK_IFR_CCIF_MD, "ifr_ccif_md", "axi_ck", 26),
 635         /* INFRA mode 2 */
 636         GATE_IFR4(CLK_IFR_RG_PWM_FBCLK6, "ifr_pwmfb", "f_f26m_ck", 0),
 637         GATE_IFR4(CLK_IFR_DISP_PWM, "ifr_disp_pwm", "f_fdisp_pwm_ck", 2),
 638         GATE_IFR4(CLK_IFR_CLDMA_BCLK, "ifr_cldmabclk", "axi_ck", 3),
 639         GATE_IFR4(CLK_IFR_AUDIO_26M_BCLK, "ifr_audio26m", "f_f26m_ck", 4),
 640         GATE_IFR4(CLK_IFR_SPI1, "ifr_spi1", "spi_ck", 6),
 641         GATE_IFR4(CLK_IFR_I2C4, "ifr_i2c4", "i2c_ck", 7),
 642         GATE_IFR4(CLK_IFR_SPI2, "ifr_spi2", "spi_ck", 9),
 643         GATE_IFR4(CLK_IFR_SPI3, "ifr_spi3", "spi_ck", 10),
 644         GATE_IFR4(CLK_IFR_I2C5, "ifr_i2c5", "i2c_ck", 18),
 645         GATE_IFR4(CLK_IFR_I2C5_ARBITER, "ifr_i2c5a", "i2c_ck", 19),
 646         GATE_IFR4(CLK_IFR_I2C5_IMM, "ifr_i2c5_imm", "i2c_ck", 20),
 647         GATE_IFR4(CLK_IFR_I2C1_ARBITER, "ifr_i2c1a", "i2c_ck", 21),
 648         GATE_IFR4(CLK_IFR_I2C1_IMM, "ifr_i2c1_imm", "i2c_ck", 22),
 649         GATE_IFR4(CLK_IFR_I2C2_ARBITER, "ifr_i2c2a", "i2c_ck", 23),
 650         GATE_IFR4(CLK_IFR_I2C2_IMM, "ifr_i2c2_imm", "i2c_ck", 24),
 651         GATE_IFR4(CLK_IFR_SPI4, "ifr_spi4", "spi_ck", 25),
 652         GATE_IFR4(CLK_IFR_SPI5, "ifr_spi5", "spi_ck", 26),
 653         GATE_IFR4(CLK_IFR_CQ_DMA, "ifr_cq_dma", "axi_ck", 27),
 654         GATE_IFR4(CLK_IFR_FAES_FDE, "ifr_faes_fde_ck", "aes_fde_ck", 29),
 655         /* INFRA mode 3 */
 656         GATE_IFR5(CLK_IFR_MSDC0_SELF, "ifr_msdc0sf", "msdc50_0_ck", 0),
 657         GATE_IFR5(CLK_IFR_MSDC1_SELF, "ifr_msdc1sf", "msdc50_0_ck", 1),
 658         GATE_IFR5(CLK_IFR_I2C6, "ifr_i2c6", "i2c_ck", 6),
 659         GATE_IFR5(CLK_IFR_AP_MSDC0, "ifr_ap_msdc0", "msdc50_0_ck", 7),
 660         GATE_IFR5(CLK_IFR_MD_MSDC0, "ifr_md_msdc0", "msdc50_0_ck", 8),
 661         GATE_IFR5(CLK_IFR_MSDC0_SRC, "ifr_msdc0_clk", "msdc50_0_ck", 9),
 662         GATE_IFR5(CLK_IFR_MSDC1_SRC, "ifr_msdc1_clk", "msdc30_1_ck", 10),
 663         GATE_IFR5(CLK_IFR_MCU_PM_BCLK, "ifr_mcu_pm_bclk", "axi_ck", 17),
 664         GATE_IFR5(CLK_IFR_CCIF2_AP, "ifr_ccif2_ap", "axi_ck", 18),
 665         GATE_IFR5(CLK_IFR_CCIF2_MD, "ifr_ccif2_md", "axi_ck", 19),
 666         GATE_IFR5(CLK_IFR_CCIF3_AP, "ifr_ccif3_ap", "axi_ck", 20),
 667         GATE_IFR5(CLK_IFR_CCIF3_MD, "ifr_ccif3_md", "axi_ck", 21),
 668 };
 669
 670 /* additional CCF control for mipi26M race condition(disp/camera) */
 671 static const struct mtk_gate_regs apmixed_cg_regs = {
 672         .set_ofs = 0x14,
 673         .clr_ofs = 0x14,
 674         .sta_ofs = 0x14,
 675 };
 676
 677 #define GATE_APMIXED(_id, _name, _parent, _shift) {     \
 678                 .id = _id,                              \
 679                 .name = _name,                          \
 680                 .parent_name = _parent,                 \
 681                 .regs = &apmixed_cg_regs,               \
 682                 .shift = _shift,                        \
 683                 .ops = &mtk_clk_gate_ops_no_setclr_inv,         \
 684         }
 685
 686 static const struct mtk_gate apmixed_clks[] = {
 687         /* AUDIO0 */
 688         GATE_APMIXED(CLK_APMIXED_SSUSB26M, "apmixed_ssusb26m", "f_f26m_ck",
 689                      4),
 690         GATE_APMIXED(CLK_APMIXED_APPLL26M, "apmixed_appll26m", "f_f26m_ck",
 691                      5),
 692         GATE_APMIXED(CLK_APMIXED_MIPIC0_26M, "apmixed_mipic026m", "f_f26m_ck",
 693                      6),
 694         GATE_APMIXED(CLK_APMIXED_MDPLLGP26M, "apmixed_mdpll26m", "f_f26m_ck",
 695                      7),
 696         GATE_APMIXED(CLK_APMIXED_MMSYS_F26M, "apmixed_mmsys26m", "f_f26m_ck",
 697                      8),
 698         GATE_APMIXED(CLK_APMIXED_UFS26M, "apmixed_ufs26m", "f_f26m_ck",
 699                      9),
 700         GATE_APMIXED(CLK_APMIXED_MIPIC1_26M, "apmixed_mipic126m", "f_f26m_ck",
 701                      11),
 702         GATE_APMIXED(CLK_APMIXED_MEMPLL26M, "apmixed_mempll26m", "f_f26m_ck",
 703                      13),
 704         GATE_APMIXED(CLK_APMIXED_CLKSQ_LVPLL_26M, "apmixed_lvpll26m",
 705                      "f_f26m_ck", 14),
 706         GATE_APMIXED(CLK_APMIXED_MIPID0_26M, "apmixed_mipid026m", "f_f26m_ck",
 707                      16),
 708 };
 709
 710 #define MT6765_PLL_FMAX         (3800UL * MHZ)
 711 #define MT6765_PLL_FMIN         (1500UL * MHZ)
 712
 713 #define CON0_MT6765_RST_BAR     BIT(23)
 714
 715 #define PLL_INFO_NULL           (0xFF)
 716
 717 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,   \
 718                 _pcwibits, _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,\
 719                 _tuner_en_bit, _pcw_reg, _pcw_shift, _div_table) {\
 720                 .id = _id,                                              \
 721                 .name = _name,                                          \
 722                 .reg = _reg,                                            \
 723                 .pwr_reg = _pwr_reg,                                    \
 724                 .en_mask = _en_mask,                                    \
 725                 .flags = _flags,                                        \
 726                 .rst_bar_mask = CON0_MT6765_RST_BAR,                    \
 727                 .fmax = MT6765_PLL_FMAX,                                \
 728                 .fmin = MT6765_PLL_FMIN,                                \
 729                 .pcwbits = _pcwbits,                                    \
 730                 .pcwibits = _pcwibits,                                  \
 731                 .pd_reg = _pd_reg,                                      \
 732                 .pd_shift = _pd_shift,                                  \
 733                 .tuner_reg = _tuner_reg,                                \
 734                 .tuner_en_reg = _tuner_en_reg,                          \
 735                 .tuner_en_bit = _tuner_en_bit,                          \
 736                 .pcw_reg = _pcw_reg,                                    \
 737                 .pcw_shift = _pcw_shift,                                \
 738                 .div_table = _div_table,                                \
 739         }
 740
 741 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
 742                         _pcwibits, _pd_reg, _pd_shift, _tuner_reg,      \
 743                         _tuner_en_reg, _tuner_en_bit, _pcw_reg, \
 744                         _pcw_shift)     \
 745                 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
 746                         _pcwbits, _pcwibits, _pd_reg, _pd_shift,        \
 747                         _tuner_reg, _tuner_en_reg, _tuner_en_bit,       \
 748                         _pcw_reg, _pcw_shift, NULL)     \
 749
 750 static const struct mtk_pll_data plls[] = {
 751         PLL(CLK_APMIXED_ARMPLL_L, "armpll_l", 0x021C, 0x0228, BIT(0),
 752             PLL_AO, 22, 8, 0x0220, 24, 0, 0, 0, 0x0220, 0),
 753         PLL(CLK_APMIXED_ARMPLL, "armpll", 0x020C, 0x0218, BIT(0),
 754             PLL_AO, 22, 8, 0x0210, 24, 0, 0, 0, 0x0210, 0),
 755         PLL(CLK_APMIXED_CCIPLL, "ccipll", 0x022C, 0x0238, BIT(0),
 756             PLL_AO, 22, 8, 0x0230, 24, 0, 0, 0, 0x0230, 0),
 757         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x023C, 0x0248, BIT(0),
 758             (HAVE_RST_BAR | PLL_AO), 22, 8, 0x0240, 24, 0, 0, 0, 0x0240,
 759             0),
 760         PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x024C, 0x0258, BIT(0),
 761             0, 22, 8, 0x0250, 24, 0, 0, 0, 0x0250, 0),
 762         PLL(CLK_APMIXED_MMPLL, "mmpll", 0x025C, 0x0268, BIT(0),
 763             0, 22, 8, 0x0260, 24, 0, 0, 0, 0x0260, 0),
 764         PLL(CLK_APMIXED_UNIV2PLL, "univ2pll", 0x026C, 0x0278, BIT(0),
 765             HAVE_RST_BAR, 22, 8, 0x0270, 24, 0, 0, 0, 0x0270, 0),
 766         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x027C, 0x0288, BIT(0),
 767             0, 22, 8, 0x0280, 24, 0, 0, 0, 0x0280, 0),
 768         PLL(CLK_APMIXED_APLL1, "apll1", 0x028C, 0x029C, BIT(0),
 769             0, 32, 8, 0x0290, 24, 0x0040, 0x000C, 0, 0x0294, 0),
 770         PLL(CLK_APMIXED_MPLL, "mpll", 0x02A0, 0x02AC, BIT(0),
 771             PLL_AO, 22, 8, 0x02A4, 24, 0, 0, 0, 0x02A4, 0),
 772 };
 773
 774 static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
 775 {
 776         struct clk_onecell_data *clk_data;
 777         int r;
 778         struct device_node *node = pdev->dev.of_node;
 779         void __iomem *base;
 780         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 781
 782         base = devm_ioremap_resource(&pdev->dev, res);
 783         if (IS_ERR(base)) {
 784                 pr_err("%s(): ioremap failed\n", __func__);
 785                 return PTR_ERR(base);
 786         }
 787
 788         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
 789
 790         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
 791
 792         mtk_clk_register_gates(node, apmixed_clks,
 793                                ARRAY_SIZE(apmixed_clks), clk_data);
 794         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 795
 796         if (r)
 797                 pr_err("%s(): could not register clock provider: %d\n",
 798                        __func__, r);
 799
 800         apmixed_base = base;
 801         /* MPLL, CCIPLL, MAINPLL set HW mode, TDCLKSQ, CLKSQ1 */
 802         writel(readl(AP_PLL_CON3) & 0xFFFFFFE1, AP_PLL_CON3);
 803         writel(readl(PLLON_CON0) & 0x01041041, PLLON_CON0);
 804         writel(readl(PLLON_CON1) & 0x01041041, PLLON_CON1);
 805
 806         return r;
 807 }
 808
 809 static int clk_mt6765_top_probe(struct platform_device *pdev)
 810 {
 811         int r;
 812         struct device_node *node = pdev->dev.of_node;
 813         void __iomem *base;
 814         struct clk_onecell_data *clk_data;
 815         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 816
 817         base = devm_ioremap_resource(&pdev->dev, res);
 818         if (IS_ERR(base)) {
 819                 pr_err("%s(): ioremap failed\n", __func__);
 820                 return PTR_ERR(base);
 821         }
 822
 823         clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
 824
 825         mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks),
 826                                     clk_data);
 827         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs),
 828                                  clk_data);
 829         mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
 830                                &mt6765_clk_lock, clk_data);
 831         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
 832                                clk_data);
 833
 834         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 835
 836         if (r)
 837                 pr_err("%s(): could not register clock provider: %d\n",
 838                        __func__, r);
 839
 840         cksys_base = base;
 841         /* [4]:no need */
 842         writel(readl(CLK_SCP_CFG_0) | 0x3EF, CLK_SCP_CFG_0);
 843         /*[1,2,3,8]: no need*/
 844         writel(readl(CLK_SCP_CFG_1) | 0x1, CLK_SCP_CFG_1);
 845
 846         return r;
 847 }
 848
 849 static int clk_mt6765_ifr_probe(struct platform_device *pdev)
 850 {
 851         struct clk_onecell_data *clk_data;
 852         int r;
 853         struct device_node *node = pdev->dev.of_node;
 854         void __iomem *base;
 855         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 856
 857         base = devm_ioremap_resource(&pdev->dev, res);
 858         if (IS_ERR(base)) {
 859                 pr_err("%s(): ioremap failed\n", __func__);
 860                 return PTR_ERR(base);
 861         }
 862
 863         clk_data = mtk_alloc_clk_data(CLK_IFR_NR_CLK);
 864
 865         mtk_clk_register_gates(node, ifr_clks, ARRAY_SIZE(ifr_clks),
 866                                clk_data);
 867         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 868
 869         if (r)
 870                 pr_err("%s(): could not register clock provider: %d\n",
 871                        __func__, r);
 872
 873         return r;
 874 }
 875
 876 static const struct of_device_id of_match_clk_mt6765[] = {
 877         {
 878                 .compatible = "mediatek,mt6765-apmixedsys",
 879                 .data = clk_mt6765_apmixed_probe,
 880         }, {
 881                 .compatible = "mediatek,mt6765-topckgen",
 882                 .data = clk_mt6765_top_probe,
 883         }, {
 884                 .compatible = "mediatek,mt6765-infracfg",
 885                 .data = clk_mt6765_ifr_probe,
 886         }, {
 887                 /* sentinel */
 888         }
 889 };
 890
 891 static int clk_mt6765_probe(struct platform_device *pdev)
 892 {
 893         int (*clk_probe)(struct platform_device *d);
 894         int r;
 895
 896         clk_probe = of_device_get_match_data(&pdev->dev);
 897         if (!clk_probe)
 898                 return -EINVAL;
 899
 900         r = clk_probe(pdev);
 901         if (r)
 902                 dev_err(&pdev->dev,
 903                         "could not register clock provider: %s: %d\n",
 904                         pdev->name, r);
 905
 906         return r;
 907 }
 908
 909 static struct platform_driver clk_mt6765_drv = {
 910         .probe = clk_mt6765_probe,
 911         .driver = {
 912                 .name = "clk-mt6765",
 913                 .of_match_table = of_match_clk_mt6765,
 914         },
 915 };
 916
 917 static int __init clk_mt6765_init(void)
 918 {
 919         return platform_driver_register(&clk_mt6765_drv);
 920 }
 921
 922 arch_initcall(clk_mt6765_init);