drivers/clk/mediatek/clk-mt2712.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/mfd/syscon.h>
  10 #include <linux/of.h>
  11 #include <linux/of_address.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/slab.h>
  15
  16 #include "clk-mtk.h"
  17 #include "clk-gate.h"
  18
  19 #include <dt-bindings/clock/mt2712-clk.h>
  20
  21 static DEFINE_SPINLOCK(mt2712_clk_lock);
  22
  23 static const struct mtk_fixed_clk top_fixed_clks[] = {
  24         FIXED_CLK(CLK_TOP_VPLL3_DPIX, "vpll3_dpix", NULL, 200000000),
  25         FIXED_CLK(CLK_TOP_VPLL_DPIX, "vpll_dpix", NULL, 200000000),
  26         FIXED_CLK(CLK_TOP_LTEPLL_FS26M, "ltepll_fs26m", NULL, 26000000),
  27         FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", NULL, 350000000),
  28         FIXED_CLK(CLK_TOP_DSI0_LNTC, "dsi0_lntc", NULL, 143000000),
  29         FIXED_CLK(CLK_TOP_DSI1_LNTC, "dsi1_lntc", NULL, 143000000),
  30         FIXED_CLK(CLK_TOP_LVDSTX3_CLKDIG_CTS, "lvdstx3", NULL, 140000000),
  31         FIXED_CLK(CLK_TOP_LVDSTX_CLKDIG_CTS, "lvdstx", NULL, 140000000),
  32         FIXED_CLK(CLK_TOP_CLKRTC_EXT, "clkrtc_ext", NULL, 32768),
  33         FIXED_CLK(CLK_TOP_CLKRTC_INT, "clkrtc_int", NULL, 32747),
  34         FIXED_CLK(CLK_TOP_CSI0, "csi0", NULL, 26000000),
  35         FIXED_CLK(CLK_TOP_CVBSPLL, "cvbspll", NULL, 108000000),
  36 };
  37
  38 static const struct mtk_fixed_factor top_early_divs[] = {
  39         FACTOR(CLK_TOP_SYS_26M, "sys_26m", "clk26m", 1,
  40                 1),
  41         FACTOR(CLK_TOP_CLK26M_D2, "clk26m_d2", "sys_26m", 1,
  42                 2),
  43 };
  44
  45 static const struct mtk_fixed_factor top_divs[] = {
  46         FACTOR(CLK_TOP_ARMCA35PLL, "armca35pll_ck", "armca35pll", 1,
  47                 1),
  48         FACTOR(CLK_TOP_ARMCA35PLL_600M, "armca35pll_600m", "armca35pll_ck", 1,
  49                 2),
  50         FACTOR(CLK_TOP_ARMCA35PLL_400M, "armca35pll_400m", "armca35pll_ck", 1,
  51                 3),
  52         FACTOR(CLK_TOP_ARMCA72PLL, "armca72pll_ck", "armca72pll", 1,
  53                 1),
  54         FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1,
  55                 1),
  56         FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "syspll_ck", 1,
  57                 2),
  58         FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1,
  59                 2),
  60         FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1,
  61                 4),
  62         FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1,
  63                 8),
  64         FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1,
  65                 16),
  66         FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "syspll_ck", 1,
  67                 3),
  68         FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1,
  69                 2),
  70         FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1,
  71                 4),
  72         FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "syspll_ck", 1,
  73                 5),
  74         FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1,
  75                 2),
  76         FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1,
  77                 4),
  78         FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "syspll_ck", 1,
  79                 7),
  80         FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1,
  81                 2),
  82         FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1,
  83                 4),
  84         FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1,
  85                 1),
  86         FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll_ck", 1,
  87                 7),
  88         FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll_ck", 1,
  89                 26),
  90         FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll_ck", 1,
  91                 52),
  92         FACTOR(CLK_TOP_UNIVPLL_D104, "univpll_d104", "univpll_ck", 1,
  93                 104),
  94         FACTOR(CLK_TOP_UNIVPLL_D208, "univpll_d208", "univpll_ck", 1,
  95                 208),
  96         FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll_ck", 1,
  97                 2),
  98         FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1,
  99                 2),
 100         FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1,
 101                 4),
 102         FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1,
 103                 8),
 104         FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll_ck", 1,
 105                 3),
 106         FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1,
 107                 2),
 108         FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1,
 109                 4),
 110         FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1,
 111                 8),
 112         FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll_ck", 1,
 113                 5),
 114         FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1,
 115                 2),
 116         FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1,
 117                 4),
 118         FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1,
 119                 8),
 120         FACTOR(CLK_TOP_F_MP0_PLL1, "f_mp0_pll1_ck", "univpll_d2", 1,
 121                 1),
 122         FACTOR(CLK_TOP_F_MP0_PLL2, "f_mp0_pll2_ck", "univpll1_d2", 1,
 123                 1),
 124         FACTOR(CLK_TOP_F_BIG_PLL1, "f_big_pll1_ck", "univpll_d2", 1,
 125                 1),
 126         FACTOR(CLK_TOP_F_BIG_PLL2, "f_big_pll2_ck", "univpll1_d2", 1,
 127                 1),
 128         FACTOR(CLK_TOP_F_BUS_PLL1, "f_bus_pll1_ck", "univpll_d2", 1,
 129                 1),
 130         FACTOR(CLK_TOP_F_BUS_PLL2, "f_bus_pll2_ck", "univpll1_d2", 1,
 131                 1),
 132         FACTOR(CLK_TOP_APLL1, "apll1_ck", "apll1", 1,
 133                 1),
 134         FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1_ck", 1,
 135                 2),
 136         FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1_ck", 1,
 137                 4),
 138         FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1_ck", 1,
 139                 8),
 140         FACTOR(CLK_TOP_APLL1_D16, "apll1_d16", "apll1_ck", 1,
 141                 16),
 142         FACTOR(CLK_TOP_APLL2, "apll2_ck", "apll2", 1,
 143                 1),
 144         FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2_ck", 1,
 145                 2),
 146         FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2_ck", 1,
 147                 4),
 148         FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2_ck", 1,
 149                 8),
 150         FACTOR(CLK_TOP_APLL2_D16, "apll2_d16", "apll2_ck", 1,
 151                 16),
 152         FACTOR(CLK_TOP_LVDSPLL, "lvdspll_ck", "lvdspll", 1,
 153                 1),
 154         FACTOR(CLK_TOP_LVDSPLL_D2, "lvdspll_d2", "lvdspll_ck", 1,
 155                 2),
 156         FACTOR(CLK_TOP_LVDSPLL_D4, "lvdspll_d4", "lvdspll_ck", 1,
 157                 4),
 158         FACTOR(CLK_TOP_LVDSPLL_D8, "lvdspll_d8", "lvdspll_ck", 1,
 159                 8),
 160         FACTOR(CLK_TOP_LVDSPLL2, "lvdspll2_ck", "lvdspll2", 1,
 161                 1),
 162         FACTOR(CLK_TOP_LVDSPLL2_D2, "lvdspll2_d2", "lvdspll2_ck", 1,
 163                 2),
 164         FACTOR(CLK_TOP_LVDSPLL2_D4, "lvdspll2_d4", "lvdspll2_ck", 1,
 165                 4),
 166         FACTOR(CLK_TOP_LVDSPLL2_D8, "lvdspll2_d8", "lvdspll2_ck", 1,
 167                 8),
 168         FACTOR(CLK_TOP_ETHERPLL_125M, "etherpll_125m", "etherpll", 1,
 169                 1),
 170         FACTOR(CLK_TOP_ETHERPLL_50M, "etherpll_50m", "etherpll", 1,
 171                 1),
 172         FACTOR(CLK_TOP_CVBS, "cvbs", "cvbspll", 1,
 173                 1),
 174         FACTOR(CLK_TOP_CVBS_D2, "cvbs_d2", "cvbs", 1,
 175                 2),
 176         FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1,
 177                 1),
 178         FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll_ck", 1,
 179                 2),
 180         FACTOR(CLK_TOP_VENCPLL, "vencpll_ck", "vencpll", 1,
 181                 1),
 182         FACTOR(CLK_TOP_VENCPLL_D2, "vencpll_d2", "vencpll_ck", 1,
 183                 2),
 184         FACTOR(CLK_TOP_VCODECPLL, "vcodecpll_ck", "vcodecpll", 1,
 185                 1),
 186         FACTOR(CLK_TOP_VCODECPLL_D2, "vcodecpll_d2", "vcodecpll_ck", 1,
 187                 2),
 188         FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1,
 189                 1),
 190         FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll_ck", 1,
 191                 2),
 192         FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll_ck", 1,
 193                 4),
 194         FACTOR(CLK_TOP_TVDPLL_D8, "tvdpll_d8", "tvdpll_ck", 1,
 195                 8),
 196         FACTOR(CLK_TOP_TVDPLL_429M, "tvdpll_429m", "tvdpll", 1,
 197                 1),
 198         FACTOR(CLK_TOP_TVDPLL_429M_D2, "tvdpll_429m_d2", "tvdpll_429m", 1,
 199                 2),
 200         FACTOR(CLK_TOP_TVDPLL_429M_D4, "tvdpll_429m_d4", "tvdpll_429m", 1,
 201                 4),
 202         FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1,
 203                 1),
 204         FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll_ck", 1,
 205                 2),
 206         FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll_ck", 1,
 207                 4),
 208         FACTOR(CLK_TOP_MSDCPLL2, "msdcpll2_ck", "msdcpll2", 1,
 209                 1),
 210         FACTOR(CLK_TOP_MSDCPLL2_D2, "msdcpll2_d2", "msdcpll2_ck", 1,
 211                 2),
 212         FACTOR(CLK_TOP_MSDCPLL2_D4, "msdcpll2_d4", "msdcpll2_ck", 1,
 213                 4),
 214         FACTOR(CLK_TOP_D2A_ULCLK_6P5M, "d2a_ulclk_6p5m", "clk26m", 1,
 215                 4),
 216         FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
 217                 3),
 218         FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
 219                 3),
 220 };
 221
 222 static const char * const axi_parents[] = {
 223         "clk26m",
 224         "syspll1_d2",
 225         "syspll_d5",
 226         "syspll1_d4",
 227         "univpll_d5",
 228         "univpll2_d2",
 229         "msdcpll2_ck"
 230 };
 231
 232 static const char * const mem_parents[] = {
 233         "clk26m",
 234         "dmpll_ck"
 235 };
 236
 237 static const char * const mm_parents[] = {
 238         "clk26m",
 239         "vencpll_ck",
 240         "syspll_d3",
 241         "syspll1_d2",
 242         "syspll_d5",
 243         "syspll1_d4",
 244         "univpll1_d2",
 245         "univpll2_d2"
 246 };
 247
 248 static const char * const pwm_parents[] = {
 249         "clk26m",
 250         "univpll2_d4",
 251         "univpll3_d2",
 252         "univpll1_d4"
 253 };
 254
 255 static const char * const vdec_parents[] = {
 256         "clk26m",
 257         "vcodecpll_ck",
 258         "tvdpll_429m",
 259         "univpll_d3",
 260         "vencpll_ck",
 261         "syspll_d3",
 262         "univpll1_d2",
 263         "mmpll_d2",
 264         "syspll3_d2",
 265         "tvdpll_ck"
 266 };
 267
 268 static const char * const venc_parents[] = {
 269         "clk26m",
 270         "univpll1_d2",
 271         "mmpll_d2",
 272         "tvdpll_d2",
 273         "syspll1_d2",
 274         "univpll_d5",
 275         "vcodecpll_d2",
 276         "univpll2_d2",
 277         "syspll3_d2"
 278 };
 279
 280 static const char * const mfg_parents[] = {
 281         "clk26m",
 282         "mmpll_ck",
 283         "univpll_d3",
 284         "clk26m",
 285         "clk26m",
 286         "clk26m",
 287         "clk26m",
 288         "clk26m",
 289         "clk26m",
 290         "syspll_d3",
 291         "syspll1_d2",
 292         "syspll_d5",
 293         "univpll_d3",
 294         "univpll1_d2",
 295         "univpll_d5",
 296         "univpll2_d2"
 297 };
 298
 299 static const char * const camtg_parents[] = {
 300         "clk26m",
 301         "univpll_d52",
 302         "univpll_d208",
 303         "univpll_d104",
 304         "clk26m_d2",
 305         "univpll_d26",
 306         "univpll2_d8",
 307         "syspll3_d4",
 308         "syspll3_d2",
 309         "univpll1_d4",
 310         "univpll2_d2"
 311 };
 312
 313 static const char * const uart_parents[] = {
 314         "clk26m",
 315         "univpll2_d8"
 316 };
 317
 318 static const char * const spi_parents[] = {
 319         "clk26m",
 320         "univpll2_d4",
 321         "univpll1_d4",
 322         "univpll2_d2",
 323         "univpll3_d2",
 324         "univpll1_d8"
 325 };
 326
 327 static const char * const usb20_parents[] = {
 328         "clk26m",
 329         "univpll1_d8",
 330         "univpll3_d4"
 331 };
 332
 333 static const char * const usb30_parents[] = {
 334         "clk26m",
 335         "univpll3_d2",
 336         "univpll3_d4",
 337         "univpll2_d4"
 338 };
 339
 340 static const char * const msdc50_0_h_parents[] = {
 341         "clk26m",
 342         "syspll1_d2",
 343         "syspll2_d2",
 344         "syspll4_d2",
 345         "univpll_d5",
 346         "univpll1_d4"
 347 };
 348
 349 static const char * const msdc50_0_parents[] = {
 350         "clk26m",
 351         "msdcpll_ck",
 352         "msdcpll_d2",
 353         "univpll1_d4",
 354         "syspll2_d2",
 355         "msdcpll_d4",
 356         "vencpll_d2",
 357         "univpll1_d2",
 358         "msdcpll2_ck",
 359         "msdcpll2_d2",
 360         "msdcpll2_d4"
 361 };
 362
 363 static const char * const msdc30_1_parents[] = {
 364         "clk26m",
 365         "univpll2_d2",
 366         "msdcpll_d2",
 367         "univpll1_d4",
 368         "syspll2_d2",
 369         "univpll_d7",
 370         "vencpll_d2"
 371 };
 372
 373 static const char * const msdc30_3_parents[] = {
 374         "clk26m",
 375         "msdcpll2_ck",
 376         "msdcpll2_d2",
 377         "univpll2_d2",
 378         "msdcpll2_d4",
 379         "univpll1_d4",
 380         "syspll2_d2",
 381         "syspll_d7",
 382         "univpll_d7",
 383         "vencpll_d2",
 384         "msdcpll_ck",
 385         "msdcpll_d2",
 386         "msdcpll_d4"
 387 };
 388
 389 static const char * const audio_parents[] = {
 390         "clk26m",
 391         "syspll3_d4",
 392         "syspll4_d4",
 393         "syspll1_d16"
 394 };
 395
 396 static const char * const aud_intbus_parents[] = {
 397         "clk26m",
 398         "syspll1_d4",
 399         "syspll4_d2",
 400         "univpll3_d2",
 401         "univpll2_d8",
 402         "syspll3_d2",
 403         "syspll3_d4"
 404 };
 405
 406 static const char * const pmicspi_parents[] = {
 407         "clk26m",
 408         "syspll1_d8",
 409         "syspll3_d4",
 410         "syspll1_d16",
 411         "univpll3_d4",
 412         "univpll_d26",
 413         "syspll3_d4"
 414 };
 415
 416 static const char * const dpilvds1_parents[] = {
 417         "clk26m",
 418         "lvdspll2_ck",
 419         "lvdspll2_d2",
 420         "lvdspll2_d4",
 421         "lvdspll2_d8",
 422         "clkfpc"
 423 };
 424
 425 static const char * const atb_parents[] = {
 426         "clk26m",
 427         "syspll1_d2",
 428         "univpll_d5",
 429         "syspll_d5"
 430 };
 431
 432 static const char * const nr_parents[] = {
 433         "clk26m",
 434         "univpll1_d4",
 435         "syspll2_d2",
 436         "syspll1_d4",
 437         "univpll1_d8",
 438         "univpll3_d2",
 439         "univpll2_d2",
 440         "syspll_d5"
 441 };
 442
 443 static const char * const nfi2x_parents[] = {
 444         "clk26m",
 445         "syspll4_d4",
 446         "univpll3_d4",
 447         "univpll1_d8",
 448         "syspll2_d4",
 449         "univpll3_d2",
 450         "syspll_d7",
 451         "syspll2_d2",
 452         "univpll2_d2",
 453         "syspll_d5",
 454         "syspll1_d2"
 455 };
 456
 457 static const char * const irda_parents[] = {
 458         "clk26m",
 459         "univpll2_d4",
 460         "syspll2_d4",
 461         "univpll2_d8"
 462 };
 463
 464 static const char * const cci400_parents[] = {
 465         "clk26m",
 466         "vencpll_ck",
 467         "armca35pll_600m",
 468         "armca35pll_400m",
 469         "univpll_d2",
 470         "syspll_d2",
 471         "msdcpll_ck",
 472         "univpll_d3"
 473 };
 474
 475 static const char * const aud_1_parents[] = {
 476         "clk26m",
 477         "apll1_ck",
 478         "univpll2_d4",
 479         "univpll2_d8"
 480 };
 481
 482 static const char * const aud_2_parents[] = {
 483         "clk26m",
 484         "apll2_ck",
 485         "univpll2_d4",
 486         "univpll2_d8"
 487 };
 488
 489 static const char * const mem_mfg_parents[] = {
 490         "clk26m",
 491         "mmpll_ck",
 492         "univpll_d3"
 493 };
 494
 495 static const char * const axi_mfg_parents[] = {
 496         "clk26m",
 497         "axi_sel",
 498         "univpll_d5"
 499 };
 500
 501 static const char * const scam_parents[] = {
 502         "clk26m",
 503         "syspll3_d2",
 504         "univpll2_d4",
 505         "syspll2_d4"
 506 };
 507
 508 static const char * const nfiecc_parents[] = {
 509         "clk26m",
 510         "nfi2x_sel",
 511         "syspll_d7",
 512         "syspll2_d2",
 513         "univpll2_d2",
 514         "univpll_d5",
 515         "syspll1_d2"
 516 };
 517
 518 static const char * const pe2_mac_p0_parents[] = {
 519         "clk26m",
 520         "syspll1_d8",
 521         "syspll4_d2",
 522         "syspll2_d4",
 523         "univpll2_d4",
 524         "syspll3_d2"
 525 };
 526
 527 static const char * const dpilvds_parents[] = {
 528         "clk26m",
 529         "lvdspll_ck",
 530         "lvdspll_d2",
 531         "lvdspll_d4",
 532         "lvdspll_d8",
 533         "clkfpc"
 534 };
 535
 536 static const char * const hdcp_parents[] = {
 537         "clk26m",
 538         "syspll4_d2",
 539         "syspll3_d4",
 540         "univpll2_d4"
 541 };
 542
 543 static const char * const hdcp_24m_parents[] = {
 544         "clk26m",
 545         "univpll_d26",
 546         "univpll_d52",
 547         "univpll2_d8"
 548 };
 549
 550 static const char * const rtc_parents[] = {
 551         "clkrtc_int",
 552         "clkrtc_ext",
 553         "clk26m",
 554         "univpll3_d8"
 555 };
 556
 557 static const char * const spinor_parents[] = {
 558         "clk26m",
 559         "clk26m_d2",
 560         "syspll4_d4",
 561         "univpll2_d8",
 562         "univpll3_d4",
 563         "syspll4_d2",
 564         "syspll2_d4",
 565         "univpll2_d4",
 566         "etherpll_125m",
 567         "syspll1_d4"
 568 };
 569
 570 static const char * const apll_parents[] = {
 571         "clk26m",
 572         "apll1_ck",
 573         "apll1_d2",
 574         "apll1_d4",
 575         "apll1_d8",
 576         "apll1_d16",
 577         "apll2_ck",
 578         "apll2_d2",
 579         "apll2_d4",
 580         "apll2_d8",
 581         "apll2_d16",
 582         "clk26m",
 583         "clk26m"
 584 };
 585
 586 static const char * const a1sys_hp_parents[] = {
 587         "clk26m",
 588         "apll1_ck",
 589         "apll1_d2",
 590         "apll1_d4",
 591         "apll1_d8",
 592         "apll1_d3"
 593 };
 594
 595 static const char * const a2sys_hp_parents[] = {
 596         "clk26m",
 597         "apll2_ck",
 598         "apll2_d2",
 599         "apll2_d4",
 600         "apll2_d8",
 601         "apll2_d3"
 602 };
 603
 604 static const char * const asm_l_parents[] = {
 605         "clk26m",
 606         "univpll2_d4",
 607         "univpll2_d2",
 608         "syspll_d5"
 609 };
 610
 611 static const char * const i2so1_parents[] = {
 612         "clk26m",
 613         "apll1_ck",
 614         "apll2_ck"
 615 };
 616
 617 static const char * const ether_125m_parents[] = {
 618         "clk26m",
 619         "etherpll_125m",
 620         "univpll3_d2"
 621 };
 622
 623 static const char * const ether_50m_parents[] = {
 624         "clk26m",
 625         "etherpll_50m",
 626         "apll1_d3",
 627         "univpll3_d4"
 628 };
 629
 630 static const char * const jpgdec_parents[] = {
 631         "clk26m",
 632         "univpll_d3",
 633         "tvdpll_429m",
 634         "vencpll_ck",
 635         "syspll_d3",
 636         "vcodecpll_ck",
 637         "univpll1_d2",
 638         "armca35pll_400m",
 639         "tvdpll_429m_d2",
 640         "tvdpll_429m_d4"
 641 };
 642
 643 static const char * const spislv_parents[] = {
 644         "clk26m",
 645         "univpll2_d4",
 646         "univpll1_d4",
 647         "univpll2_d2",
 648         "univpll3_d2",
 649         "univpll1_d8",
 650         "univpll1_d2",
 651         "univpll_d5"
 652 };
 653
 654 static const char * const ether_parents[] = {
 655         "clk26m",
 656         "etherpll_50m",
 657         "univpll_d26"
 658 };
 659
 660 static const char * const di_parents[] = {
 661         "clk26m",
 662         "tvdpll_d2",
 663         "tvdpll_d4",
 664         "tvdpll_d8",
 665         "vencpll_ck",
 666         "vencpll_d2",
 667         "cvbs",
 668         "cvbs_d2"
 669 };
 670
 671 static const char * const tvd_parents[] = {
 672         "clk26m",
 673         "cvbs_d2",
 674         "univpll2_d8"
 675 };
 676
 677 static const char * const i2c_parents[] = {
 678         "clk26m",
 679         "univpll_d26",
 680         "univpll2_d4",
 681         "univpll3_d2",
 682         "univpll1_d4"
 683 };
 684
 685 static const char * const msdc0p_aes_parents[] = {
 686         "clk26m",
 687         "syspll_d2",
 688         "univpll_d3",
 689         "vcodecpll_ck"
 690 };
 691
 692 static const char * const cmsys_parents[] = {
 693         "clk26m",
 694         "univpll_d3",
 695         "syspll_d3",
 696         "syspll1_d2",
 697         "syspll2_d2"
 698 };
 699
 700 static const char * const gcpu_parents[] = {
 701         "clk26m",
 702         "syspll_d3",
 703         "syspll1_d2",
 704         "univpll1_d2",
 705         "univpll_d5",
 706         "univpll3_d2",
 707         "univpll_d3"
 708 };
 709
 710 static const char * const aud_apll1_parents[] = {
 711         "apll1",
 712         "clkaud_ext_i_1"
 713 };
 714
 715 static const char * const aud_apll2_parents[] = {
 716         "apll2",
 717         "clkaud_ext_i_2"
 718 };
 719
 720 static const char * const apll1_ref_parents[] = {
 721         "clkaud_ext_i_2",
 722         "clkaud_ext_i_1",
 723         "clki2si0_mck_i",
 724         "clki2si1_mck_i",
 725         "clki2si2_mck_i",
 726         "clktdmin_mclk_i",
 727         "clki2si2_mck_i",
 728         "clktdmin_mclk_i"
 729 };
 730
 731 static const char * const audull_vtx_parents[] = {
 732         "d2a_ulclk_6p5m",
 733         "clkaud_ext_i_0"
 734 };
 735
 736 static struct mtk_composite top_muxes[] = {
 737         /* CLK_CFG_0 */
 738         MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents, 0x040, 0, 3,
 739                 7, CLK_IS_CRITICAL),
 740         MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
 741                 15, CLK_IS_CRITICAL),
 742         MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
 743                 mm_parents, 0x040, 24, 3, 31),
 744         /* CLK_CFG_1 */
 745         MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel",
 746                 pwm_parents, 0x050, 0, 2, 7),
 747         MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel",
 748                 vdec_parents, 0x050, 8, 4, 15),
 749         MUX_GATE(CLK_TOP_VENC_SEL, "venc_sel",
 750                 venc_parents, 0x050, 16, 4, 23),
 751         MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel",
 752                 mfg_parents, 0x050, 24, 4, 31),
 753         /* CLK_CFG_2 */
 754         MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel",
 755                 camtg_parents, 0x060, 0, 4, 7),
 756         MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
 757                 uart_parents, 0x060, 8, 1, 15),
 758         MUX_GATE(CLK_TOP_SPI_SEL, "spi_sel",
 759                 spi_parents, 0x060, 16, 3, 23),
 760         MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel",
 761                 usb20_parents, 0x060, 24, 2, 31),
 762         /* CLK_CFG_3 */
 763         MUX_GATE(CLK_TOP_USB30_SEL, "usb30_sel",
 764                 usb30_parents, 0x070, 0, 2, 7),
 765         MUX_GATE(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc50_0_h_sel",
 766                 msdc50_0_h_parents, 0x070, 8, 3, 15),
 767         MUX_GATE(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
 768                 msdc50_0_parents, 0x070, 16, 4, 23),
 769         MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
 770                 msdc30_1_parents, 0x070, 24, 3, 31),
 771         /* CLK_CFG_4 */
 772         MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
 773                 msdc30_1_parents, 0x080, 0, 3, 7),
 774         MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel",
 775                 msdc30_3_parents, 0x080, 8, 4, 15),
 776         MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel",
 777                 audio_parents, 0x080, 16, 2, 23),
 778         MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
 779                 aud_intbus_parents, 0x080, 24, 3, 31),
 780         /* CLK_CFG_5 */
 781         MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel",
 782                 pmicspi_parents, 0x090, 0, 3, 7),
 783         MUX_GATE(CLK_TOP_DPILVDS1_SEL, "dpilvds1_sel",
 784                 dpilvds1_parents, 0x090, 8, 3, 15),
 785         MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel",
 786                 atb_parents, 0x090, 16, 2, 23),
 787         MUX_GATE(CLK_TOP_NR_SEL, "nr_sel",
 788                 nr_parents, 0x090, 24, 3, 31),
 789         /* CLK_CFG_6 */
 790         MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel",
 791                 nfi2x_parents, 0x0a0, 0, 4, 7),
 792         MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel",
 793                 irda_parents, 0x0a0, 8, 2, 15),
 794         MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel",
 795                 cci400_parents, 0x0a0, 16, 3, 23),
 796         MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel",
 797                 aud_1_parents, 0x0a0, 24, 2, 31),
 798         /* CLK_CFG_7 */
 799         MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
 800                 aud_2_parents, 0x0b0, 0, 2, 7),
 801         MUX_GATE(CLK_TOP_MEM_MFG_IN_AS_SEL, "mem_mfg_sel",
 802                 mem_mfg_parents, 0x0b0, 8, 2, 15),
 803         MUX_GATE(CLK_TOP_AXI_MFG_IN_AS_SEL, "axi_mfg_sel",
 804                 axi_mfg_parents, 0x0b0, 16, 2, 23),
 805         MUX_GATE(CLK_TOP_SCAM_SEL, "scam_sel",
 806                 scam_parents, 0x0b0, 24, 2, 31),
 807         /* CLK_CFG_8 */
 808         MUX_GATE(CLK_TOP_NFIECC_SEL, "nfiecc_sel",
 809                 nfiecc_parents, 0x0c0, 0, 3, 7),
 810         MUX_GATE(CLK_TOP_PE2_MAC_P0_SEL, "pe2_mac_p0_sel",
 811                 pe2_mac_p0_parents, 0x0c0, 8, 3, 15),
 812         MUX_GATE(CLK_TOP_PE2_MAC_P1_SEL, "pe2_mac_p1_sel",
 813                 pe2_mac_p0_parents, 0x0c0, 16, 3, 23),
 814         MUX_GATE(CLK_TOP_DPILVDS_SEL, "dpilvds_sel",
 815                 dpilvds_parents, 0x0c0, 24, 3, 31),
 816         /* CLK_CFG_9 */
 817         MUX_GATE(CLK_TOP_MSDC50_3_HCLK_SEL, "msdc50_3_h_sel",
 818                 msdc50_0_h_parents, 0x0d0, 0, 3, 7),
 819         MUX_GATE(CLK_TOP_HDCP_SEL, "hdcp_sel",
 820                 hdcp_parents, 0x0d0, 8, 2, 15),
 821         MUX_GATE(CLK_TOP_HDCP_24M_SEL, "hdcp_24m_sel",
 822                 hdcp_24m_parents, 0x0d0, 16, 2, 23),
 823         MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x0d0, 24, 2,
 824                 31, CLK_IS_CRITICAL),
 825         /* CLK_CFG_10 */
 826         MUX_GATE(CLK_TOP_SPINOR_SEL, "spinor_sel",
 827                 spinor_parents, 0x500, 0, 4, 7),
 828         MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel",
 829                 apll_parents, 0x500, 8, 4, 15),
 830         MUX_GATE(CLK_TOP_APLL2_SEL, "apll2_sel",
 831                 apll_parents, 0x500, 16, 4, 23),
 832         MUX_GATE(CLK_TOP_A1SYS_HP_SEL, "a1sys_hp_sel",
 833                 a1sys_hp_parents, 0x500, 24, 3, 31),
 834         /* CLK_CFG_11 */
 835         MUX_GATE(CLK_TOP_A2SYS_HP_SEL, "a2sys_hp_sel",
 836                 a2sys_hp_parents, 0x510, 0, 3, 7),
 837         MUX_GATE(CLK_TOP_ASM_L_SEL, "asm_l_sel",
 838                 asm_l_parents, 0x510, 8, 2, 15),
 839         MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel",
 840                 asm_l_parents, 0x510, 16, 2, 23),
 841         MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel",
 842                 asm_l_parents, 0x510, 24, 2, 31),
 843         /* CLK_CFG_12 */
 844         MUX_GATE(CLK_TOP_I2SO1_SEL, "i2so1_sel",
 845                 i2so1_parents, 0x520, 0, 2, 7),
 846         MUX_GATE(CLK_TOP_I2SO2_SEL, "i2so2_sel",
 847                 i2so1_parents, 0x520, 8, 2, 15),
 848         MUX_GATE(CLK_TOP_I2SO3_SEL, "i2so3_sel",
 849                 i2so1_parents, 0x520, 16, 2, 23),
 850         MUX_GATE(CLK_TOP_TDMO0_SEL, "tdmo0_sel",
 851                 i2so1_parents, 0x520, 24, 2, 31),
 852         /* CLK_CFG_13 */
 853         MUX_GATE(CLK_TOP_TDMO1_SEL, "tdmo1_sel",
 854                 i2so1_parents, 0x530, 0, 2, 7),
 855         MUX_GATE(CLK_TOP_I2SI1_SEL, "i2si1_sel",
 856                 i2so1_parents, 0x530, 8, 2, 15),
 857         MUX_GATE(CLK_TOP_I2SI2_SEL, "i2si2_sel",
 858                 i2so1_parents, 0x530, 16, 2, 23),
 859         MUX_GATE(CLK_TOP_I2SI3_SEL, "i2si3_sel",
 860                 i2so1_parents, 0x530, 24, 2, 31),
 861         /* CLK_CFG_14 */
 862         MUX_GATE(CLK_TOP_ETHER_125M_SEL, "ether_125m_sel",
 863                 ether_125m_parents, 0x540, 0, 2, 7),
 864         MUX_GATE(CLK_TOP_ETHER_50M_SEL, "ether_50m_sel",
 865                 ether_50m_parents, 0x540, 8, 2, 15),
 866         MUX_GATE(CLK_TOP_JPGDEC_SEL, "jpgdec_sel",
 867                 jpgdec_parents, 0x540, 16, 4, 23),
 868         MUX_GATE(CLK_TOP_SPISLV_SEL, "spislv_sel",
 869                 spislv_parents, 0x540, 24, 3, 31),
 870         /* CLK_CFG_15 */
 871         MUX_GATE(CLK_TOP_ETHER_50M_RMII_SEL, "ether_sel",
 872                 ether_parents, 0x550, 0, 2, 7),
 873         MUX_GATE(CLK_TOP_CAM2TG_SEL, "cam2tg_sel",
 874                 camtg_parents, 0x550, 8, 4, 15),
 875         MUX_GATE(CLK_TOP_DI_SEL, "di_sel",
 876                 di_parents, 0x550, 16, 3, 23),
 877         MUX_GATE(CLK_TOP_TVD_SEL, "tvd_sel",
 878                 tvd_parents, 0x550, 24, 2, 31),
 879         /* CLK_CFG_16 */
 880         MUX_GATE(CLK_TOP_I2C_SEL, "i2c_sel",
 881                 i2c_parents, 0x560, 0, 3, 7),
 882         MUX_GATE(CLK_TOP_PWM_INFRA_SEL, "pwm_infra_sel",
 883                 pwm_parents, 0x560, 8, 2, 15),
 884         MUX_GATE(CLK_TOP_MSDC0P_AES_SEL, "msdc0p_aes_sel",
 885                 msdc0p_aes_parents, 0x560, 16, 2, 23),
 886         MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel",
 887                 cmsys_parents, 0x560, 24, 3, 31),
 888         /* CLK_CFG_17 */
 889         MUX_GATE(CLK_TOP_GCPU_SEL, "gcpu_sel",
 890                 gcpu_parents, 0x570, 0, 3, 7),
 891         /* CLK_AUDDIV_4 */
 892         MUX(CLK_TOP_AUD_APLL1_SEL, "aud_apll1_sel",
 893                 aud_apll1_parents, 0x134, 0, 1),
 894         MUX(CLK_TOP_AUD_APLL2_SEL, "aud_apll2_sel",
 895                 aud_apll2_parents, 0x134, 1, 1),
 896         MUX(CLK_TOP_DA_AUDULL_VTX_6P5M_SEL, "audull_vtx_sel",
 897                 audull_vtx_parents, 0x134, 31, 1),
 898         MUX(CLK_TOP_APLL1_REF_SEL, "apll1_ref_sel",
 899                 apll1_ref_parents, 0x134, 4, 3),
 900         MUX(CLK_TOP_APLL2_REF_SEL, "apll2_ref_sel",
 901                 apll1_ref_parents, 0x134, 7, 3),
 902 };
 903
 904 static const char * const mcu_mp0_parents[] = {
 905         "clk26m",
 906         "armca35pll_ck",
 907         "f_mp0_pll1_ck",
 908         "f_mp0_pll2_ck"
 909 };
 910
 911 static const char * const mcu_mp2_parents[] = {
 912         "clk26m",
 913         "armca72pll_ck",
 914         "f_big_pll1_ck",
 915         "f_big_pll2_ck"
 916 };
 917
 918 static const char * const mcu_bus_parents[] = {
 919         "clk26m",
 920         "cci400_sel",
 921         "f_bus_pll1_ck",
 922         "f_bus_pll2_ck"
 923 };
 924
 925 static struct mtk_composite mcu_muxes[] = {
 926         /* mp0_pll_divider_cfg */
 927         MUX_GATE_FLAGS(CLK_MCU_MP0_SEL, "mcu_mp0_sel", mcu_mp0_parents, 0x7A0,
 928                 9, 2, -1, CLK_IS_CRITICAL),
 929         /* mp2_pll_divider_cfg */
 930         MUX_GATE_FLAGS(CLK_MCU_MP2_SEL, "mcu_mp2_sel", mcu_mp2_parents, 0x7A8,
 931                 9, 2, -1, CLK_IS_CRITICAL),
 932         /* bus_pll_divider_cfg */
 933         MUX_GATE_FLAGS(CLK_MCU_BUS_SEL, "mcu_bus_sel", mcu_bus_parents, 0x7C0,
 934                 9, 2, -1, CLK_IS_CRITICAL),
 935 };
 936
 937 static const struct mtk_clk_divider top_adj_divs[] = {
 938         DIV_ADJ(CLK_TOP_APLL_DIV0, "apll_div0", "i2so1_sel", 0x124, 0, 8),
 939         DIV_ADJ(CLK_TOP_APLL_DIV1, "apll_div1", "i2so2_sel", 0x124, 8, 8),
 940         DIV_ADJ(CLK_TOP_APLL_DIV2, "apll_div2", "i2so3_sel", 0x124, 16, 8),
 941         DIV_ADJ(CLK_TOP_APLL_DIV3, "apll_div3", "tdmo0_sel", 0x124, 24, 8),
 942         DIV_ADJ(CLK_TOP_APLL_DIV4, "apll_div4", "tdmo1_sel", 0x128, 0, 8),
 943         DIV_ADJ(CLK_TOP_APLL_DIV5, "apll_div5", "i2si1_sel", 0x128, 8, 8),
 944         DIV_ADJ(CLK_TOP_APLL_DIV6, "apll_div6", "i2si2_sel", 0x128, 16, 8),
 945         DIV_ADJ(CLK_TOP_APLL_DIV7, "apll_div7", "i2si3_sel", 0x128, 24, 8),
 946 };
 947
 948 static const struct mtk_gate_regs top0_cg_regs = {
 949         .set_ofs = 0x120,
 950         .clr_ofs = 0x120,
 951         .sta_ofs = 0x120,
 952 };
 953
 954 static const struct mtk_gate_regs top1_cg_regs = {
 955         .set_ofs = 0x424,
 956         .clr_ofs = 0x424,
 957         .sta_ofs = 0x424,
 958 };
 959
 960 #define GATE_TOP0(_id, _name, _parent, _shift) {        \
 961                 .id = _id,                              \
 962                 .name = _name,                          \
 963                 .parent_name = _parent,                 \
 964                 .regs = &top0_cg_regs,                  \
 965                 .shift = _shift,                        \
 966                 .ops = &mtk_clk_gate_ops_no_setclr,     \
 967         }
 968
 969 #define GATE_TOP1(_id, _name, _parent, _shift) {        \
 970                 .id = _id,                              \
 971                 .name = _name,                          \
 972                 .parent_name = _parent,                 \
 973                 .regs = &top1_cg_regs,                  \
 974                 .shift = _shift,                        \
 975                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
 976         }
 977
 978 static const struct mtk_gate top_clks[] = {
 979         /* TOP0 */
 980         GATE_TOP0(CLK_TOP_APLL_DIV_PDN0, "apll_div_pdn0", "i2so1_sel", 0),
 981         GATE_TOP0(CLK_TOP_APLL_DIV_PDN1, "apll_div_pdn1", "i2so2_sel", 1),
 982         GATE_TOP0(CLK_TOP_APLL_DIV_PDN2, "apll_div_pdn2", "i2so3_sel", 2),
 983         GATE_TOP0(CLK_TOP_APLL_DIV_PDN3, "apll_div_pdn3", "tdmo0_sel", 3),
 984         GATE_TOP0(CLK_TOP_APLL_DIV_PDN4, "apll_div_pdn4", "tdmo1_sel", 4),
 985         GATE_TOP0(CLK_TOP_APLL_DIV_PDN5, "apll_div_pdn5", "i2si1_sel", 5),
 986         GATE_TOP0(CLK_TOP_APLL_DIV_PDN6, "apll_div_pdn6", "i2si2_sel", 6),
 987         GATE_TOP0(CLK_TOP_APLL_DIV_PDN7, "apll_div_pdn7", "i2si3_sel", 7),
 988         /* TOP1 */
 989         GATE_TOP1(CLK_TOP_NFI2X_EN, "nfi2x_en", "nfi2x_sel", 0),
 990         GATE_TOP1(CLK_TOP_NFIECC_EN, "nfiecc_en", "nfiecc_sel", 1),
 991         GATE_TOP1(CLK_TOP_NFI1X_CK_EN, "nfi1x_ck_en", "nfi2x_sel", 2),
 992 };
 993
 994 static const struct mtk_gate_regs infra_cg_regs = {
 995         .set_ofs = 0x40,
 996         .clr_ofs = 0x44,
 997         .sta_ofs = 0x48,
 998 };
 999
1000 #define GATE_INFRA(_id, _name, _parent, _shift) {       \
1001                 .id = _id,                              \
1002                 .name = _name,                          \
1003                 .parent_name = _parent,                 \
1004                 .regs = &infra_cg_regs,                 \
1005                 .shift = _shift,                        \
1006                 .ops = &mtk_clk_gate_ops_setclr,        \
1007         }
1008
1009 static const struct mtk_gate infra_clks[] = {
1010         GATE_INFRA(CLK_INFRA_DBGCLK, "infra_dbgclk", "axi_sel", 0),
1011         GATE_INFRA(CLK_INFRA_GCE, "infra_gce", "axi_sel", 6),
1012         GATE_INFRA(CLK_INFRA_M4U, "infra_m4u", "mem_sel", 8),
1013         GATE_INFRA(CLK_INFRA_KP, "infra_kp", "axi_sel", 16),
1014         GATE_INFRA(CLK_INFRA_AO_SPI0, "infra_ao_spi0", "spi_sel", 24),
1015         GATE_INFRA(CLK_INFRA_AO_SPI1, "infra_ao_spi1", "spislv_sel", 25),
1016         GATE_INFRA(CLK_INFRA_AO_UART5, "infra_ao_uart5", "axi_sel", 26),
1017 };
1018
1019 static const struct mtk_gate_regs peri0_cg_regs = {
1020         .set_ofs = 0x8,
1021         .clr_ofs = 0x10,
1022         .sta_ofs = 0x18,
1023 };
1024
1025 static const struct mtk_gate_regs peri1_cg_regs = {
1026         .set_ofs = 0xc,
1027         .clr_ofs = 0x14,
1028         .sta_ofs = 0x1c,
1029 };
1030
1031 static const struct mtk_gate_regs peri2_cg_regs = {
1032         .set_ofs = 0x42c,
1033         .clr_ofs = 0x42c,
1034         .sta_ofs = 0x42c,
1035 };
1036
1037 #define GATE_PERI0(_id, _name, _parent, _shift) {       \
1038                 .id = _id,                              \
1039                 .name = _name,                          \
1040                 .parent_name = _parent,                 \
1041                 .regs = &peri0_cg_regs,                 \
1042                 .shift = _shift,                        \
1043                 .ops = &mtk_clk_gate_ops_setclr,        \
1044         }
1045
1046 #define GATE_PERI1(_id, _name, _parent, _shift) {       \
1047                 .id = _id,                              \
1048                 .name = _name,                          \
1049                 .parent_name = _parent,                 \
1050                 .regs = &peri1_cg_regs,                 \
1051                 .shift = _shift,                        \
1052                 .ops = &mtk_clk_gate_ops_setclr,        \
1053         }
1054
1055 #define GATE_PERI2(_id, _name, _parent, _shift) {       \
1056                 .id = _id,                              \
1057                 .name = _name,                          \
1058                 .parent_name = _parent,                 \
1059                 .regs = &peri2_cg_regs,                 \
1060                 .shift = _shift,                        \
1061                 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1062         }
1063
1064 static const struct mtk_gate peri_clks[] = {
1065         /* PERI0 */
1066         GATE_PERI0(CLK_PERI_NFI, "per_nfi",
1067                 "axi_sel", 0),
1068         GATE_PERI0(CLK_PERI_THERM, "per_therm",
1069                 "axi_sel", 1),
1070         GATE_PERI0(CLK_PERI_PWM0, "per_pwm0",
1071                 "pwm_sel", 2),
1072         GATE_PERI0(CLK_PERI_PWM1, "per_pwm1",
1073                 "pwm_sel", 3),
1074         GATE_PERI0(CLK_PERI_PWM2, "per_pwm2",
1075                 "pwm_sel", 4),
1076         GATE_PERI0(CLK_PERI_PWM3, "per_pwm3",
1077                 "pwm_sel", 5),
1078         GATE_PERI0(CLK_PERI_PWM4, "per_pwm4",
1079                 "pwm_sel", 6),
1080         GATE_PERI0(CLK_PERI_PWM5, "per_pwm5",
1081                 "pwm_sel", 7),
1082         GATE_PERI0(CLK_PERI_PWM6, "per_pwm6",
1083                 "pwm_sel", 8),
1084         GATE_PERI0(CLK_PERI_PWM7, "per_pwm7",
1085                 "pwm_sel", 9),
1086         GATE_PERI0(CLK_PERI_PWM, "per_pwm",
1087                 "pwm_sel", 10),
1088         GATE_PERI0(CLK_PERI_AP_DMA, "per_ap_dma",
1089                 "axi_sel", 13),
1090         GATE_PERI0(CLK_PERI_MSDC30_0, "per_msdc30_0",
1091                 "msdc50_0_sel", 14),
1092         GATE_PERI0(CLK_PERI_MSDC30_1, "per_msdc30_1",
1093                 "msdc30_1_sel", 15),
1094         GATE_PERI0(CLK_PERI_MSDC30_2, "per_msdc30_2",
1095                 "msdc30_2_sel", 16),
1096         GATE_PERI0(CLK_PERI_MSDC30_3, "per_msdc30_3",
1097                 "msdc30_3_sel", 17),
1098         GATE_PERI0(CLK_PERI_UART0, "per_uart0",
1099                 "uart_sel", 20),
1100         GATE_PERI0(CLK_PERI_UART1, "per_uart1",
1101                 "uart_sel", 21),
1102         GATE_PERI0(CLK_PERI_UART2, "per_uart2",
1103                 "uart_sel", 22),
1104         GATE_PERI0(CLK_PERI_UART3, "per_uart3",
1105                 "uart_sel", 23),
1106         GATE_PERI0(CLK_PERI_I2C0, "per_i2c0",
1107                 "axi_sel", 24),
1108         GATE_PERI0(CLK_PERI_I2C1, "per_i2c1",
1109                 "axi_sel", 25),
1110         GATE_PERI0(CLK_PERI_I2C2, "per_i2c2",
1111                 "axi_sel", 26),
1112         GATE_PERI0(CLK_PERI_I2C3, "per_i2c3",
1113                 "axi_sel", 27),
1114         GATE_PERI0(CLK_PERI_I2C4, "per_i2c4",
1115                 "axi_sel", 28),
1116         GATE_PERI0(CLK_PERI_AUXADC, "per_auxadc",
1117                 "ltepll_fs26m", 29),
1118         GATE_PERI0(CLK_PERI_SPI0, "per_spi0",
1119                 "spi_sel", 30),
1120         /* PERI1 */
1121         GATE_PERI1(CLK_PERI_SPI, "per_spi",
1122                 "spinor_sel", 1),
1123         GATE_PERI1(CLK_PERI_I2C5, "per_i2c5",
1124                 "axi_sel", 3),
1125         GATE_PERI1(CLK_PERI_SPI2, "per_spi2",
1126                 "spi_sel", 5),
1127         GATE_PERI1(CLK_PERI_SPI3, "per_spi3",
1128                 "spi_sel", 6),
1129         GATE_PERI1(CLK_PERI_SPI5, "per_spi5",
1130                 "spi_sel", 8),
1131         GATE_PERI1(CLK_PERI_UART4, "per_uart4",
1132                 "uart_sel", 9),
1133         GATE_PERI1(CLK_PERI_SFLASH, "per_sflash",
1134                 "uart_sel", 11),
1135         GATE_PERI1(CLK_PERI_GMAC, "per_gmac",
1136                 "uart_sel", 12),
1137         GATE_PERI1(CLK_PERI_PCIE0, "per_pcie0",
1138                 "uart_sel", 14),
1139         GATE_PERI1(CLK_PERI_PCIE1, "per_pcie1",
1140                 "uart_sel", 15),
1141         GATE_PERI1(CLK_PERI_GMAC_PCLK, "per_gmac_pclk",
1142                 "uart_sel", 16),
1143         /* PERI2 */
1144         GATE_PERI2(CLK_PERI_MSDC50_0_EN, "per_msdc50_0_en",
1145                 "msdc50_0_sel", 0),
1146         GATE_PERI2(CLK_PERI_MSDC30_1_EN, "per_msdc30_1_en",
1147                 "msdc30_1_sel", 1),
1148         GATE_PERI2(CLK_PERI_MSDC30_2_EN, "per_msdc30_2_en",
1149                 "msdc30_2_sel", 2),
1150         GATE_PERI2(CLK_PERI_MSDC30_3_EN, "per_msdc30_3_en",
1151                 "msdc30_3_sel", 3),
1152         GATE_PERI2(CLK_PERI_MSDC50_0_HCLK_EN, "per_msdc50_0_h",
1153                 "msdc50_0_h_sel", 4),
1154         GATE_PERI2(CLK_PERI_MSDC50_3_HCLK_EN, "per_msdc50_3_h",
1155                 "msdc50_3_h_sel", 5),
1156         GATE_PERI2(CLK_PERI_MSDC30_0_QTR_EN, "per_msdc30_0_q",
1157                 "axi_sel", 6),
1158         GATE_PERI2(CLK_PERI_MSDC30_3_QTR_EN, "per_msdc30_3_q",
1159                 "mem_sel", 7),
1160 };
1161
1162 #define MT2712_PLL_FMAX         (3000UL * MHZ)
1163
1164 #define CON0_MT2712_RST_BAR     BIT(24)
1165
1166 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,   \
1167                         _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
1168                         _tuner_en_bit, _pcw_reg, _pcw_shift,            \
1169                         _div_table) {                                   \
1170                 .id = _id,                                              \
1171                 .name = _name,                                          \
1172                 .reg = _reg,                                            \
1173                 .pwr_reg = _pwr_reg,                                    \
1174                 .en_mask = _en_mask,                                    \
1175                 .flags = _flags,                                        \
1176                 .rst_bar_mask = CON0_MT2712_RST_BAR,                    \
1177                 .fmax = MT2712_PLL_FMAX,                                \
1178                 .pcwbits = _pcwbits,                                    \
1179                 .pd_reg = _pd_reg,                                      \
1180                 .pd_shift = _pd_shift,                                  \
1181                 .tuner_reg = _tuner_reg,                                \
1182                 .tuner_en_reg = _tuner_en_reg,                          \
1183                 .tuner_en_bit = _tuner_en_bit,                          \
1184                 .pcw_reg = _pcw_reg,                                    \
1185                 .pcw_shift = _pcw_shift,                                \
1186                 .div_table = _div_table,                                \
1187         }
1188
1189 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,     \
1190                         _pd_reg, _pd_shift, _tuner_reg, _tuner_en_reg,  \
1191                         _tuner_en_bit, _pcw_reg, _pcw_shift)            \
1192                 PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags,     \
1193                         _pcwbits, _pd_reg, _pd_shift, _tuner_reg,       \
1194                         _tuner_en_reg, _tuner_en_bit, _pcw_reg,         \
1195                         _pcw_shift, NULL)
1196
1197 static const struct mtk_pll_div_table armca35pll_div_table[] = {
1198         { .div = 0, .freq = MT2712_PLL_FMAX },
1199         { .div = 1, .freq = 1202500000 },
1200         { .div = 2, .freq = 500500000 },
1201         { .div = 3, .freq = 315250000 },
1202         { .div = 4, .freq = 157625000 },
1203         { } /* sentinel */
1204 };
1205
1206 static const struct mtk_pll_div_table armca72pll_div_table[] = {
1207         { .div = 0, .freq = MT2712_PLL_FMAX },
1208         { .div = 1, .freq = 994500000 },
1209         { .div = 2, .freq = 520000000 },
1210         { .div = 3, .freq = 315250000 },
1211         { .div = 4, .freq = 157625000 },
1212         { } /* sentinel */
1213 };
1214
1215 static const struct mtk_pll_div_table mmpll_div_table[] = {
1216         { .div = 0, .freq = MT2712_PLL_FMAX },
1217         { .div = 1, .freq = 1001000000 },
1218         { .div = 2, .freq = 601250000 },
1219         { .div = 3, .freq = 250250000 },
1220         { .div = 4, .freq = 125125000 },
1221         { } /* sentinel */
1222 };
1223
1224 static const struct mtk_pll_data plls[] = {
1225         PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000101,
1226                 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
1227         PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000101,
1228                 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
1229         PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000101,
1230                 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
1231         PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000101,
1232                 0, 31, 0x0280, 4, 0, 0, 0, 0x0284, 0),
1233         PLL(CLK_APMIXED_APLL1, "apll1", 0x0330, 0x0340, 0x00000101,
1234                 0, 31, 0x0330, 4, 0x0338, 0x0014, 0, 0x0334, 0),
1235         PLL(CLK_APMIXED_APLL2, "apll2", 0x0350, 0x0360, 0x00000101,
1236                 0, 31, 0x0350, 4, 0x0358, 0x0014, 1, 0x0354, 0),
1237         PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x0370, 0x037c, 0x00000101,
1238                 0, 31, 0x0370, 4, 0, 0, 0, 0x0374, 0),
1239         PLL(CLK_APMIXED_LVDSPLL2, "lvdspll2", 0x0390, 0x039C, 0x00000101,
1240                 0, 31, 0x0390, 4, 0, 0, 0, 0x0394, 0),
1241         PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0270, 0x027C, 0x00000101,
1242                 0, 31, 0x0270, 4, 0, 0, 0, 0x0274, 0),
1243         PLL(CLK_APMIXED_MSDCPLL2, "msdcpll2", 0x0410, 0x041C, 0x00000101,
1244                 0, 31, 0x0410, 4, 0, 0, 0, 0x0414, 0),
1245         PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x0290, 0x029C, 0xc0000101,
1246                 0, 31, 0x0290, 4, 0, 0, 0, 0x0294, 0),
1247         PLL_B(CLK_APMIXED_MMPLL, "mmpll", 0x0250, 0x0260, 0x00000101,
1248                 0, 31, 0x0250, 4, 0, 0, 0, 0x0254, 0,
1249                 mmpll_div_table),
1250         PLL_B(CLK_APMIXED_ARMCA35PLL, "armca35pll", 0x0100, 0x0110, 0xf0000101,
1251                 HAVE_RST_BAR, 31, 0x0100, 4, 0, 0, 0, 0x0104, 0,
1252                 armca35pll_div_table),
1253         PLL_B(CLK_APMIXED_ARMCA72PLL, "armca72pll", 0x0210, 0x0220, 0x00000101,
1254                 0, 31, 0x0210, 4, 0, 0, 0, 0x0214, 0,
1255                 armca72pll_div_table),
1256         PLL(CLK_APMIXED_ETHERPLL, "etherpll", 0x0300, 0x030C, 0xc0000101,
1257                 0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1258 };
1259
1260 static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1261 {
1262         struct clk_onecell_data *clk_data;
1263         int r;
1264         struct device_node *node = pdev->dev.of_node;
1265
1266         clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
1267
1268         mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
1269
1270         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1271
1272         if (r != 0)
1273                 pr_err("%s(): could not register clock provider: %d\n",
1274                         __func__, r);
1275
1276         return r;
1277 }
1278
1279 static struct clk_onecell_data *top_clk_data;
1280
1281 static void clk_mt2712_top_init_early(struct device_node *node)
1282 {
1283         int r, i;
1284
1285         if (!top_clk_data) {
1286                 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1287
1288                 for (i = 0; i < CLK_TOP_NR_CLK; i++)
1289                         top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
1290         }
1291
1292         mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1293                         top_clk_data);
1294
1295         r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1296         if (r)
1297                 pr_err("%s(): could not register clock provider: %d\n",
1298                         __func__, r);
1299 }
1300
1301 CLK_OF_DECLARE_DRIVER(mt2712_topckgen, "mediatek,mt2712-topckgen",
1302                         clk_mt2712_top_init_early);
1303
1304 static int clk_mt2712_top_probe(struct platform_device *pdev)
1305 {
1306         int r, i;
1307         struct device_node *node = pdev->dev.of_node;
1308         void __iomem *base;
1309
1310         base = devm_platform_ioremap_resource(pdev, 0);
1311         if (IS_ERR(base)) {
1312                 pr_err("%s(): ioremap failed\n", __func__);
1313                 return PTR_ERR(base);
1314         }
1315
1316         if (!top_clk_data) {
1317                 top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
1318         } else {
1319                 for (i = 0; i < CLK_TOP_NR_CLK; i++) {
1320                         if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
1321                                 top_clk_data->clks[i] = ERR_PTR(-ENOENT);
1322                 }
1323         }
1324
1325         mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
1326                         top_clk_data);
1327         mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs),
1328                         top_clk_data);
1329         mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
1330         mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
1331                         &mt2712_clk_lock, top_clk_data);
1332         mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
1333                         &mt2712_clk_lock, top_clk_data);
1334         mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
1335                         top_clk_data);
1336
1337         r = of_clk_add_provider(node, of_clk_src_onecell_get, top_clk_data);
1338
1339         if (r != 0)
1340                 pr_err("%s(): could not register clock provider: %d\n",
1341                         __func__, r);
1342
1343         return r;
1344 }
1345
1346 static int clk_mt2712_infra_probe(struct platform_device *pdev)
1347 {
1348         struct clk_onecell_data *clk_data;
1349         int r;
1350         struct device_node *node = pdev->dev.of_node;
1351
1352         clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
1353
1354         mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
1355                         clk_data);
1356
1357         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1358
1359         if (r != 0)
1360                 pr_err("%s(): could not register clock provider: %d\n",
1361                         __func__, r);
1362
1363         mtk_register_reset_controller(node, 2, 0x30);
1364
1365         return r;
1366 }
1367
1368 static int clk_mt2712_peri_probe(struct platform_device *pdev)
1369 {
1370         struct clk_onecell_data *clk_data;
1371         int r;
1372         struct device_node *node = pdev->dev.of_node;
1373
1374         clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
1375
1376         mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
1377                         clk_data);
1378
1379         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1380
1381         if (r != 0)
1382                 pr_err("%s(): could not register clock provider: %d\n",
1383                         __func__, r);
1384
1385         mtk_register_reset_controller(node, 2, 0);
1386
1387         return r;
1388 }
1389
1390 static int clk_mt2712_mcu_probe(struct platform_device *pdev)
1391 {
1392         struct clk_onecell_data *clk_data;
1393         int r;
1394         struct device_node *node = pdev->dev.of_node;
1395         void __iomem *base;
1396
1397         base = devm_platform_ioremap_resource(pdev, 0);
1398         if (IS_ERR(base)) {
1399                 pr_err("%s(): ioremap failed\n", __func__);
1400                 return PTR_ERR(base);
1401         }
1402
1403         clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
1404
1405         mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
1406                         &mt2712_clk_lock, clk_data);
1407
1408         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1409
1410         if (r != 0)
1411                 pr_err("%s(): could not register clock provider: %d\n",
1412                         __func__, r);
1413
1414         return r;
1415 }
1416
1417 static const struct of_device_id of_match_clk_mt2712[] = {
1418         {
1419                 .compatible = "mediatek,mt2712-apmixedsys",
1420                 .data = clk_mt2712_apmixed_probe,
1421         }, {
1422                 .compatible = "mediatek,mt2712-topckgen",
1423                 .data = clk_mt2712_top_probe,
1424         }, {
1425                 .compatible = "mediatek,mt2712-infracfg",
1426                 .data = clk_mt2712_infra_probe,
1427         }, {
1428                 .compatible = "mediatek,mt2712-pericfg",
1429                 .data = clk_mt2712_peri_probe,
1430         }, {
1431                 .compatible = "mediatek,mt2712-mcucfg",
1432                 .data = clk_mt2712_mcu_probe,
1433         }, {
1434                 /* sentinel */
1435         }
1436 };
1437
1438 static int clk_mt2712_probe(struct platform_device *pdev)
1439 {
1440         int (*clk_probe)(struct platform_device *);
1441         int r;
1442
1443         clk_probe = of_device_get_match_data(&pdev->dev);
1444         if (!clk_probe)
1445                 return -EINVAL;
1446
1447         r = clk_probe(pdev);
1448         if (r != 0)
1449                 dev_err(&pdev->dev,
1450                         "could not register clock provider: %s: %d\n",
1451                         pdev->name, r);
1452
1453         return r;
1454 }
1455
1456 static struct platform_driver clk_mt2712_drv = {
1457         .probe = clk_mt2712_probe,
1458         .driver = {
1459                 .name = "clk-mt2712",
1460                 .of_match_table = of_match_clk_mt2712,
1461         },
1462 };
1463
1464 static int __init clk_mt2712_init(void)
1465 {
1466         return platform_driver_register(&clk_mt2712_drv);
1467 }
1468
1469 arch_initcall(clk_mt2712_init);