drivers/clk/mediatek/clk-mt2712-mm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2017 MediaTek Inc.
   4  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/platform_device.h>
   9
  10 #include "clk-mtk.h"
  11 #include "clk-gate.h"
  12
  13 #include <dt-bindings/clock/mt2712-clk.h>
  14
  15 static const struct mtk_gate_regs mm0_cg_regs = {
  16         .set_ofs = 0x104,
  17         .clr_ofs = 0x108,
  18         .sta_ofs = 0x100,
  19 };
  20
  21 static const struct mtk_gate_regs mm1_cg_regs = {
  22         .set_ofs = 0x114,
  23         .clr_ofs = 0x118,
  24         .sta_ofs = 0x110,
  25 };
  26
  27 static const struct mtk_gate_regs mm2_cg_regs = {
  28         .set_ofs = 0x224,
  29         .clr_ofs = 0x228,
  30         .sta_ofs = 0x220,
  31 };
  32
  33 #define GATE_MM0(_id, _name, _parent, _shift) { \
  34                 .id = _id,                              \
  35                 .name = _name,                          \
  36                 .parent_name = _parent,                 \
  37                 .regs = &mm0_cg_regs,                   \
  38                 .shift = _shift,                        \
  39                 .ops = &mtk_clk_gate_ops_setclr,        \
  40         }
  41
  42 #define GATE_MM1(_id, _name, _parent, _shift) { \
  43                 .id = _id,                              \
  44                 .name = _name,                          \
  45                 .parent_name = _parent,                 \
  46                 .regs = &mm1_cg_regs,                   \
  47                 .shift = _shift,                        \
  48                 .ops = &mtk_clk_gate_ops_setclr,        \
  49         }
  50
  51 #define GATE_MM2(_id, _name, _parent, _shift) { \
  52                 .id = _id,                              \
  53                 .name = _name,                          \
  54                 .parent_name = _parent,                 \
  55                 .regs = &mm2_cg_regs,                   \
  56                 .shift = _shift,                        \
  57                 .ops = &mtk_clk_gate_ops_setclr,        \
  58         }
  59
  60 static const struct mtk_gate mm_clks[] = {
  61         /* MM0 */
  62         GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
  63         GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
  64         GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
  65         GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
  66         GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
  67         GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
  68         GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
  69         GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
  70         GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
  71         GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
  72         GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
  73         GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
  74         GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
  75         GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
  76         GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
  77         GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
  78         GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
  79         GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
  80         GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
  81         GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
  82         GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
  83         GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
  84         GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
  85         GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
  86         GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
  87         GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
  88         GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
  89         GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
  90         GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
  91         GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
  92         /* MM1 */
  93         GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
  94         GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
  95         GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
  96         GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
  97         GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
  98         GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
  99         GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
 100         GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
 101         GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
 102         GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
 103         GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
 104         GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
 105         GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
 106         GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
 107         GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
 108         GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
 109         GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
 110         GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
 111         GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
 112         GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
 113         GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
 114         GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
 115         GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
 116         GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
 117         GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
 118         GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
 119         /* MM2 */
 120         GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
 121         GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
 122         GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
 123         GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
 124         GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
 125         GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
 126         GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
 127 };
 128
 129 static int clk_mt2712_mm_probe(struct platform_device *pdev)
 130 {
 131         struct device *dev = &pdev->dev;
 132         struct device_node *node = dev->parent->of_node;
 133         struct clk_onecell_data *clk_data;
 134         int r;
 135
 136         clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
 137
 138         mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
 139                         clk_data);
 140
 141         r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
 142
 143         if (r != 0)
 144                 pr_err("%s(): could not register clock provider: %d\n",
 145                         __func__, r);
 146
 147         return r;
 148 }
 149
 150 static struct platform_driver clk_mt2712_mm_drv = {
 151         .probe = clk_mt2712_mm_probe,
 152         .driver = {
 153                 .name = "clk-mt2712-mm",
 154         },
 155 };
 156
 157 builtin_platform_driver(clk_mt2712_mm_drv);