1 // SPDX-License-Identifier: GPL-2.0
3 * Ingenic JZ4725B SoC CGU driver
5 * Copyright (C) 2018 Paul Cercueil
6 * Author: Paul Cercueil <paul@crapouillou.net>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
12 #include <dt-bindings/clock/jz4725b-cgu.h>
15 /* CGU register offsets */
16 #define CGU_REG_CPCCR 0x00
17 #define CGU_REG_LCR 0x04
18 #define CGU_REG_CPPCR 0x10
19 #define CGU_REG_CLKGR 0x20
20 #define CGU_REG_OPCR 0x24
21 #define CGU_REG_I2SCDR 0x60
22 #define CGU_REG_LPCDR 0x64
23 #define CGU_REG_MSCCDR 0x68
24 #define CGU_REG_SSICDR 0x74
25 #define CGU_REG_CIMCDR 0x78
27 /* bits within the LCR register */
28 #define LCR_SLEEP BIT(0)
30 static struct ingenic_cgu *cgu;
32 static const s8 pll_od_encoding[4] = {
36 static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
40 [JZ4725B_CLK_EXT] = { "ext", CGU_CLK_EXT },
41 [JZ4725B_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT },
45 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
57 .od_encoding = pll_od_encoding,
64 /* Muxes & dividers */
66 [JZ4725B_CLK_PLL_HALF] = {
67 "pll half", CGU_CLK_DIV,
68 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
69 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
72 [JZ4725B_CLK_CCLK] = {
74 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
75 .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
78 [JZ4725B_CLK_HCLK] = {
80 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
81 .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
84 [JZ4725B_CLK_PCLK] = {
86 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
87 .div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
90 [JZ4725B_CLK_MCLK] = {
92 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
93 .div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
97 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
98 .parents = { JZ4725B_CLK_PLL, -1, -1, -1 },
99 .div = { CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1 },
100 .gate = { CGU_REG_CLKGR, 13 },
103 [JZ4725B_CLK_LCD] = {
104 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
105 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
106 .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
107 .gate = { CGU_REG_CLKGR, 9 },
110 [JZ4725B_CLK_I2S] = {
111 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
112 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
113 .mux = { CGU_REG_CPCCR, 31, 1 },
114 .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
115 .gate = { CGU_REG_CLKGR, 6 },
118 [JZ4725B_CLK_SPI] = {
119 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
120 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL, -1, -1 },
121 .mux = { CGU_REG_SSICDR, 31, 1 },
122 .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
123 .gate = { CGU_REG_CLKGR, 4 },
126 [JZ4725B_CLK_MMC_MUX] = {
127 "mmc_mux", CGU_CLK_DIV,
128 .parents = { JZ4725B_CLK_PLL_HALF, -1, -1, -1 },
129 .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
132 [JZ4725B_CLK_UDC] = {
133 "udc", CGU_CLK_MUX | CGU_CLK_DIV,
134 .parents = { JZ4725B_CLK_EXT, JZ4725B_CLK_PLL_HALF, -1, -1 },
135 .mux = { CGU_REG_CPCCR, 29, 1 },
136 .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
139 /* Gate-only clocks */
141 [JZ4725B_CLK_UART] = {
142 "uart", CGU_CLK_GATE,
143 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
144 .gate = { CGU_REG_CLKGR, 0 },
147 [JZ4725B_CLK_DMA] = {
149 .parents = { JZ4725B_CLK_PCLK, -1, -1, -1 },
150 .gate = { CGU_REG_CLKGR, 12 },
153 [JZ4725B_CLK_ADC] = {
155 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
156 .gate = { CGU_REG_CLKGR, 7 },
159 [JZ4725B_CLK_I2C] = {
161 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
162 .gate = { CGU_REG_CLKGR, 3 },
165 [JZ4725B_CLK_AIC] = {
167 .parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
168 .gate = { CGU_REG_CLKGR, 5 },
171 [JZ4725B_CLK_MMC0] = {
172 "mmc0", CGU_CLK_GATE,
173 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
174 .gate = { CGU_REG_CLKGR, 6 },
177 [JZ4725B_CLK_MMC1] = {
178 "mmc1", CGU_CLK_GATE,
179 .parents = { JZ4725B_CLK_MMC_MUX, -1, -1, -1 },
180 .gate = { CGU_REG_CLKGR, 16 },
183 [JZ4725B_CLK_BCH] = {
185 .parents = { JZ4725B_CLK_MCLK/* not sure */, -1, -1, -1 },
186 .gate = { CGU_REG_CLKGR, 11 },
189 [JZ4725B_CLK_TCU] = {
191 .parents = { JZ4725B_CLK_EXT/* not sure */, -1, -1, -1 },
192 .gate = { CGU_REG_CLKGR, 1 },
195 [JZ4725B_CLK_EXT512] = {
196 "ext/512", CGU_CLK_FIXDIV,
197 .parents = { JZ4725B_CLK_EXT },
199 /* Doc calls it EXT512, but it seems to be /256... */
203 [JZ4725B_CLK_RTC] = {
205 .parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
206 .mux = { CGU_REG_OPCR, 2, 1},
210 static void __init jz4725b_cgu_init(struct device_node *np)
214 cgu = ingenic_cgu_new(jz4725b_cgu_clocks,
215 ARRAY_SIZE(jz4725b_cgu_clocks), np);
217 pr_err("%s: failed to initialise CGU\n", __func__);
221 retval = ingenic_cgu_register_clocks(cgu);
223 pr_err("%s: failed to register CGU Clocks\n", __func__);
225 CLK_OF_DECLARE(jz4725b_cgu, "ingenic,jz4725b-cgu", jz4725b_cgu_init);