1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic SoC CGU driver
5 * Copyright (c) 2013-2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clkdev.h>
13 #include <linux/delay.h>
15 #include <linux/iopoll.h>
16 #include <linux/math64.h>
18 #include <linux/of_address.h>
19 #include <linux/slab.h>
20 #include <linux/spinlock.h>
21 #include <linux/time.h>
25 #define MHZ (1000 * 1000)
27 static inline const struct ingenic_cgu_clk_info *
28 to_clk_info(struct ingenic_clk *clk)
30 return &clk->cgu->clock_info[clk->idx];
34 * ingenic_cgu_gate_get() - get the value of clock gate register bit
35 * @cgu: reference to the CGU whose registers should be read
36 * @info: info struct describing the gate bit
38 * Retrieves the state of the clock gate bit described by info. The
39 * caller must hold cgu->lock.
41 * Return: true if the gate bit is set, else false.
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,
45 const struct ingenic_cgu_gate_info *info)
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit))
48 ^ info->clear_to_gate;
52 * ingenic_cgu_gate_set() - set the value of clock gate register bit
53 * @cgu: reference to the CGU whose registers should be modified
54 * @info: info struct describing the gate bit
55 * @val: non-zero to gate a clock, otherwise zero
57 * Sets the given gate bit in order to gate or ungate a clock.
59 * The caller must hold cgu->lock.
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,
63 const struct ingenic_cgu_gate_info *info, bool val)
65 u32 clkgr = readl(cgu->base + info->reg);
67 if (val ^ info->clear_to_gate)
68 clkgr |= BIT(info->bit);
70 clkgr &= ~BIT(info->bit);
72 writel(clkgr, cgu->base + info->reg);
80 ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
82 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
83 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
84 struct ingenic_cgu *cgu = ingenic_clk->cgu;
85 const struct ingenic_cgu_pll_info *pll_info;
86 unsigned m, n, od_enc, od;
90 BUG_ON(clk_info->type != CGU_CLK_PLL);
91 pll_info = &clk_info->pll;
93 ctl = readl(cgu->base + pll_info->reg);
95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
96 m += pll_info->m_offset;
97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
98 n += pll_info->n_offset;
99 od_enc = ctl >> pll_info->od_shift;
100 od_enc &= GENMASK(pll_info->od_bits - 1, 0);
102 ctl = readl(cgu->base + pll_info->bypass_reg);
104 bypass = !pll_info->no_bypass_bit &&
105 !!(ctl & BIT(pll_info->bypass_bit));
110 for (od = 0; od < pll_info->od_max; od++) {
111 if (pll_info->od_encoding[od] == od_enc)
114 BUG_ON(od == pll_info->od_max);
117 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
122 ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
123 unsigned long rate, unsigned long parent_rate,
124 unsigned *pm, unsigned *pn, unsigned *pod)
126 const struct ingenic_cgu_pll_info *pll_info;
129 pll_info = &clk_info->pll;
133 * The frequency after the input divider must be between 10 and 50 MHz.
134 * The highest divider yields the best resolution.
136 n = parent_rate / (10 * MHZ);
137 n = min_t(unsigned, n, 1 << clk_info->pll.n_bits);
138 n = max_t(unsigned, n, pll_info->n_offset);
140 m = (rate / MHZ) * od * n / (parent_rate / MHZ);
141 m = min_t(unsigned, m, 1 << clk_info->pll.m_bits);
142 m = max_t(unsigned, m, pll_info->m_offset);
151 return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
156 ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
157 unsigned long *prate)
159 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
160 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
162 return ingenic_pll_calc(clk_info, req_rate, *prate, NULL, NULL, NULL);
165 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,
166 const struct ingenic_cgu_pll_info *pll_info)
170 return readl_poll_timeout(cgu->base + pll_info->reg, ctl,
171 ctl & BIT(pll_info->stable_bit),
172 0, 100 * USEC_PER_MSEC);
176 ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate,
177 unsigned long parent_rate)
179 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
180 struct ingenic_cgu *cgu = ingenic_clk->cgu;
181 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
182 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
183 unsigned long rate, flags;
184 unsigned int m, n, od;
188 rate = ingenic_pll_calc(clk_info, req_rate, parent_rate,
190 if (rate != req_rate)
191 pr_info("ingenic-cgu: request '%s' rate %luHz, actual %luHz\n",
192 clk_info->name, req_rate, rate);
194 spin_lock_irqsave(&cgu->lock, flags);
195 ctl = readl(cgu->base + pll_info->reg);
197 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift);
198 ctl |= (m - pll_info->m_offset) << pll_info->m_shift;
200 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
201 ctl |= (n - pll_info->n_offset) << pll_info->n_shift;
203 ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
204 ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;
206 writel(ctl, cgu->base + pll_info->reg);
208 /* If the PLL is enabled, verify that it's stable */
209 if (ctl & BIT(pll_info->enable_bit))
210 ret = ingenic_pll_check_stable(cgu, pll_info);
212 spin_unlock_irqrestore(&cgu->lock, flags);
217 static int ingenic_pll_enable(struct clk_hw *hw)
219 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
220 struct ingenic_cgu *cgu = ingenic_clk->cgu;
221 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
222 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
227 spin_lock_irqsave(&cgu->lock, flags);
228 ctl = readl(cgu->base + pll_info->bypass_reg);
230 ctl &= ~BIT(pll_info->bypass_bit);
232 writel(ctl, cgu->base + pll_info->bypass_reg);
234 ctl = readl(cgu->base + pll_info->reg);
236 ctl |= BIT(pll_info->enable_bit);
238 writel(ctl, cgu->base + pll_info->reg);
240 ret = ingenic_pll_check_stable(cgu, pll_info);
241 spin_unlock_irqrestore(&cgu->lock, flags);
246 static void ingenic_pll_disable(struct clk_hw *hw)
248 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
249 struct ingenic_cgu *cgu = ingenic_clk->cgu;
250 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
251 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
255 spin_lock_irqsave(&cgu->lock, flags);
256 ctl = readl(cgu->base + pll_info->reg);
258 ctl &= ~BIT(pll_info->enable_bit);
260 writel(ctl, cgu->base + pll_info->reg);
261 spin_unlock_irqrestore(&cgu->lock, flags);
264 static int ingenic_pll_is_enabled(struct clk_hw *hw)
266 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
267 struct ingenic_cgu *cgu = ingenic_clk->cgu;
268 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
269 const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
272 ctl = readl(cgu->base + pll_info->reg);
274 return !!(ctl & BIT(pll_info->enable_bit));
277 static const struct clk_ops ingenic_pll_ops = {
278 .recalc_rate = ingenic_pll_recalc_rate,
279 .round_rate = ingenic_pll_round_rate,
280 .set_rate = ingenic_pll_set_rate,
282 .enable = ingenic_pll_enable,
283 .disable = ingenic_pll_disable,
284 .is_enabled = ingenic_pll_is_enabled,
288 * Operations for all non-PLL clocks
291 static u8 ingenic_clk_get_parent(struct clk_hw *hw)
293 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
294 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
295 struct ingenic_cgu *cgu = ingenic_clk->cgu;
297 u8 i, hw_idx, idx = 0;
299 if (clk_info->type & CGU_CLK_MUX) {
300 reg = readl(cgu->base + clk_info->mux.reg);
301 hw_idx = (reg >> clk_info->mux.shift) &
302 GENMASK(clk_info->mux.bits - 1, 0);
305 * Convert the hardware index to the parent index by skipping
306 * over any -1's in the parents array.
308 for (i = 0; i < hw_idx; i++) {
309 if (clk_info->parents[i] != -1)
317 static int ingenic_clk_set_parent(struct clk_hw *hw, u8 idx)
319 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
320 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
321 struct ingenic_cgu *cgu = ingenic_clk->cgu;
323 u8 curr_idx, hw_idx, num_poss;
326 if (clk_info->type & CGU_CLK_MUX) {
328 * Convert the parent index to the hardware index by adding
329 * 1 for any -1 in the parents array preceding the given
330 * index. That is, we want the index of idx'th entry in
331 * clk_info->parents which does not equal -1.
333 hw_idx = curr_idx = 0;
334 num_poss = 1 << clk_info->mux.bits;
335 for (; hw_idx < num_poss; hw_idx++) {
336 if (clk_info->parents[hw_idx] == -1)
343 /* idx should always be a valid parent */
344 BUG_ON(curr_idx != idx);
346 mask = GENMASK(clk_info->mux.bits - 1, 0);
347 mask <<= clk_info->mux.shift;
349 spin_lock_irqsave(&cgu->lock, flags);
351 /* write the register */
352 reg = readl(cgu->base + clk_info->mux.reg);
354 reg |= hw_idx << clk_info->mux.shift;
355 writel(reg, cgu->base + clk_info->mux.reg);
357 spin_unlock_irqrestore(&cgu->lock, flags);
361 return idx ? -EINVAL : 0;
365 ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
367 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
368 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
369 struct ingenic_cgu *cgu = ingenic_clk->cgu;
370 unsigned long rate = parent_rate;
373 if (clk_info->type & CGU_CLK_DIV) {
374 div_reg = readl(cgu->base + clk_info->div.reg);
375 div = (div_reg >> clk_info->div.shift) &
376 GENMASK(clk_info->div.bits - 1, 0);
378 if (clk_info->div.div_table)
379 div = clk_info->div.div_table[div];
381 div = (div + 1) * clk_info->div.div;
384 } else if (clk_info->type & CGU_CLK_FIXDIV) {
385 rate /= clk_info->fixdiv.div;
392 ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
397 for (i = 0; i < (1 << clk_info->div.bits)
398 && clk_info->div.div_table[i]; i++) {
399 if (clk_info->div.div_table[i] >= div)
407 ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
408 unsigned long parent_rate, unsigned long req_rate)
410 unsigned int div, hw_div;
412 /* calculate the divide */
413 div = DIV_ROUND_UP(parent_rate, req_rate);
415 if (clk_info->div.div_table) {
416 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
418 return clk_info->div.div_table[hw_div];
421 /* Impose hardware constraints */
422 div = min_t(unsigned, div, 1 << clk_info->div.bits);
423 div = max_t(unsigned, div, 1);
426 * If the divider value itself must be divided before being written to
427 * the divider register, we must ensure we don't have any bits set that
428 * would be lost as a result of doing so.
430 div /= clk_info->div.div;
431 div *= clk_info->div.div;
437 ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
438 unsigned long *parent_rate)
440 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
441 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
442 unsigned int div = 1;
444 if (clk_info->type & CGU_CLK_DIV)
445 div = ingenic_clk_calc_div(clk_info, *parent_rate, req_rate);
446 else if (clk_info->type & CGU_CLK_FIXDIV)
447 div = clk_info->fixdiv.div;
448 else if (clk_hw_can_set_rate_parent(hw))
449 *parent_rate = req_rate;
451 return DIV_ROUND_UP(*parent_rate, div);
454 static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,
455 const struct ingenic_cgu_clk_info *clk_info)
459 return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,
460 !(reg & BIT(clk_info->div.busy_bit)),
461 0, 100 * USEC_PER_MSEC);
465 ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
466 unsigned long parent_rate)
468 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
469 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
470 struct ingenic_cgu *cgu = ingenic_clk->cgu;
471 unsigned long rate, flags;
472 unsigned int hw_div, div;
476 if (clk_info->type & CGU_CLK_DIV) {
477 div = ingenic_clk_calc_div(clk_info, parent_rate, req_rate);
478 rate = DIV_ROUND_UP(parent_rate, div);
480 if (rate != req_rate)
483 if (clk_info->div.div_table)
484 hw_div = ingenic_clk_calc_hw_div(clk_info, div);
486 hw_div = ((div / clk_info->div.div) - 1);
488 spin_lock_irqsave(&cgu->lock, flags);
489 reg = readl(cgu->base + clk_info->div.reg);
491 /* update the divide */
492 mask = GENMASK(clk_info->div.bits - 1, 0);
493 reg &= ~(mask << clk_info->div.shift);
494 reg |= hw_div << clk_info->div.shift;
496 /* clear the stop bit */
497 if (clk_info->div.stop_bit != -1)
498 reg &= ~BIT(clk_info->div.stop_bit);
500 /* set the change enable bit */
501 if (clk_info->div.ce_bit != -1)
502 reg |= BIT(clk_info->div.ce_bit);
504 /* update the hardware */
505 writel(reg, cgu->base + clk_info->div.reg);
507 /* wait for the change to take effect */
508 if (clk_info->div.busy_bit != -1)
509 ret = ingenic_clk_check_stable(cgu, clk_info);
511 spin_unlock_irqrestore(&cgu->lock, flags);
518 static int ingenic_clk_enable(struct clk_hw *hw)
520 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
521 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
522 struct ingenic_cgu *cgu = ingenic_clk->cgu;
525 if (clk_info->type & CGU_CLK_GATE) {
526 /* ungate the clock */
527 spin_lock_irqsave(&cgu->lock, flags);
528 ingenic_cgu_gate_set(cgu, &clk_info->gate, false);
529 spin_unlock_irqrestore(&cgu->lock, flags);
531 if (clk_info->gate.delay_us)
532 udelay(clk_info->gate.delay_us);
538 static void ingenic_clk_disable(struct clk_hw *hw)
540 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
541 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
542 struct ingenic_cgu *cgu = ingenic_clk->cgu;
545 if (clk_info->type & CGU_CLK_GATE) {
547 spin_lock_irqsave(&cgu->lock, flags);
548 ingenic_cgu_gate_set(cgu, &clk_info->gate, true);
549 spin_unlock_irqrestore(&cgu->lock, flags);
553 static int ingenic_clk_is_enabled(struct clk_hw *hw)
555 struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
556 const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
557 struct ingenic_cgu *cgu = ingenic_clk->cgu;
560 if (clk_info->type & CGU_CLK_GATE)
561 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
566 static const struct clk_ops ingenic_clk_ops = {
567 .get_parent = ingenic_clk_get_parent,
568 .set_parent = ingenic_clk_set_parent,
570 .recalc_rate = ingenic_clk_recalc_rate,
571 .round_rate = ingenic_clk_round_rate,
572 .set_rate = ingenic_clk_set_rate,
574 .enable = ingenic_clk_enable,
575 .disable = ingenic_clk_disable,
576 .is_enabled = ingenic_clk_is_enabled,
583 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)
585 const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];
586 struct clk_init_data clk_init;
587 struct ingenic_clk *ingenic_clk = NULL;
588 struct clk *clk, *parent;
589 const char *parent_names[4];
590 unsigned caps, i, num_possible;
593 BUILD_BUG_ON(ARRAY_SIZE(clk_info->parents) > ARRAY_SIZE(parent_names));
595 if (clk_info->type == CGU_CLK_EXT) {
596 clk = of_clk_get_by_name(cgu->np, clk_info->name);
598 pr_err("%s: no external clock '%s' provided\n",
599 __func__, clk_info->name);
603 err = clk_register_clkdev(clk, clk_info->name, NULL);
608 cgu->clocks.clks[idx] = clk;
612 if (!clk_info->type) {
613 pr_err("%s: no clock type specified for '%s'\n", __func__,
618 ingenic_clk = kzalloc(sizeof(*ingenic_clk), GFP_KERNEL);
624 ingenic_clk->hw.init = &clk_init;
625 ingenic_clk->cgu = cgu;
626 ingenic_clk->idx = idx;
628 clk_init.name = clk_info->name;
630 clk_init.parent_names = parent_names;
632 caps = clk_info->type;
634 if (caps & CGU_CLK_DIV) {
635 caps &= ~CGU_CLK_DIV;
636 } else if (!(caps & CGU_CLK_CUSTOM)) {
637 /* pass rate changes to the parent clock */
638 clk_init.flags |= CLK_SET_RATE_PARENT;
641 if (caps & (CGU_CLK_MUX | CGU_CLK_CUSTOM)) {
642 clk_init.num_parents = 0;
644 if (caps & CGU_CLK_MUX)
645 num_possible = 1 << clk_info->mux.bits;
647 num_possible = ARRAY_SIZE(clk_info->parents);
649 for (i = 0; i < num_possible; i++) {
650 if (clk_info->parents[i] == -1)
653 parent = cgu->clocks.clks[clk_info->parents[i]];
654 parent_names[clk_init.num_parents] =
655 __clk_get_name(parent);
656 clk_init.num_parents++;
659 BUG_ON(!clk_init.num_parents);
660 BUG_ON(clk_init.num_parents > ARRAY_SIZE(parent_names));
662 BUG_ON(clk_info->parents[0] == -1);
663 clk_init.num_parents = 1;
664 parent = cgu->clocks.clks[clk_info->parents[0]];
665 parent_names[0] = __clk_get_name(parent);
668 if (caps & CGU_CLK_CUSTOM) {
669 clk_init.ops = clk_info->custom.clk_ops;
671 caps &= ~CGU_CLK_CUSTOM;
674 pr_err("%s: custom clock may not be combined with type 0x%x\n",
678 } else if (caps & CGU_CLK_PLL) {
679 clk_init.ops = &ingenic_pll_ops;
681 caps &= ~CGU_CLK_PLL;
684 pr_err("%s: PLL may not be combined with type 0x%x\n",
689 clk_init.ops = &ingenic_clk_ops;
692 /* nothing to do for gates or fixed dividers */
693 caps &= ~(CGU_CLK_GATE | CGU_CLK_FIXDIV);
695 if (caps & CGU_CLK_MUX) {
696 if (!(caps & CGU_CLK_MUX_GLITCHFREE))
697 clk_init.flags |= CLK_SET_PARENT_GATE;
699 caps &= ~(CGU_CLK_MUX | CGU_CLK_MUX_GLITCHFREE);
703 pr_err("%s: unknown clock type 0x%x\n", __func__, caps);
707 clk = clk_register(NULL, &ingenic_clk->hw);
709 pr_err("%s: failed to register clock '%s'\n", __func__,
715 err = clk_register_clkdev(clk, clk_info->name, NULL);
719 cgu->clocks.clks[idx] = clk;
727 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info,
728 unsigned num_clocks, struct device_node *np)
730 struct ingenic_cgu *cgu;
732 cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);
736 cgu->base = of_iomap(np, 0);
738 pr_err("%s: failed to map CGU registers\n", __func__);
743 cgu->clock_info = clock_info;
744 cgu->clocks.clk_num = num_clocks;
746 spin_lock_init(&cgu->lock);
756 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)
761 cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),
763 if (!cgu->clocks.clks) {
768 for (i = 0; i < cgu->clocks.clk_num; i++) {
769 err = ingenic_register_clock(cgu, i);
771 goto err_out_unregister;
774 err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,
777 goto err_out_unregister;
782 for (i = 0; i < cgu->clocks.clk_num; i++) {
783 if (!cgu->clocks.clks[i])
785 if (cgu->clock_info[i].type & CGU_CLK_EXT)
786 clk_put(cgu->clocks.clks[i]);
788 clk_unregister(cgu->clocks.clks[i]);
790 kfree(cgu->clocks.clks);