1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bits.h>
4 #include <linux/clk-provider.h>
7 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/spinlock.h>
14 #define CCDR_MMDC_CH0_MASK BIT(17)
15 #define CCDR_MMDC_CH1_MASK BIT(16)
17 DEFINE_SPINLOCK(imx_ccm_lock);
18 EXPORT_SYMBOL_GPL(imx_ccm_lock);
20 void imx_unregister_clocks(struct clk *clks[], unsigned int count)
24 for (i = 0; i < count; i++)
25 clk_unregister(clks[i]);
28 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count)
32 for (i = 0; i < count; i++)
33 clk_hw_unregister(hws[i]);
35 EXPORT_SYMBOL_GPL(imx_unregister_hw_clocks);
37 void imx_mmdc_mask_handshake(void __iomem *ccm_base,
42 reg = readl_relaxed(ccm_base + CCM_CCDR);
43 reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK;
44 writel_relaxed(reg, ccm_base + CCM_CCDR);
47 void imx_check_clocks(struct clk *clks[], unsigned int count)
51 for (i = 0; i < count; i++)
53 pr_err("i.MX clk %u: register failed with %ld\n",
57 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
61 for (i = 0; i < count; i++)
63 pr_err("i.MX clk %u: register failed with %ld\n",
66 EXPORT_SYMBOL_GPL(imx_check_clk_hws);
68 static struct clk *imx_obtain_fixed_clock_from_dt(const char *name)
70 struct of_phandle_args phandle;
71 struct clk *clk = ERR_PTR(-ENODEV);
74 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
76 return ERR_PTR(-ENOMEM);
78 phandle.np = of_find_node_by_path(path);
82 clk = of_clk_get_from_provider(&phandle);
83 of_node_put(phandle.np);
88 struct clk *imx_obtain_fixed_clock(
89 const char *name, unsigned long rate)
93 clk = imx_obtain_fixed_clock_from_dt(name);
95 clk = imx_clk_fixed(name, rate);
99 struct clk_hw *imx_obtain_fixed_clock_hw(
100 const char *name, unsigned long rate)
104 clk = imx_obtain_fixed_clock_from_dt(name);
106 clk = imx_clk_fixed(name, rate);
107 return __clk_get_hw(clk);
110 struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np,
115 clk = of_clk_get_by_name(np, name);
117 return ERR_PTR(-ENOENT);
119 return __clk_get_hw(clk);
121 EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw);
124 * This fixups the register CCM_CSCMR1 write value.
125 * The write/read/divider values of the aclk_podf field
126 * of that register have the relationship described by
127 * the following table:
129 * write value read value divider
137 * 3b'111 3b'001 2(default)
139 * That's why we do the xor operation below.
141 #define CSCMR1_FIXUP 0x00600000
143 void imx_cscmr1_fixup(u32 *val)
145 *val ^= CSCMR1_FIXUP;
150 static int imx_keep_uart_clocks;
151 static struct clk ** const *imx_uart_clocks;
153 static int __init imx_keep_uart_clocks_param(char *str)
155 imx_keep_uart_clocks = 1;
159 __setup_param("earlycon", imx_keep_uart_earlycon,
160 imx_keep_uart_clocks_param, 0);
161 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
162 imx_keep_uart_clocks_param, 0);
164 void imx_register_uart_clocks(struct clk ** const clks[])
166 if (imx_keep_uart_clocks) {
169 imx_uart_clocks = clks;
170 for (i = 0; imx_uart_clocks[i]; i++)
171 clk_prepare_enable(*imx_uart_clocks[i]);
175 static int __init imx_clk_disable_uart(void)
177 if (imx_keep_uart_clocks && imx_uart_clocks) {
180 for (i = 0; imx_uart_clocks[i]; i++)
181 clk_disable_unprepare(*imx_uart_clocks[i]);
186 late_initcall_sync(imx_clk_disable_uart);
189 MODULE_LICENSE("GPL v2");