1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bits.h>
4 #include <linux/clk-provider.h>
7 #include <linux/module.h>
9 #include <linux/slab.h>
10 #include <linux/spinlock.h>
14 #define CCDR_MMDC_CH0_MASK BIT(17)
15 #define CCDR_MMDC_CH1_MASK BIT(16)
17 DEFINE_SPINLOCK(imx_ccm_lock);
18 EXPORT_SYMBOL_GPL(imx_ccm_lock);
21 EXPORT_SYMBOL_GPL(mcore_booted);
23 void imx_unregister_clocks(struct clk *clks[], unsigned int count)
27 for (i = 0; i < count; i++)
28 clk_unregister(clks[i]);
31 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count)
35 for (i = 0; i < count; i++)
36 clk_hw_unregister(hws[i]);
38 EXPORT_SYMBOL_GPL(imx_unregister_hw_clocks);
40 void imx_mmdc_mask_handshake(void __iomem *ccm_base,
45 reg = readl_relaxed(ccm_base + CCM_CCDR);
46 reg |= chn == 0 ? CCDR_MMDC_CH0_MASK : CCDR_MMDC_CH1_MASK;
47 writel_relaxed(reg, ccm_base + CCM_CCDR);
50 void imx_check_clocks(struct clk *clks[], unsigned int count)
54 for (i = 0; i < count; i++)
56 pr_err("i.MX clk %u: register failed with %ld\n",
60 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
64 for (i = 0; i < count; i++)
66 pr_err("i.MX clk %u: register failed with %ld\n",
69 EXPORT_SYMBOL_GPL(imx_check_clk_hws);
71 static struct clk *imx_obtain_fixed_clock_from_dt(const char *name)
73 struct of_phandle_args phandle;
74 struct clk *clk = ERR_PTR(-ENODEV);
77 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
79 return ERR_PTR(-ENOMEM);
81 phandle.np = of_find_node_by_path(path);
85 clk = of_clk_get_from_provider(&phandle);
86 of_node_put(phandle.np);
91 struct clk *imx_obtain_fixed_clock(
92 const char *name, unsigned long rate)
96 clk = imx_obtain_fixed_clock_from_dt(name);
98 clk = imx_clk_fixed(name, rate);
102 struct clk_hw *imx_obtain_fixed_clock_hw(
103 const char *name, unsigned long rate)
107 clk = imx_obtain_fixed_clock_from_dt(name);
109 clk = imx_clk_fixed(name, rate);
110 return __clk_get_hw(clk);
113 struct clk_hw * imx_obtain_fixed_clk_hw(struct device_node *np,
118 clk = of_clk_get_by_name(np, name);
120 return ERR_PTR(-ENOENT);
122 return __clk_get_hw(clk);
124 EXPORT_SYMBOL_GPL(imx_obtain_fixed_clk_hw);
127 * This fixups the register CCM_CSCMR1 write value.
128 * The write/read/divider values of the aclk_podf field
129 * of that register have the relationship described by
130 * the following table:
132 * write value read value divider
140 * 3b'111 3b'001 2(default)
142 * That's why we do the xor operation below.
144 #define CSCMR1_FIXUP 0x00600000
146 void imx_cscmr1_fixup(u32 *val)
148 *val ^= CSCMR1_FIXUP;
154 static bool imx_keep_uart_clocks;
155 static int imx_enabled_uart_clocks;
156 static struct clk **imx_uart_clocks;
158 static int __init imx_keep_uart_clocks_param(char *str)
160 imx_keep_uart_clocks = 1;
164 __setup_param("earlycon", imx_keep_uart_earlycon,
165 imx_keep_uart_clocks_param, 0);
166 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
167 imx_keep_uart_clocks_param, 0);
169 void imx_register_uart_clocks(unsigned int clk_count)
171 imx_enabled_uart_clocks = 0;
173 /* i.MX boards use device trees now. For build tests without CONFIG_OF, do nothing */
175 if (imx_keep_uart_clocks) {
178 imx_uart_clocks = kcalloc(clk_count, sizeof(struct clk *), GFP_KERNEL);
179 if (!imx_uart_clocks)
185 for (i = 0; i < clk_count; i++) {
186 imx_uart_clocks[imx_enabled_uart_clocks] = of_clk_get(of_stdout, i);
188 /* Stop if there are no more of_stdout references */
189 if (IS_ERR(imx_uart_clocks[imx_enabled_uart_clocks]))
192 /* Only enable the clock if it's not NULL */
193 if (imx_uart_clocks[imx_enabled_uart_clocks])
194 clk_prepare_enable(imx_uart_clocks[imx_enabled_uart_clocks++]);
200 static int __init imx_clk_disable_uart(void)
202 if (imx_keep_uart_clocks && imx_enabled_uart_clocks) {
205 for (i = 0; i < imx_enabled_uart_clocks; i++) {
206 clk_disable_unprepare(imx_uart_clocks[i]);
207 clk_put(imx_uart_clocks[i]);
209 kfree(imx_uart_clocks);
214 late_initcall_sync(imx_clk_disable_uart);
217 MODULE_LICENSE("GPL v2");