1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/slab.h>
6 #include <linux/spinlock.h>
9 DEFINE_SPINLOCK(imx_ccm_lock);
11 void __init imx_check_clocks(struct clk *clks[], unsigned int count)
15 for (i = 0; i < count; i++)
17 pr_err("i.MX clk %u: register failed with %ld\n",
21 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count)
25 for (i = 0; i < count; i++)
27 pr_err("i.MX clk %u: register failed with %ld\n",
31 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name)
33 struct of_phandle_args phandle;
34 struct clk *clk = ERR_PTR(-ENODEV);
37 path = kasprintf(GFP_KERNEL, "/clocks/%s", name);
39 return ERR_PTR(-ENOMEM);
41 phandle.np = of_find_node_by_path(path);
45 clk = of_clk_get_from_provider(&phandle);
46 of_node_put(phandle.np);
51 struct clk * __init imx_obtain_fixed_clock(
52 const char *name, unsigned long rate)
56 clk = imx_obtain_fixed_clock_from_dt(name);
58 clk = imx_clk_fixed(name, rate);
62 struct clk_hw * __init imx_obtain_fixed_clk_hw(struct device_node *np,
67 clk = of_clk_get_by_name(np, name);
69 return ERR_PTR(-ENOENT);
71 return __clk_get_hw(clk);
75 * This fixups the register CCM_CSCMR1 write value.
76 * The write/read/divider values of the aclk_podf field
77 * of that register have the relationship described by
78 * the following table:
80 * write value read value divider
88 * 3b'111 3b'001 2(default)
90 * That's why we do the xor operation below.
92 #define CSCMR1_FIXUP 0x00600000
94 void imx_cscmr1_fixup(u32 *val)
100 static int imx_keep_uart_clocks __initdata;
101 static struct clk ** const *imx_uart_clocks __initdata;
103 static int __init imx_keep_uart_clocks_param(char *str)
105 imx_keep_uart_clocks = 1;
109 __setup_param("earlycon", imx_keep_uart_earlycon,
110 imx_keep_uart_clocks_param, 0);
111 __setup_param("earlyprintk", imx_keep_uart_earlyprintk,
112 imx_keep_uart_clocks_param, 0);
114 void __init imx_register_uart_clocks(struct clk ** const clks[])
116 if (imx_keep_uart_clocks) {
119 imx_uart_clocks = clks;
120 for (i = 0; imx_uart_clocks[i]; i++)
121 clk_prepare_enable(*imx_uart_clocks[i]);
125 static int __init imx_clk_disable_uart(void)
127 if (imx_keep_uart_clocks && imx_uart_clocks) {
130 for (i = 0; imx_uart_clocks[i]; i++)
131 clk_disable_unprepare(*imx_uart_clocks[i]);
136 late_initcall_sync(imx_clk_disable_uart);