1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * This driver supports the SCCG plls found in the imx8m SOCs
7 * Documentation for this SCCG pll can be found at:
8 * https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
11 #include <linux/clk-provider.h>
12 #include <linux/err.h>
14 #include <linux/iopoll.h>
15 #include <linux/slab.h>
16 #include <linux/bitfield.h>
25 #define PLL_DIVF1_MASK GENMASK(18, 13)
26 #define PLL_DIVF2_MASK GENMASK(12, 7)
27 #define PLL_DIVR1_MASK GENMASK(27, 25)
28 #define PLL_DIVR2_MASK GENMASK(24, 19)
29 #define PLL_DIVQ_MASK GENMASK(6, 1)
30 #define PLL_REF_MASK GENMASK(2, 0)
32 #define PLL_LOCK_MASK BIT(31)
33 #define PLL_PD_MASK BIT(7)
35 /* These are the specification limits for the SSCG PLL */
36 #define PLL_REF_MIN_FREQ 25000000UL
37 #define PLL_REF_MAX_FREQ 235000000UL
39 #define PLL_STAGE1_MIN_FREQ 1600000000UL
40 #define PLL_STAGE1_MAX_FREQ 2400000000UL
42 #define PLL_STAGE1_REF_MIN_FREQ 25000000UL
43 #define PLL_STAGE1_REF_MAX_FREQ 54000000UL
45 #define PLL_STAGE2_MIN_FREQ 1200000000UL
46 #define PLL_STAGE2_MAX_FREQ 2400000000UL
48 #define PLL_STAGE2_REF_MIN_FREQ 54000000UL
49 #define PLL_STAGE2_REF_MAX_FREQ 75000000UL
51 #define PLL_OUT_MIN_FREQ 20000000UL
52 #define PLL_OUT_MAX_FREQ 1200000000UL
54 #define PLL_DIVR1_MAX 7
55 #define PLL_DIVR2_MAX 63
56 #define PLL_DIVF1_MAX 63
57 #define PLL_DIVF2_MAX 63
58 #define PLL_DIVQ_MAX 63
60 #define PLL_BYPASS_NONE 0x0
61 #define PLL_BYPASS1 0x2
62 #define PLL_BYPASS2 0x1
64 #define SSCG_PLL_BYPASS1_MASK BIT(5)
65 #define SSCG_PLL_BYPASS2_MASK BIT(4)
66 #define SSCG_PLL_BYPASS_MASK GENMASK(5, 4)
68 #define PLL_SCCG_LOCK_TIMEOUT 70
70 struct clk_sscg_pll_setup {
81 uint64_t fout_request;
87 const struct clk_ops ops;
89 struct clk_sscg_pll_setup setup;
95 #define to_clk_sscg_pll(_hw) container_of(_hw, struct clk_sscg_pll, hw)
97 static int clk_sscg_pll_wait_lock(struct clk_sscg_pll *pll)
101 val = readl_relaxed(pll->base + PLL_CFG0);
103 /* don't wait for lock if all plls are bypassed */
104 if (!(val & SSCG_PLL_BYPASS2_MASK))
105 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
106 0, PLL_SCCG_LOCK_TIMEOUT);
111 static int clk_sscg_pll2_check_match(struct clk_sscg_pll_setup *setup,
112 struct clk_sscg_pll_setup *temp_setup)
114 int new_diff = temp_setup->fout - temp_setup->fout_request;
115 int diff = temp_setup->fout_error;
117 if (abs(diff) > abs(new_diff)) {
118 temp_setup->fout_error = new_diff;
119 memcpy(setup, temp_setup, sizeof(struct clk_sscg_pll_setup));
121 if (temp_setup->fout_request == temp_setup->fout)
127 static int clk_sscg_divq_lookup(struct clk_sscg_pll_setup *setup,
128 struct clk_sscg_pll_setup *temp_setup)
132 for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX;
133 temp_setup->divq++) {
134 temp_setup->vco2 = temp_setup->vco1;
135 do_div(temp_setup->vco2, temp_setup->divr2 + 1);
136 temp_setup->vco2 *= 2;
137 temp_setup->vco2 *= temp_setup->divf2 + 1;
138 if (temp_setup->vco2 >= PLL_STAGE2_MIN_FREQ &&
139 temp_setup->vco2 <= PLL_STAGE2_MAX_FREQ) {
140 temp_setup->fout = temp_setup->vco2;
141 do_div(temp_setup->fout, 2 * (temp_setup->divq + 1));
143 ret = clk_sscg_pll2_check_match(setup, temp_setup);
145 temp_setup->bypass = PLL_BYPASS1;
154 static int clk_sscg_divf2_lookup(struct clk_sscg_pll_setup *setup,
155 struct clk_sscg_pll_setup *temp_setup)
159 for (temp_setup->divf2 = 0; temp_setup->divf2 <= PLL_DIVF2_MAX;
160 temp_setup->divf2++) {
161 ret = clk_sscg_divq_lookup(setup, temp_setup);
169 static int clk_sscg_divr2_lookup(struct clk_sscg_pll_setup *setup,
170 struct clk_sscg_pll_setup *temp_setup)
174 for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX;
175 temp_setup->divr2++) {
176 temp_setup->ref_div2 = temp_setup->vco1;
177 do_div(temp_setup->ref_div2, temp_setup->divr2 + 1);
178 if (temp_setup->ref_div2 >= PLL_STAGE2_REF_MIN_FREQ &&
179 temp_setup->ref_div2 <= PLL_STAGE2_REF_MAX_FREQ) {
180 ret = clk_sscg_divf2_lookup(setup, temp_setup);
189 static int clk_sscg_pll2_find_setup(struct clk_sscg_pll_setup *setup,
190 struct clk_sscg_pll_setup *temp_setup,
195 if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ)
198 temp_setup->vco1 = ref;
200 ret = clk_sscg_divr2_lookup(setup, temp_setup);
204 static int clk_sscg_divf1_lookup(struct clk_sscg_pll_setup *setup,
205 struct clk_sscg_pll_setup *temp_setup)
209 for (temp_setup->divf1 = 0; temp_setup->divf1 <= PLL_DIVF1_MAX;
210 temp_setup->divf1++) {
211 uint64_t vco1 = temp_setup->ref;
213 do_div(vco1, temp_setup->divr1 + 1);
215 vco1 *= temp_setup->divf1 + 1;
217 ret = clk_sscg_pll2_find_setup(setup, temp_setup, vco1);
219 temp_setup->bypass = PLL_BYPASS_NONE;
227 static int clk_sscg_divr1_lookup(struct clk_sscg_pll_setup *setup,
228 struct clk_sscg_pll_setup *temp_setup)
232 for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX;
233 temp_setup->divr1++) {
234 temp_setup->ref_div1 = temp_setup->ref;
235 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1);
236 if (temp_setup->ref_div1 >= PLL_STAGE1_REF_MIN_FREQ &&
237 temp_setup->ref_div1 <= PLL_STAGE1_REF_MAX_FREQ) {
238 ret = clk_sscg_divf1_lookup(setup, temp_setup);
247 static int clk_sscg_pll1_find_setup(struct clk_sscg_pll_setup *setup,
248 struct clk_sscg_pll_setup *temp_setup,
253 if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ)
256 temp_setup->ref = ref;
258 ret = clk_sscg_divr1_lookup(setup, temp_setup);
263 static int clk_sscg_pll_find_setup(struct clk_sscg_pll_setup *setup,
265 uint64_t rate, int try_bypass)
267 struct clk_sscg_pll_setup temp_setup;
270 memset(&temp_setup, 0, sizeof(struct clk_sscg_pll_setup));
271 memset(setup, 0, sizeof(struct clk_sscg_pll_setup));
273 temp_setup.fout_error = PLL_OUT_MAX_FREQ;
274 temp_setup.fout_request = rate;
276 switch (try_bypass) {
279 setup->bypass = PLL_BYPASS2;
285 ret = clk_sscg_pll2_find_setup(setup, &temp_setup, prate);
287 case PLL_BYPASS_NONE:
288 ret = clk_sscg_pll1_find_setup(setup, &temp_setup, prate);
295 static int clk_sscg_pll_is_prepared(struct clk_hw *hw)
297 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
299 u32 val = readl_relaxed(pll->base + PLL_CFG0);
301 return (val & PLL_PD_MASK) ? 0 : 1;
304 static int clk_sscg_pll_prepare(struct clk_hw *hw)
306 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
309 val = readl_relaxed(pll->base + PLL_CFG0);
311 writel_relaxed(val, pll->base + PLL_CFG0);
313 return clk_sscg_pll_wait_lock(pll);
316 static void clk_sscg_pll_unprepare(struct clk_hw *hw)
318 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
321 val = readl_relaxed(pll->base + PLL_CFG0);
323 writel_relaxed(val, pll->base + PLL_CFG0);
326 static unsigned long clk_sscg_pll_recalc_rate(struct clk_hw *hw,
327 unsigned long parent_rate)
329 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
330 u32 val, divr1, divf1, divr2, divf2, divq;
333 val = readl_relaxed(pll->base + PLL_CFG2);
334 divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
335 divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
336 divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
337 divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
338 divq = FIELD_GET(PLL_DIVQ_MASK, val);
340 temp64 = parent_rate;
342 val = readl(pll->base + PLL_CFG0);
343 if (val & SSCG_PLL_BYPASS2_MASK) {
344 temp64 = parent_rate;
345 } else if (val & SSCG_PLL_BYPASS1_MASK) {
347 do_div(temp64, (divr2 + 1) * (divq + 1));
350 temp64 *= (divf1 + 1) * (divf2 + 1);
351 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
357 static int clk_sscg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
358 unsigned long parent_rate)
360 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
361 struct clk_sscg_pll_setup *setup = &pll->setup;
364 /* set bypass here too since the parent might be the same */
365 val = readl(pll->base + PLL_CFG0);
366 val &= ~SSCG_PLL_BYPASS_MASK;
367 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
368 writel(val, pll->base + PLL_CFG0);
370 val = readl_relaxed(pll->base + PLL_CFG2);
371 val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
372 val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK);
373 val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1);
374 val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2);
375 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1);
376 val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2);
377 val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq);
378 writel_relaxed(val, pll->base + PLL_CFG2);
380 return clk_sscg_pll_wait_lock(pll);
383 static u8 clk_sscg_pll_get_parent(struct clk_hw *hw)
385 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
387 u8 ret = pll->parent;
389 val = readl(pll->base + PLL_CFG0);
390 if (val & SSCG_PLL_BYPASS2_MASK)
392 else if (val & SSCG_PLL_BYPASS1_MASK)
397 static int clk_sscg_pll_set_parent(struct clk_hw *hw, u8 index)
399 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
402 val = readl(pll->base + PLL_CFG0);
403 val &= ~SSCG_PLL_BYPASS_MASK;
404 val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
405 writel(val, pll->base + PLL_CFG0);
407 return clk_sscg_pll_wait_lock(pll);
410 static int __clk_sscg_pll_determine_rate(struct clk_hw *hw,
411 struct clk_rate_request *req,
417 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
418 struct clk_sscg_pll_setup *setup = &pll->setup;
419 struct clk_hw *parent_hw = NULL;
420 int bypass_parent_index;
428 bypass_parent_index = pll->bypass2;
431 bypass_parent_index = pll->bypass1;
434 bypass_parent_index = pll->parent;
438 parent_hw = clk_hw_get_parent_by_index(hw, bypass_parent_index);
439 ret = __clk_determine_rate(parent_hw, req);
441 ret = clk_sscg_pll_find_setup(setup, req->rate,
445 req->best_parent_hw = parent_hw;
446 req->best_parent_rate = req->rate;
447 req->rate = setup->fout;
452 static int clk_sscg_pll_determine_rate(struct clk_hw *hw,
453 struct clk_rate_request *req)
455 struct clk_sscg_pll *pll = to_clk_sscg_pll(hw);
456 struct clk_sscg_pll_setup *setup = &pll->setup;
457 uint64_t rate = req->rate;
458 uint64_t min = req->min_rate;
459 uint64_t max = req->max_rate;
462 if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ)
465 ret = __clk_sscg_pll_determine_rate(hw, req, req->rate, req->rate,
470 ret = __clk_sscg_pll_determine_rate(hw, req, PLL_STAGE1_REF_MIN_FREQ,
471 PLL_STAGE1_REF_MAX_FREQ, rate,
476 ret = __clk_sscg_pll_determine_rate(hw, req, PLL_REF_MIN_FREQ,
477 PLL_REF_MAX_FREQ, rate,
482 if (setup->fout >= min && setup->fout <= max)
488 static const struct clk_ops clk_sscg_pll_ops = {
489 .prepare = clk_sscg_pll_prepare,
490 .unprepare = clk_sscg_pll_unprepare,
491 .is_prepared = clk_sscg_pll_is_prepared,
492 .recalc_rate = clk_sscg_pll_recalc_rate,
493 .set_rate = clk_sscg_pll_set_rate,
494 .set_parent = clk_sscg_pll_set_parent,
495 .get_parent = clk_sscg_pll_get_parent,
496 .determine_rate = clk_sscg_pll_determine_rate,
499 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
500 const char * const *parent_names,
502 u8 parent, u8 bypass1, u8 bypass2,
506 struct clk_sscg_pll *pll;
507 struct clk_init_data init;
511 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
513 return ERR_PTR(-ENOMEM);
515 pll->parent = parent;
516 pll->bypass1 = bypass1;
517 pll->bypass2 = bypass2;
521 init.ops = &clk_sscg_pll_ops;
524 init.parent_names = parent_names;
525 init.num_parents = num_parents;
528 pll->hw.init = &init;
532 ret = clk_hw_register(NULL, hw);