1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2018-2021 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com>
7 #ifndef __IMX_CLK_SCU_H
8 #define __IMX_CLK_SCU_H
10 #include <linux/firmware/imx/sci.h>
13 #define IMX_SCU_GPR_CLK_GATE BIT(0)
14 #define IMX_SCU_GPR_CLK_DIV BIT(1)
15 #define IMX_SCU_GPR_CLK_MUX BIT(2)
17 struct imx_clk_scu_rsrc_table {
22 extern struct list_head imx_scu_clks[];
23 extern const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops;
24 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl;
25 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qxp;
26 extern const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm;
28 int imx_clk_scu_init(struct device_node *np,
29 const struct imx_clk_scu_rsrc_table *data);
30 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
32 struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
33 const char * const *parents,
34 int num_parents, u32 rsrc_id, u8 clk_type);
36 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
37 const char * const *parents, int num_parents,
38 u32 rsrc_id, u8 clk_type);
40 void imx_clk_scu_unregister(void);
42 struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags,
44 void __iomem *reg, u8 bit_idx, bool hw_gate);
45 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
47 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
48 int num_parents, u32 rsrc_id, u8 gpr_id, u8 flags,
51 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
54 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type);
57 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
58 int num_parents, u32 rsrc_id, u8 clk_type)
60 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type);
63 static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
64 const char *parent_name, unsigned long flags,
65 void __iomem *reg, u8 bit_idx, bool hw_gate)
67 return __imx_clk_lpcg_scu(dev, name, parent_name, flags, reg,
71 static inline struct clk_hw *imx_clk_lpcg_scu(const char *name, const char *parent_name,
72 unsigned long flags, void __iomem *reg,
73 u8 bit_idx, bool hw_gate)
75 return __imx_clk_lpcg_scu(NULL, name, parent_name, flags, reg,
79 static inline struct clk_hw *imx_clk_gate_gpr_scu(const char *name, const char *parent_name,
80 u32 rsrc_id, u8 gpr_id, bool invert)
82 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
83 IMX_SCU_GPR_CLK_GATE, invert);
86 static inline struct clk_hw *imx_clk_divider_gpr_scu(const char *name, const char *parent_name,
87 u32 rsrc_id, u8 gpr_id)
89 return __imx_clk_gpr_scu(name, &parent_name, 1, rsrc_id, gpr_id,
90 IMX_SCU_GPR_CLK_DIV, 0);
93 static inline struct clk_hw *imx_clk_mux_gpr_scu(const char *name, const char * const *parent_names,
94 int num_parents, u32 rsrc_id, u8 gpr_id)
96 return __imx_clk_gpr_scu(name, parent_names, num_parents, rsrc_id,
97 gpr_id, IMX_SCU_GPR_CLK_MUX, 0);