drivers/clk/imx/clk-sccg-pll.c

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Copyright 2018 NXP.
   4  *
   5  * This driver supports the SCCG plls found in the imx8m SOCs
   6  *
   7  * Documentation for this SCCG pll can be found at:
   8  *   https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
   9  */
  10
  11 #include <linux/clk-provider.h>
  12 #include <linux/err.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/slab.h>
  15 #include <linux/bitfield.h>
  16
  17 #include "clk.h"
  18
  19 /* PLL CFGs */
  20 #define PLL_CFG0                0x0
  21 #define PLL_CFG1                0x4
  22 #define PLL_CFG2                0x8
  23
  24 #define PLL_DIVF1_MASK          GENMASK(18, 13)
  25 #define PLL_DIVF2_MASK          GENMASK(12, 7)
  26 #define PLL_DIVR1_MASK          GENMASK(27, 25)
  27 #define PLL_DIVR2_MASK          GENMASK(24, 19)
  28 #define PLL_DIVQ_MASK           GENMASK(6, 1)
  29 #define PLL_REF_MASK            GENMASK(2, 0)
  30
  31 #define PLL_LOCK_MASK           BIT(31)
  32 #define PLL_PD_MASK             BIT(7)
  33
  34 /* These are the specification limits for the SSCG PLL */
  35 #define PLL_REF_MIN_FREQ                25000000UL
  36 #define PLL_REF_MAX_FREQ                235000000UL
  37
  38 #define PLL_STAGE1_MIN_FREQ             1600000000UL
  39 #define PLL_STAGE1_MAX_FREQ             2400000000UL
  40
  41 #define PLL_STAGE1_REF_MIN_FREQ         25000000UL
  42 #define PLL_STAGE1_REF_MAX_FREQ         54000000UL
  43
  44 #define PLL_STAGE2_MIN_FREQ             1200000000UL
  45 #define PLL_STAGE2_MAX_FREQ             2400000000UL
  46
  47 #define PLL_STAGE2_REF_MIN_FREQ         54000000UL
  48 #define PLL_STAGE2_REF_MAX_FREQ         75000000UL
  49
  50 #define PLL_OUT_MIN_FREQ                20000000UL
  51 #define PLL_OUT_MAX_FREQ                1200000000UL
  52
  53 #define PLL_DIVR1_MAX                   7
  54 #define PLL_DIVR2_MAX                   63
  55 #define PLL_DIVF1_MAX                   63
  56 #define PLL_DIVF2_MAX                   63
  57 #define PLL_DIVQ_MAX                    63
  58
  59 #define PLL_BYPASS_NONE                 0x0
  60 #define PLL_BYPASS1                     0x2
  61 #define PLL_BYPASS2                     0x1
  62
  63 #define SSCG_PLL_BYPASS1_MASK           BIT(5)
  64 #define SSCG_PLL_BYPASS2_MASK           BIT(4)
  65 #define SSCG_PLL_BYPASS_MASK            GENMASK(5, 4)
  66
  67 #define PLL_SCCG_LOCK_TIMEOUT           70
  68
  69 struct clk_sccg_pll_setup {
  70         int divr1, divf1;
  71         int divr2, divf2;
  72         int divq;
  73         int bypass;
  74
  75         uint64_t vco1;
  76         uint64_t vco2;
  77         uint64_t fout;
  78         uint64_t ref;
  79         uint64_t ref_div1;
  80         uint64_t ref_div2;
  81         uint64_t fout_request;
  82         int fout_error;
  83 };
  84
  85 struct clk_sccg_pll {
  86         struct clk_hw   hw;
  87         const struct clk_ops  ops;
  88
  89         void __iomem *base;
  90
  91         struct clk_sccg_pll_setup setup;
  92
  93         u8 parent;
  94         u8 bypass1;
  95         u8 bypass2;
  96 };
  97
  98 #define to_clk_sccg_pll(_hw) container_of(_hw, struct clk_sccg_pll, hw)
  99
 100 static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll)
 101 {
 102         u32 val;
 103
 104         val = readl_relaxed(pll->base + PLL_CFG0);
 105
 106         /* don't wait for lock if all plls are bypassed */
 107         if (!(val & SSCG_PLL_BYPASS2_MASK))
 108                 return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
 109                                                 0, PLL_SCCG_LOCK_TIMEOUT);
 110
 111         return 0;
 112 }
 113
 114 static int clk_sccg_pll2_check_match(struct clk_sccg_pll_setup *setup,
 115                                         struct clk_sccg_pll_setup *temp_setup)
 116 {
 117         int new_diff = temp_setup->fout - temp_setup->fout_request;
 118         int diff = temp_setup->fout_error;
 119
 120         if (abs(diff) > abs(new_diff)) {
 121                 temp_setup->fout_error = new_diff;
 122                 memcpy(setup, temp_setup, sizeof(struct clk_sccg_pll_setup));
 123
 124                 if (temp_setup->fout_request == temp_setup->fout)
 125                         return 0;
 126         }
 127         return -1;
 128 }
 129
 130 static int clk_sccg_divq_lookup(struct clk_sccg_pll_setup *setup,
 131                                 struct clk_sccg_pll_setup *temp_setup)
 132 {
 133         int ret = -EINVAL;
 134
 135         for (temp_setup->divq = 0; temp_setup->divq <= PLL_DIVQ_MAX;
 136              temp_setup->divq++) {
 137                 temp_setup->vco2 = temp_setup->vco1;
 138                 do_div(temp_setup->vco2, temp_setup->divr2 + 1);
 139                 temp_setup->vco2 *= 2;
 140                 temp_setup->vco2 *= temp_setup->divf2 + 1;
 141                 if (temp_setup->vco2 >= PLL_STAGE2_MIN_FREQ &&
 142                                 temp_setup->vco2 <= PLL_STAGE2_MAX_FREQ) {
 143                         temp_setup->fout = temp_setup->vco2;
 144                         do_div(temp_setup->fout, 2 * (temp_setup->divq + 1));
 145
 146                         ret = clk_sccg_pll2_check_match(setup, temp_setup);
 147                         if (!ret) {
 148                                 temp_setup->bypass = PLL_BYPASS1;
 149                                 return ret;
 150                         }
 151                 }
 152         }
 153
 154         return ret;
 155 }
 156
 157 static int clk_sccg_divf2_lookup(struct clk_sccg_pll_setup *setup,
 158                                         struct clk_sccg_pll_setup *temp_setup)
 159 {
 160         int ret = -EINVAL;
 161
 162         for (temp_setup->divf2 = 0; temp_setup->divf2 <= PLL_DIVF2_MAX;
 163              temp_setup->divf2++) {
 164                 ret = clk_sccg_divq_lookup(setup, temp_setup);
 165                 if (!ret)
 166                         return ret;
 167         }
 168
 169         return ret;
 170 }
 171
 172 static int clk_sccg_divr2_lookup(struct clk_sccg_pll_setup *setup,
 173                                 struct clk_sccg_pll_setup *temp_setup)
 174 {
 175         int ret = -EINVAL;
 176
 177         for (temp_setup->divr2 = 0; temp_setup->divr2 <= PLL_DIVR2_MAX;
 178              temp_setup->divr2++) {
 179                 temp_setup->ref_div2 = temp_setup->vco1;
 180                 do_div(temp_setup->ref_div2, temp_setup->divr2 + 1);
 181                 if (temp_setup->ref_div2 >= PLL_STAGE2_REF_MIN_FREQ &&
 182                     temp_setup->ref_div2 <= PLL_STAGE2_REF_MAX_FREQ) {
 183                         ret = clk_sccg_divf2_lookup(setup, temp_setup);
 184                         if (!ret)
 185                                 return ret;
 186                 }
 187         }
 188
 189         return ret;
 190 }
 191
 192 static int clk_sccg_pll2_find_setup(struct clk_sccg_pll_setup *setup,
 193                                         struct clk_sccg_pll_setup *temp_setup,
 194                                         uint64_t ref)
 195 {
 196
 197         int ret = -EINVAL;
 198
 199         if (ref < PLL_STAGE1_MIN_FREQ || ref > PLL_STAGE1_MAX_FREQ)
 200                 return ret;
 201
 202         temp_setup->vco1 = ref;
 203
 204         ret = clk_sccg_divr2_lookup(setup, temp_setup);
 205         return ret;
 206 }
 207
 208 static int clk_sccg_divf1_lookup(struct clk_sccg_pll_setup *setup,
 209                                 struct clk_sccg_pll_setup *temp_setup)
 210 {
 211         int ret = -EINVAL;
 212
 213         for (temp_setup->divf1 = 0; temp_setup->divf1 <= PLL_DIVF1_MAX;
 214              temp_setup->divf1++) {
 215                 uint64_t vco1 = temp_setup->ref;
 216
 217                 do_div(vco1, temp_setup->divr1 + 1);
 218                 vco1 *= 2;
 219                 vco1 *= temp_setup->divf1 + 1;
 220
 221                 ret = clk_sccg_pll2_find_setup(setup, temp_setup, vco1);
 222                 if (!ret) {
 223                         temp_setup->bypass = PLL_BYPASS_NONE;
 224                         return ret;
 225                 }
 226         }
 227
 228         return ret;
 229 }
 230
 231 static int clk_sccg_divr1_lookup(struct clk_sccg_pll_setup *setup,
 232                                 struct clk_sccg_pll_setup *temp_setup)
 233 {
 234         int ret = -EINVAL;
 235
 236         for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX;
 237              temp_setup->divr1++) {
 238                 temp_setup->ref_div1 = temp_setup->ref;
 239                 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1);
 240                 if (temp_setup->ref_div1 >= PLL_STAGE1_REF_MIN_FREQ &&
 241                     temp_setup->ref_div1 <= PLL_STAGE1_REF_MAX_FREQ) {
 242                         ret = clk_sccg_divf1_lookup(setup, temp_setup);
 243                         if (!ret)
 244                                 return ret;
 245                 }
 246         }
 247
 248         return ret;
 249 }
 250
 251 static int clk_sccg_pll1_find_setup(struct clk_sccg_pll_setup *setup,
 252                                         struct clk_sccg_pll_setup *temp_setup,
 253                                         uint64_t ref)
 254 {
 255
 256         int ret = -EINVAL;
 257
 258         if (ref < PLL_REF_MIN_FREQ || ref > PLL_REF_MAX_FREQ)
 259                 return ret;
 260
 261         temp_setup->ref = ref;
 262
 263         ret = clk_sccg_divr1_lookup(setup, temp_setup);
 264
 265         return ret;
 266 }
 267
 268 static int clk_sccg_pll_find_setup(struct clk_sccg_pll_setup *setup,
 269                                         uint64_t prate,
 270                                         uint64_t rate, int try_bypass)
 271 {
 272         struct clk_sccg_pll_setup temp_setup;
 273         int ret = -EINVAL;
 274
 275         memset(&temp_setup, 0, sizeof(struct clk_sccg_pll_setup));
 276         memset(setup, 0, sizeof(struct clk_sccg_pll_setup));
 277
 278         temp_setup.fout_error = PLL_OUT_MAX_FREQ;
 279         temp_setup.fout_request = rate;
 280
 281         switch (try_bypass) {
 282
 283         case PLL_BYPASS2:
 284                 if (prate == rate) {
 285                         setup->bypass = PLL_BYPASS2;
 286                         setup->fout = rate;
 287                         ret = 0;
 288                 }
 289                 break;
 290
 291         case PLL_BYPASS1:
 292                 ret = clk_sccg_pll2_find_setup(setup, &temp_setup, prate);
 293                 break;
 294
 295         case PLL_BYPASS_NONE:
 296                 ret = clk_sccg_pll1_find_setup(setup, &temp_setup, prate);
 297                 break;
 298         }
 299
 300         return ret;
 301 }
 302
 303
 304 static int clk_sccg_pll_is_prepared(struct clk_hw *hw)
 305 {
 306         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 307
 308         u32 val = readl_relaxed(pll->base + PLL_CFG0);
 309
 310         return (val & PLL_PD_MASK) ? 0 : 1;
 311 }
 312
 313 static int clk_sccg_pll_prepare(struct clk_hw *hw)
 314 {
 315         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 316         u32 val;
 317
 318         val = readl_relaxed(pll->base + PLL_CFG0);
 319         val &= ~PLL_PD_MASK;
 320         writel_relaxed(val, pll->base + PLL_CFG0);
 321
 322         return clk_sccg_pll_wait_lock(pll);
 323 }
 324
 325 static void clk_sccg_pll_unprepare(struct clk_hw *hw)
 326 {
 327         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 328         u32 val;
 329
 330         val = readl_relaxed(pll->base + PLL_CFG0);
 331         val |= PLL_PD_MASK;
 332         writel_relaxed(val, pll->base + PLL_CFG0);
 333 }
 334
 335 static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
 336                                          unsigned long parent_rate)
 337 {
 338         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 339         u32 val, divr1, divf1, divr2, divf2, divq;
 340         u64 temp64;
 341
 342         val = readl_relaxed(pll->base + PLL_CFG2);
 343         divr1 = FIELD_GET(PLL_DIVR1_MASK, val);
 344         divr2 = FIELD_GET(PLL_DIVR2_MASK, val);
 345         divf1 = FIELD_GET(PLL_DIVF1_MASK, val);
 346         divf2 = FIELD_GET(PLL_DIVF2_MASK, val);
 347         divq = FIELD_GET(PLL_DIVQ_MASK, val);
 348
 349         temp64 = parent_rate;
 350
 351         val = clk_readl(pll->base + PLL_CFG0);
 352         if (val & SSCG_PLL_BYPASS2_MASK) {
 353                 temp64 = parent_rate;
 354         } else if (val & SSCG_PLL_BYPASS1_MASK) {
 355                 temp64 *= divf2;
 356                 do_div(temp64, (divr2 + 1) * (divq + 1));
 357         } else {
 358                 temp64 *= 2;
 359                 temp64 *= (divf1 + 1) * (divf2 + 1);
 360                 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1));
 361         }
 362
 363         return temp64;
 364 }
 365
 366 static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 367                             unsigned long parent_rate)
 368 {
 369         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 370         struct clk_sccg_pll_setup *setup = &pll->setup;
 371         u32 val;
 372
 373         /* set bypass here too since the parent might be the same */
 374         val = clk_readl(pll->base + PLL_CFG0);
 375         val &= ~SSCG_PLL_BYPASS_MASK;
 376         val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
 377         clk_writel(val, pll->base + PLL_CFG0);
 378
 379         val = readl_relaxed(pll->base + PLL_CFG2);
 380         val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
 381         val &= ~(PLL_DIVR1_MASK | PLL_DIVR2_MASK | PLL_DIVQ_MASK);
 382         val |= FIELD_PREP(PLL_DIVF1_MASK, setup->divf1);
 383         val |= FIELD_PREP(PLL_DIVF2_MASK, setup->divf2);
 384         val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1);
 385         val |= FIELD_PREP(PLL_DIVR2_MASK, setup->divr2);
 386         val |= FIELD_PREP(PLL_DIVQ_MASK, setup->divq);
 387         writel_relaxed(val, pll->base + PLL_CFG2);
 388
 389         return clk_sccg_pll_wait_lock(pll);
 390 }
 391
 392 static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
 393 {
 394         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 395         u32 val;
 396         u8 ret = pll->parent;
 397
 398         val = clk_readl(pll->base + PLL_CFG0);
 399         if (val & SSCG_PLL_BYPASS2_MASK)
 400                 ret = pll->bypass2;
 401         else if (val & SSCG_PLL_BYPASS1_MASK)
 402                 ret = pll->bypass1;
 403         return ret;
 404 }
 405
 406 static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
 407 {
 408         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 409         u32 val;
 410
 411         val = clk_readl(pll->base + PLL_CFG0);
 412         val &= ~SSCG_PLL_BYPASS_MASK;
 413         val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
 414         clk_writel(val, pll->base + PLL_CFG0);
 415
 416         return clk_sccg_pll_wait_lock(pll);
 417 }
 418
 419 static int __clk_sccg_pll_determine_rate(struct clk_hw *hw,
 420                                         struct clk_rate_request *req,
 421                                         uint64_t min,
 422                                         uint64_t max,
 423                                         uint64_t rate,
 424                                         int bypass)
 425 {
 426         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 427         struct clk_sccg_pll_setup *setup = &pll->setup;
 428         struct clk_hw *parent_hw = NULL;
 429         int bypass_parent_index;
 430         int ret = -EINVAL;
 431
 432         req->max_rate = max;
 433         req->min_rate = min;
 434
 435         switch (bypass) {
 436         case PLL_BYPASS2:
 437                 bypass_parent_index = pll->bypass2;
 438                 break;
 439         case PLL_BYPASS1:
 440                 bypass_parent_index = pll->bypass1;
 441                 break;
 442         default:
 443                 bypass_parent_index = pll->parent;
 444                 break;
 445         }
 446
 447         parent_hw = clk_hw_get_parent_by_index(hw, bypass_parent_index);
 448         ret = __clk_determine_rate(parent_hw, req);
 449         if (!ret) {
 450                 ret = clk_sccg_pll_find_setup(setup, req->rate,
 451                                                 rate, bypass);
 452         }
 453
 454         req->best_parent_hw = parent_hw;
 455         req->best_parent_rate = req->rate;
 456         req->rate = setup->fout;
 457
 458         return ret;
 459 }
 460
 461 static int clk_sccg_pll_determine_rate(struct clk_hw *hw,
 462                                        struct clk_rate_request *req)
 463 {
 464         struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
 465         struct clk_sccg_pll_setup *setup = &pll->setup;
 466         uint64_t rate = req->rate;
 467         uint64_t min = req->min_rate;
 468         uint64_t max = req->max_rate;
 469         int ret = -EINVAL;
 470
 471         if (rate < PLL_OUT_MIN_FREQ || rate > PLL_OUT_MAX_FREQ)
 472                 return ret;
 473
 474         ret = __clk_sccg_pll_determine_rate(hw, req, req->rate, req->rate,
 475                                                 rate, PLL_BYPASS2);
 476         if (!ret)
 477                 return ret;
 478
 479         ret = __clk_sccg_pll_determine_rate(hw, req, PLL_STAGE1_REF_MIN_FREQ,
 480                                                 PLL_STAGE1_REF_MAX_FREQ, rate,
 481                                                 PLL_BYPASS1);
 482         if (!ret)
 483                 return ret;
 484
 485         ret = __clk_sccg_pll_determine_rate(hw, req, PLL_REF_MIN_FREQ,
 486                                                 PLL_REF_MAX_FREQ, rate,
 487                                                 PLL_BYPASS_NONE);
 488         if (!ret)
 489                 return ret;
 490
 491         if (setup->fout >= min && setup->fout <= max)
 492                 ret = 0;
 493
 494         return ret;
 495 }
 496
 497 static const struct clk_ops clk_sccg_pll_ops = {
 498         .prepare        = clk_sccg_pll_prepare,
 499         .unprepare      = clk_sccg_pll_unprepare,
 500         .is_prepared    = clk_sccg_pll_is_prepared,
 501         .recalc_rate    = clk_sccg_pll_recalc_rate,
 502         .set_rate       = clk_sccg_pll_set_rate,
 503         .set_parent     = clk_sccg_pll_set_parent,
 504         .get_parent     = clk_sccg_pll_get_parent,
 505         .determine_rate = clk_sccg_pll_determine_rate,
 506 };
 507
 508 struct clk *imx_clk_sccg_pll(const char *name,
 509                                 const char * const *parent_names,
 510                                 u8 num_parents,
 511                                 u8 parent, u8 bypass1, u8 bypass2,
 512                                 void __iomem *base,
 513                                 unsigned long flags)
 514 {
 515         struct clk_sccg_pll *pll;
 516         struct clk_init_data init;
 517         struct clk_hw *hw;
 518         int ret;
 519
 520         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 521         if (!pll)
 522                 return ERR_PTR(-ENOMEM);
 523
 524         pll->parent = parent;
 525         pll->bypass1 = bypass1;
 526         pll->bypass2 = bypass2;
 527
 528         pll->base = base;
 529         init.name = name;
 530         init.ops = &clk_sccg_pll_ops;
 531
 532         init.flags = flags;
 533         init.parent_names = parent_names;
 534         init.num_parents = num_parents;
 535
 536         pll->base = base;
 537         pll->hw.init = &init;
 538
 539         hw = &pll->hw;
 540
 541         ret = clk_hw_register(NULL, hw);
 542         if (ret) {
 543                 kfree(pll);
 544                 return ERR_PTR(ret);
 545         }
 546
 547         return hw->clk;
 548 }