1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 * Copyright 2017~2018 NXP
6 * Author: Dong Aisheng <aisheng.dong@nxp.com>
10 #include <linux/clk-provider.h>
11 #include <linux/err.h>
13 #include <linux/iopoll.h>
14 #include <linux/slab.h>
18 /* PLL Control Status Register (xPLLCSR) */
19 #define PLL_CSR_OFFSET 0x0
20 #define PLL_VLD BIT(24)
23 /* PLL Configuration Register (xPLLCFG) */
24 #define PLL_CFG_OFFSET 0x08
25 #define BP_PLL_MULT 16
26 #define BM_PLL_MULT (0x7f << 16)
28 /* PLL Numerator Register (xPLLNUM) */
29 #define PLL_NUM_OFFSET 0x10
31 /* PLL Denominator Register (xPLLDENOM) */
32 #define PLL_DENOM_OFFSET 0x14
34 #define MAX_MFD 0x3fffffff
35 #define DEFAULT_MFD 1000000
42 /* Valid PLL MULT Table */
43 static const int pllv4_mult_table[] = {33, 27, 22, 20, 17, 16};
45 #define to_clk_pllv4(__hw) container_of(__hw, struct clk_pllv4, hw)
47 #define LOCK_TIMEOUT_US USEC_PER_MSEC
49 static inline int clk_pllv4_wait_lock(struct clk_pllv4 *pll)
53 return readl_poll_timeout(pll->base + PLL_CSR_OFFSET,
54 csr, csr & PLL_VLD, 0, LOCK_TIMEOUT_US);
57 static int clk_pllv4_is_prepared(struct clk_hw *hw)
59 struct clk_pllv4 *pll = to_clk_pllv4(hw);
61 if (readl_relaxed(pll->base) & PLL_EN)
67 static unsigned long clk_pllv4_recalc_rate(struct clk_hw *hw,
68 unsigned long parent_rate)
70 struct clk_pllv4 *pll = to_clk_pllv4(hw);
74 mult = readl_relaxed(pll->base + PLL_CFG_OFFSET);
78 mfn = readl_relaxed(pll->base + PLL_NUM_OFFSET);
79 mfd = readl_relaxed(pll->base + PLL_DENOM_OFFSET);
84 return (parent_rate * mult) + (u32)temp64;
87 static long clk_pllv4_round_rate(struct clk_hw *hw, unsigned long rate,
90 unsigned long parent_rate = *prate;
91 unsigned long round_rate, i;
92 u32 mfn, mfd = DEFAULT_MFD;
96 for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
97 round_rate = parent_rate * pllv4_mult_table[i];
98 if (rate >= round_rate) {
105 pr_warn("%s: unable to round rate %lu, parent rate %lu\n",
106 clk_hw_get_name(hw), rate, parent_rate);
110 if (parent_rate <= MAX_MFD)
113 temp64 = (u64)(rate - round_rate);
115 do_div(temp64, parent_rate);
119 * NOTE: The value of numerator must always be configured to be
120 * less than the value of the denominator. If we can't get a proper
121 * pair of mfn/mfd, we simply return the round_rate without using
127 temp64 = (u64)parent_rate;
131 return round_rate + (u32)temp64;
134 static bool clk_pllv4_is_valid_mult(unsigned int mult)
138 /* check if mult is in valid MULT table */
139 for (i = 0; i < ARRAY_SIZE(pllv4_mult_table); i++) {
140 if (pllv4_mult_table[i] == mult)
147 static int clk_pllv4_set_rate(struct clk_hw *hw, unsigned long rate,
148 unsigned long parent_rate)
150 struct clk_pllv4 *pll = to_clk_pllv4(hw);
151 u32 val, mult, mfn, mfd = DEFAULT_MFD;
154 mult = rate / parent_rate;
156 if (!clk_pllv4_is_valid_mult(mult))
159 if (parent_rate <= MAX_MFD)
162 temp64 = (u64)(rate - mult * parent_rate);
164 do_div(temp64, parent_rate);
167 val = readl_relaxed(pll->base + PLL_CFG_OFFSET);
169 val |= mult << BP_PLL_MULT;
170 writel_relaxed(val, pll->base + PLL_CFG_OFFSET);
172 writel_relaxed(mfn, pll->base + PLL_NUM_OFFSET);
173 writel_relaxed(mfd, pll->base + PLL_DENOM_OFFSET);
178 static int clk_pllv4_prepare(struct clk_hw *hw)
181 struct clk_pllv4 *pll = to_clk_pllv4(hw);
183 val = readl_relaxed(pll->base);
185 writel_relaxed(val, pll->base);
187 return clk_pllv4_wait_lock(pll);
190 static void clk_pllv4_unprepare(struct clk_hw *hw)
193 struct clk_pllv4 *pll = to_clk_pllv4(hw);
195 val = readl_relaxed(pll->base);
197 writel_relaxed(val, pll->base);
200 static const struct clk_ops clk_pllv4_ops = {
201 .recalc_rate = clk_pllv4_recalc_rate,
202 .round_rate = clk_pllv4_round_rate,
203 .set_rate = clk_pllv4_set_rate,
204 .prepare = clk_pllv4_prepare,
205 .unprepare = clk_pllv4_unprepare,
206 .is_prepared = clk_pllv4_is_prepared,
209 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
212 struct clk_pllv4 *pll;
214 struct clk_init_data init;
217 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
219 return ERR_PTR(-ENOMEM);
224 init.ops = &clk_pllv4_ops;
225 init.parent_names = &parent_name;
226 init.num_parents = 1;
227 init.flags = CLK_SET_RATE_GATE;
229 pll->hw.init = &init;
232 ret = clk_hw_register(NULL, hw);