1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/bits.h>
3 #include <linux/clk-provider.h>
5 #include <linux/slab.h>
6 #include <linux/kernel.h>
14 * @clk_hw clock source
15 * @parent the parent clock name
16 * @base base address of pll registers
18 * PLL clock version 1, found on i.MX1/21/25/27/31/35
22 #define MFN_SIGN (BIT(MFN_BITS - 1))
23 #define MFN_MASK (MFN_SIGN - 1)
28 enum imx_pllv1_type type;
31 #define to_clk_pllv1(clk) (container_of(clk, struct clk_pllv1, clk))
33 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll)
35 return pll->type == IMX_PLLV1_IMX1;
38 static inline bool is_imx21_pllv1(struct clk_pllv1 *pll)
40 return pll->type == IMX_PLLV1_IMX21;
43 static inline bool is_imx27_pllv1(struct clk_pllv1 *pll)
45 return pll->type == IMX_PLLV1_IMX27;
48 static inline bool mfn_is_negative(struct clk_pllv1 *pll, unsigned int mfn)
50 return !is_imx1_pllv1(pll) && !is_imx21_pllv1(pll) && (mfn & MFN_SIGN);
53 static unsigned long clk_pllv1_recalc_rate(struct clk_hw *hw,
54 unsigned long parent_rate)
56 struct clk_pllv1 *pll = to_clk_pllv1(hw);
57 unsigned long long ull;
59 unsigned int mfi, mfn, mfd, pd;
63 reg = readl(pll->base);
66 * Get the resulting clock rate from a PLL register value and the input
67 * frequency. PLLs with this register layout can be found on i.MX1,
68 * i.MX21, i.MX27 and i,MX31
70 * mfi + mfn / (mfd + 1)
71 * f = 2 * f_ref * --------------------
75 mfi = (reg >> 10) & 0xf;
77 mfd = (reg >> 16) & 0x3ff;
78 pd = (reg >> 26) & 0xf;
80 mfi = mfi <= 5 ? 5 : mfi;
85 * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
86 * 2's complements number.
87 * On i.MX27 the bit 9 is the sign bit.
89 if (mfn_is_negative(pll, mfn)) {
90 if (is_imx27_pllv1(pll))
91 mfn_abs = mfn & MFN_MASK;
93 mfn_abs = BIT(MFN_BITS) - mfn;
96 rate = parent_rate * 2;
99 ull = (unsigned long long)rate * mfn_abs;
101 do_div(ull, mfd + 1);
103 if (mfn_is_negative(pll, mfn))
104 ull = (rate * mfi) - ull;
106 ull = (rate * mfi) + ull;
111 static const struct clk_ops clk_pllv1_ops = {
112 .recalc_rate = clk_pllv1_recalc_rate,
115 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
116 const char *parent, void __iomem *base)
118 struct clk_pllv1 *pll;
120 struct clk_init_data init;
123 pll = kmalloc(sizeof(*pll), GFP_KERNEL);
125 return ERR_PTR(-ENOMEM);
131 init.ops = &clk_pllv1_ops;
133 init.parent_names = &parent;
134 init.num_parents = 1;
136 pll->hw.init = &init;
139 ret = clk_hw_register(NULL, hw);