1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
6 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
10 #include <linux/iopoll.h>
11 #include <linux/slab.h>
12 #include <linux/jiffies.h>
18 #define LOCK_STATUS BIT(31)
19 #define LOCK_SEL_MASK BIT(29)
20 #define CLKE_MASK BIT(11)
21 #define RST_MASK BIT(9)
22 #define BYPASS_MASK BIT(4)
24 #define MDIV_MASK GENMASK(21, 12)
26 #define PDIV_MASK GENMASK(9, 4)
28 #define SDIV_MASK GENMASK(2, 0)
30 #define KDIV_MASK GENMASK(15, 0)
32 #define LOCK_TIMEOUT_US 10000
37 enum imx_pll14xx_type type;
38 const struct imx_pll14xx_rate_table *rate_table;
42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
44 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
45 PLL_1416X_RATE(1800000000U, 225, 3, 0),
46 PLL_1416X_RATE(1600000000U, 200, 3, 0),
47 PLL_1416X_RATE(1500000000U, 375, 3, 1),
48 PLL_1416X_RATE(1400000000U, 350, 3, 1),
49 PLL_1416X_RATE(1200000000U, 300, 3, 1),
50 PLL_1416X_RATE(1000000000U, 250, 3, 1),
51 PLL_1416X_RATE(800000000U, 200, 3, 1),
52 PLL_1416X_RATE(750000000U, 250, 2, 2),
53 PLL_1416X_RATE(700000000U, 350, 3, 2),
54 PLL_1416X_RATE(600000000U, 300, 3, 2),
57 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
58 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
59 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
60 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
61 PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
62 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
63 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
66 struct imx_pll14xx_clk imx_1443x_pll = {
68 .rate_table = imx_pll1443x_tbl,
69 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
72 struct imx_pll14xx_clk imx_1443x_dram_pll = {
74 .rate_table = imx_pll1443x_tbl,
75 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
76 .flags = CLK_GET_RATE_NOCACHE,
79 struct imx_pll14xx_clk imx_1416x_pll = {
81 .rate_table = imx_pll1416x_tbl,
82 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
85 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
86 struct clk_pll14xx *pll, unsigned long rate)
88 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
91 for (i = 0; i < pll->rate_count; i++)
92 if (rate == rate_table[i].rate)
93 return &rate_table[i];
98 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
101 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
102 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
105 /* Assumming rate_table is in descending order */
106 for (i = 0; i < pll->rate_count; i++)
107 if (rate >= rate_table[i].rate)
108 return rate_table[i].rate;
110 /* return minimum supported value */
111 return rate_table[i - 1].rate;
114 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
115 unsigned long parent_rate)
117 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
118 u32 mdiv, pdiv, sdiv, pll_div;
119 u64 fvco = parent_rate;
121 pll_div = readl_relaxed(pll->base + 4);
122 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
123 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
124 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
127 do_div(fvco, pdiv << sdiv);
132 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
133 unsigned long parent_rate)
135 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
136 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
138 u64 fvco = parent_rate;
140 pll_div_ctl0 = readl_relaxed(pll->base + 4);
141 pll_div_ctl1 = readl_relaxed(pll->base + 8);
142 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
143 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
144 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
145 kdiv = pll_div_ctl1 & KDIV_MASK;
147 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
148 fvco *= (mdiv * 65536 + kdiv);
151 do_div(fvco, pdiv << sdiv);
156 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
159 u32 old_mdiv, old_pdiv;
161 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
162 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
164 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
167 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
171 return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
175 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
178 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
179 const struct imx_pll14xx_rate_table *rate;
183 rate = imx_get_pll_settings(pll, drate);
185 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
186 drate, clk_hw_get_name(hw));
190 tmp = readl_relaxed(pll->base + 4);
192 if (!clk_pll14xx_mp_change(rate, tmp)) {
193 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
194 tmp |= rate->sdiv << SDIV_SHIFT;
195 writel_relaxed(tmp, pll->base + 4);
200 /* Bypass clock and set lock to pll output lock */
201 tmp = readl_relaxed(pll->base);
202 tmp |= LOCK_SEL_MASK;
203 writel_relaxed(tmp, pll->base);
207 writel_relaxed(tmp, pll->base);
211 writel(tmp, pll->base);
213 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
214 (rate->sdiv << SDIV_SHIFT);
215 writel_relaxed(div_val, pll->base + 0x4);
218 * According to SPEC, t3 - t2 need to be greater than
219 * 1us and 1/FREF, respectively.
220 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
227 writel_relaxed(tmp, pll->base);
230 ret = clk_pll14xx_wait_lock(pll);
236 writel_relaxed(tmp, pll->base);
241 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
244 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
245 const struct imx_pll14xx_rate_table *rate;
249 rate = imx_get_pll_settings(pll, drate);
251 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
252 drate, clk_hw_get_name(hw));
256 tmp = readl_relaxed(pll->base + 4);
258 if (!clk_pll14xx_mp_change(rate, tmp)) {
259 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
260 tmp |= rate->sdiv << SDIV_SHIFT;
261 writel_relaxed(tmp, pll->base + 4);
263 tmp = rate->kdiv << KDIV_SHIFT;
264 writel_relaxed(tmp, pll->base + 8);
270 tmp = readl_relaxed(pll->base);
272 writel_relaxed(tmp, pll->base);
276 writel_relaxed(tmp, pll->base);
278 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
279 (rate->sdiv << SDIV_SHIFT);
280 writel_relaxed(div_val, pll->base + 0x4);
281 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
284 * According to SPEC, t3 - t2 need to be greater than
285 * 1us and 1/FREF, respectively.
286 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
293 writel_relaxed(tmp, pll->base);
296 ret = clk_pll14xx_wait_lock(pll);
302 writel_relaxed(tmp, pll->base);
307 static int clk_pll14xx_prepare(struct clk_hw *hw)
309 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
314 * RESETB = 1 from 0, PLL starts its normal
315 * operation after lock time
317 val = readl_relaxed(pll->base + GNRL_CTL);
321 writel_relaxed(val, pll->base + GNRL_CTL);
323 writel_relaxed(val, pll->base + GNRL_CTL);
325 ret = clk_pll14xx_wait_lock(pll);
330 writel_relaxed(val, pll->base + GNRL_CTL);
335 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
337 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
340 val = readl_relaxed(pll->base + GNRL_CTL);
342 return (val & RST_MASK) ? 1 : 0;
345 static void clk_pll14xx_unprepare(struct clk_hw *hw)
347 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
351 * Set RST to 0, power down mode is enabled and
352 * every digital block is reset
354 val = readl_relaxed(pll->base + GNRL_CTL);
356 writel_relaxed(val, pll->base + GNRL_CTL);
359 static const struct clk_ops clk_pll1416x_ops = {
360 .prepare = clk_pll14xx_prepare,
361 .unprepare = clk_pll14xx_unprepare,
362 .is_prepared = clk_pll14xx_is_prepared,
363 .recalc_rate = clk_pll1416x_recalc_rate,
364 .round_rate = clk_pll14xx_round_rate,
365 .set_rate = clk_pll1416x_set_rate,
368 static const struct clk_ops clk_pll1416x_min_ops = {
369 .recalc_rate = clk_pll1416x_recalc_rate,
372 static const struct clk_ops clk_pll1443x_ops = {
373 .prepare = clk_pll14xx_prepare,
374 .unprepare = clk_pll14xx_unprepare,
375 .is_prepared = clk_pll14xx_is_prepared,
376 .recalc_rate = clk_pll1443x_recalc_rate,
377 .round_rate = clk_pll14xx_round_rate,
378 .set_rate = clk_pll1443x_set_rate,
381 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
382 const char *parent_name, void __iomem *base,
383 const struct imx_pll14xx_clk *pll_clk)
385 struct clk_pll14xx *pll;
387 struct clk_init_data init;
391 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
393 return ERR_PTR(-ENOMEM);
396 init.flags = pll_clk->flags;
397 init.parent_names = &parent_name;
398 init.num_parents = 1;
400 switch (pll_clk->type) {
402 if (!pll_clk->rate_table)
403 init.ops = &clk_pll1416x_min_ops;
405 init.ops = &clk_pll1416x_ops;
408 init.ops = &clk_pll1443x_ops;
411 pr_err("%s: Unknown pll type for pll clk %s\n",
414 return ERR_PTR(-EINVAL);
418 pll->hw.init = &init;
419 pll->type = pll_clk->type;
420 pll->rate_table = pll_clk->rate_table;
421 pll->rate_count = pll_clk->rate_count;
423 val = readl_relaxed(pll->base + GNRL_CTL);
425 writel_relaxed(val, pll->base + GNRL_CTL);
429 ret = clk_hw_register(dev, hw);
431 pr_err("%s: failed to register pll %s %d\n",
432 __func__, name, ret);