1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
6 #include <linux/bits.h>
7 #include <linux/clk-provider.h>
9 #include <linux/export.h>
11 #include <linux/iopoll.h>
12 #include <linux/slab.h>
13 #include <linux/jiffies.h>
19 #define LOCK_STATUS BIT(31)
20 #define LOCK_SEL_MASK BIT(29)
21 #define CLKE_MASK BIT(11)
22 #define RST_MASK BIT(9)
23 #define BYPASS_MASK BIT(4)
25 #define MDIV_MASK GENMASK(21, 12)
27 #define PDIV_MASK GENMASK(9, 4)
29 #define SDIV_MASK GENMASK(2, 0)
31 #define KDIV_MASK GENMASK(15, 0)
33 #define LOCK_TIMEOUT_US 10000
38 enum imx_pll14xx_type type;
39 const struct imx_pll14xx_rate_table *rate_table;
43 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
45 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
46 PLL_1416X_RATE(1800000000U, 225, 3, 0),
47 PLL_1416X_RATE(1600000000U, 200, 3, 0),
48 PLL_1416X_RATE(1500000000U, 375, 3, 1),
49 PLL_1416X_RATE(1400000000U, 350, 3, 1),
50 PLL_1416X_RATE(1200000000U, 300, 3, 1),
51 PLL_1416X_RATE(1000000000U, 250, 3, 1),
52 PLL_1416X_RATE(800000000U, 200, 3, 1),
53 PLL_1416X_RATE(750000000U, 250, 2, 2),
54 PLL_1416X_RATE(700000000U, 350, 3, 2),
55 PLL_1416X_RATE(600000000U, 300, 3, 2),
58 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
59 PLL_1443X_RATE(1039500000U, 173, 2, 1, 16384),
60 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
61 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
62 PLL_1443X_RATE(519750000U, 173, 2, 2, 16384),
63 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
64 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
67 struct imx_pll14xx_clk imx_1443x_pll = {
69 .rate_table = imx_pll1443x_tbl,
70 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
72 EXPORT_SYMBOL_GPL(imx_1443x_pll);
74 struct imx_pll14xx_clk imx_1443x_dram_pll = {
76 .rate_table = imx_pll1443x_tbl,
77 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
78 .flags = CLK_GET_RATE_NOCACHE,
80 EXPORT_SYMBOL_GPL(imx_1443x_dram_pll);
82 struct imx_pll14xx_clk imx_1416x_pll = {
84 .rate_table = imx_pll1416x_tbl,
85 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
87 EXPORT_SYMBOL_GPL(imx_1416x_pll);
89 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
90 struct clk_pll14xx *pll, unsigned long rate)
92 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
95 for (i = 0; i < pll->rate_count; i++)
96 if (rate == rate_table[i].rate)
97 return &rate_table[i];
102 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
103 unsigned long *prate)
105 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
106 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
109 /* Assumming rate_table is in descending order */
110 for (i = 0; i < pll->rate_count; i++)
111 if (rate >= rate_table[i].rate)
112 return rate_table[i].rate;
114 /* return minimum supported value */
115 return rate_table[i - 1].rate;
118 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
119 unsigned long parent_rate)
121 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
122 u32 mdiv, pdiv, sdiv, pll_div;
123 u64 fvco = parent_rate;
125 pll_div = readl_relaxed(pll->base + 4);
126 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
127 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
128 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
131 do_div(fvco, pdiv << sdiv);
136 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
137 unsigned long parent_rate)
139 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
140 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
142 u64 fvco = parent_rate;
144 pll_div_ctl0 = readl_relaxed(pll->base + 4);
145 pll_div_ctl1 = readl_relaxed(pll->base + 8);
146 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
147 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
148 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
149 kdiv = pll_div_ctl1 & KDIV_MASK;
151 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
152 fvco *= (mdiv * 65536 + kdiv);
155 do_div(fvco, pdiv << sdiv);
160 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
163 u32 old_mdiv, old_pdiv;
165 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
166 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
168 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
171 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
175 return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
179 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
182 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
183 const struct imx_pll14xx_rate_table *rate;
187 rate = imx_get_pll_settings(pll, drate);
189 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
190 drate, clk_hw_get_name(hw));
194 tmp = readl_relaxed(pll->base + 4);
196 if (!clk_pll14xx_mp_change(rate, tmp)) {
197 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
198 tmp |= rate->sdiv << SDIV_SHIFT;
199 writel_relaxed(tmp, pll->base + 4);
204 /* Bypass clock and set lock to pll output lock */
205 tmp = readl_relaxed(pll->base);
206 tmp |= LOCK_SEL_MASK;
207 writel_relaxed(tmp, pll->base);
211 writel_relaxed(tmp, pll->base);
215 writel(tmp, pll->base);
217 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
218 (rate->sdiv << SDIV_SHIFT);
219 writel_relaxed(div_val, pll->base + 0x4);
222 * According to SPEC, t3 - t2 need to be greater than
223 * 1us and 1/FREF, respectively.
224 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
231 writel_relaxed(tmp, pll->base);
234 ret = clk_pll14xx_wait_lock(pll);
240 writel_relaxed(tmp, pll->base);
245 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
248 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
249 const struct imx_pll14xx_rate_table *rate;
253 rate = imx_get_pll_settings(pll, drate);
255 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
256 drate, clk_hw_get_name(hw));
260 tmp = readl_relaxed(pll->base + 4);
262 if (!clk_pll14xx_mp_change(rate, tmp)) {
263 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
264 tmp |= rate->sdiv << SDIV_SHIFT;
265 writel_relaxed(tmp, pll->base + 4);
267 tmp = rate->kdiv << KDIV_SHIFT;
268 writel_relaxed(tmp, pll->base + 8);
274 tmp = readl_relaxed(pll->base);
276 writel_relaxed(tmp, pll->base);
280 writel_relaxed(tmp, pll->base);
282 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
283 (rate->sdiv << SDIV_SHIFT);
284 writel_relaxed(div_val, pll->base + 0x4);
285 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
288 * According to SPEC, t3 - t2 need to be greater than
289 * 1us and 1/FREF, respectively.
290 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
297 writel_relaxed(tmp, pll->base);
300 ret = clk_pll14xx_wait_lock(pll);
306 writel_relaxed(tmp, pll->base);
311 static int clk_pll14xx_prepare(struct clk_hw *hw)
313 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
318 * RESETB = 1 from 0, PLL starts its normal
319 * operation after lock time
321 val = readl_relaxed(pll->base + GNRL_CTL);
325 writel_relaxed(val, pll->base + GNRL_CTL);
327 writel_relaxed(val, pll->base + GNRL_CTL);
329 ret = clk_pll14xx_wait_lock(pll);
334 writel_relaxed(val, pll->base + GNRL_CTL);
339 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
341 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
344 val = readl_relaxed(pll->base + GNRL_CTL);
346 return (val & RST_MASK) ? 1 : 0;
349 static void clk_pll14xx_unprepare(struct clk_hw *hw)
351 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
355 * Set RST to 0, power down mode is enabled and
356 * every digital block is reset
358 val = readl_relaxed(pll->base + GNRL_CTL);
360 writel_relaxed(val, pll->base + GNRL_CTL);
363 static const struct clk_ops clk_pll1416x_ops = {
364 .prepare = clk_pll14xx_prepare,
365 .unprepare = clk_pll14xx_unprepare,
366 .is_prepared = clk_pll14xx_is_prepared,
367 .recalc_rate = clk_pll1416x_recalc_rate,
368 .round_rate = clk_pll14xx_round_rate,
369 .set_rate = clk_pll1416x_set_rate,
372 static const struct clk_ops clk_pll1416x_min_ops = {
373 .recalc_rate = clk_pll1416x_recalc_rate,
376 static const struct clk_ops clk_pll1443x_ops = {
377 .prepare = clk_pll14xx_prepare,
378 .unprepare = clk_pll14xx_unprepare,
379 .is_prepared = clk_pll14xx_is_prepared,
380 .recalc_rate = clk_pll1443x_recalc_rate,
381 .round_rate = clk_pll14xx_round_rate,
382 .set_rate = clk_pll1443x_set_rate,
385 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
386 const char *parent_name, void __iomem *base,
387 const struct imx_pll14xx_clk *pll_clk)
389 struct clk_pll14xx *pll;
391 struct clk_init_data init;
395 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
397 return ERR_PTR(-ENOMEM);
400 init.flags = pll_clk->flags;
401 init.parent_names = &parent_name;
402 init.num_parents = 1;
404 switch (pll_clk->type) {
406 if (!pll_clk->rate_table)
407 init.ops = &clk_pll1416x_min_ops;
409 init.ops = &clk_pll1416x_ops;
412 init.ops = &clk_pll1443x_ops;
415 pr_err("%s: Unknown pll type for pll clk %s\n",
418 return ERR_PTR(-EINVAL);
422 pll->hw.init = &init;
423 pll->type = pll_clk->type;
424 pll->rate_table = pll_clk->rate_table;
425 pll->rate_count = pll_clk->rate_count;
427 val = readl_relaxed(pll->base + GNRL_CTL);
429 writel_relaxed(val, pll->base + GNRL_CTL);
433 ret = clk_hw_register(dev, hw);
435 pr_err("%s: failed to register pll %s %d\n",
436 __func__, name, ret);
443 EXPORT_SYMBOL_GPL(imx_dev_clk_hw_pll14xx);