1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
6 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
10 #include <linux/iopoll.h>
11 #include <linux/slab.h>
12 #include <linux/jiffies.h>
18 #define LOCK_STATUS BIT(31)
19 #define LOCK_SEL_MASK BIT(29)
20 #define CLKE_MASK BIT(11)
21 #define RST_MASK BIT(9)
22 #define BYPASS_MASK BIT(4)
24 #define MDIV_MASK GENMASK(21, 12)
26 #define PDIV_MASK GENMASK(9, 4)
28 #define SDIV_MASK GENMASK(2, 0)
30 #define KDIV_MASK GENMASK(15, 0)
32 #define LOCK_TIMEOUT_US 10000
37 enum imx_pll14xx_type type;
38 const struct imx_pll14xx_rate_table *rate_table;
42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
44 static const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] = {
45 PLL_1416X_RATE(1800000000U, 225, 3, 0),
46 PLL_1416X_RATE(1600000000U, 200, 3, 0),
47 PLL_1416X_RATE(1500000000U, 375, 3, 1),
48 PLL_1416X_RATE(1400000000U, 350, 3, 1),
49 PLL_1416X_RATE(1200000000U, 300, 3, 1),
50 PLL_1416X_RATE(1000000000U, 250, 3, 1),
51 PLL_1416X_RATE(800000000U, 200, 3, 1),
52 PLL_1416X_RATE(750000000U, 250, 2, 2),
53 PLL_1416X_RATE(700000000U, 350, 3, 2),
54 PLL_1416X_RATE(600000000U, 300, 3, 2),
57 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {
58 PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
59 PLL_1443X_RATE(594000000U, 198, 2, 2, 0),
60 PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),
61 PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),
64 struct imx_pll14xx_clk imx_1443x_pll = {
66 .rate_table = imx_pll1443x_tbl,
67 .rate_count = ARRAY_SIZE(imx_pll1443x_tbl),
70 struct imx_pll14xx_clk imx_1416x_pll = {
72 .rate_table = imx_pll1416x_tbl,
73 .rate_count = ARRAY_SIZE(imx_pll1416x_tbl),
76 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
77 struct clk_pll14xx *pll, unsigned long rate)
79 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
82 for (i = 0; i < pll->rate_count; i++)
83 if (rate == rate_table[i].rate)
84 return &rate_table[i];
89 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
92 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
93 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
96 /* Assumming rate_table is in descending order */
97 for (i = 0; i < pll->rate_count; i++)
98 if (rate >= rate_table[i].rate)
99 return rate_table[i].rate;
101 /* return minimum supported value */
102 return rate_table[i - 1].rate;
105 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
106 unsigned long parent_rate)
108 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
109 u32 mdiv, pdiv, sdiv, pll_div;
110 u64 fvco = parent_rate;
112 pll_div = readl_relaxed(pll->base + 4);
113 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
114 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
115 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
118 do_div(fvco, pdiv << sdiv);
123 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
126 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
127 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1;
129 u64 fvco = parent_rate;
131 pll_div_ctl0 = readl_relaxed(pll->base + 4);
132 pll_div_ctl1 = readl_relaxed(pll->base + 8);
133 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
134 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
135 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
136 kdiv = pll_div_ctl1 & KDIV_MASK;
138 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
139 fvco *= (mdiv * 65536 + kdiv);
142 do_div(fvco, pdiv << sdiv);
147 static inline bool clk_pll14xx_mp_change(const struct imx_pll14xx_rate_table *rate,
150 u32 old_mdiv, old_pdiv;
152 old_mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
153 old_pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
155 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
158 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
162 return readl_poll_timeout(pll->base, val, val & LOCK_STATUS, 0,
166 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
169 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
170 const struct imx_pll14xx_rate_table *rate;
174 rate = imx_get_pll_settings(pll, drate);
176 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
177 drate, clk_hw_get_name(hw));
181 tmp = readl_relaxed(pll->base + 4);
183 if (!clk_pll14xx_mp_change(rate, tmp)) {
184 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
185 tmp |= rate->sdiv << SDIV_SHIFT;
186 writel_relaxed(tmp, pll->base + 4);
191 /* Bypass clock and set lock to pll output lock */
192 tmp = readl_relaxed(pll->base);
193 tmp |= LOCK_SEL_MASK;
194 writel_relaxed(tmp, pll->base);
198 writel_relaxed(tmp, pll->base);
202 writel(tmp, pll->base);
204 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
205 (rate->sdiv << SDIV_SHIFT);
206 writel_relaxed(div_val, pll->base + 0x4);
209 * According to SPEC, t3 - t2 need to be greater than
210 * 1us and 1/FREF, respectively.
211 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
218 writel_relaxed(tmp, pll->base);
221 ret = clk_pll14xx_wait_lock(pll);
227 writel_relaxed(tmp, pll->base);
232 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
235 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
236 const struct imx_pll14xx_rate_table *rate;
240 rate = imx_get_pll_settings(pll, drate);
242 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
243 drate, clk_hw_get_name(hw));
247 tmp = readl_relaxed(pll->base + 4);
249 if (!clk_pll14xx_mp_change(rate, tmp)) {
250 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
251 tmp |= rate->sdiv << SDIV_SHIFT;
252 writel_relaxed(tmp, pll->base + 4);
254 tmp = rate->kdiv << KDIV_SHIFT;
255 writel_relaxed(tmp, pll->base + 8);
261 tmp = readl_relaxed(pll->base);
263 writel_relaxed(tmp, pll->base);
267 writel_relaxed(tmp, pll->base);
269 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
270 (rate->sdiv << SDIV_SHIFT);
271 writel_relaxed(div_val, pll->base + 0x4);
272 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
275 * According to SPEC, t3 - t2 need to be greater than
276 * 1us and 1/FREF, respectively.
277 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
284 writel_relaxed(tmp, pll->base);
287 ret = clk_pll14xx_wait_lock(pll);
293 writel_relaxed(tmp, pll->base);
298 static int clk_pll14xx_prepare(struct clk_hw *hw)
300 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
305 * RESETB = 1 from 0, PLL starts its normal
306 * operation after lock time
308 val = readl_relaxed(pll->base + GNRL_CTL);
312 writel_relaxed(val, pll->base + GNRL_CTL);
314 writel_relaxed(val, pll->base + GNRL_CTL);
316 ret = clk_pll14xx_wait_lock(pll);
321 writel_relaxed(val, pll->base + GNRL_CTL);
326 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
328 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
331 val = readl_relaxed(pll->base + GNRL_CTL);
333 return (val & RST_MASK) ? 1 : 0;
336 static void clk_pll14xx_unprepare(struct clk_hw *hw)
338 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
342 * Set RST to 0, power down mode is enabled and
343 * every digital block is reset
345 val = readl_relaxed(pll->base + GNRL_CTL);
347 writel_relaxed(val, pll->base + GNRL_CTL);
350 static const struct clk_ops clk_pll1416x_ops = {
351 .prepare = clk_pll14xx_prepare,
352 .unprepare = clk_pll14xx_unprepare,
353 .is_prepared = clk_pll14xx_is_prepared,
354 .recalc_rate = clk_pll1416x_recalc_rate,
355 .round_rate = clk_pll14xx_round_rate,
356 .set_rate = clk_pll1416x_set_rate,
359 static const struct clk_ops clk_pll1416x_min_ops = {
360 .recalc_rate = clk_pll1416x_recalc_rate,
363 static const struct clk_ops clk_pll1443x_ops = {
364 .prepare = clk_pll14xx_prepare,
365 .unprepare = clk_pll14xx_unprepare,
366 .is_prepared = clk_pll14xx_is_prepared,
367 .recalc_rate = clk_pll1443x_recalc_rate,
368 .round_rate = clk_pll14xx_round_rate,
369 .set_rate = clk_pll1443x_set_rate,
372 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
374 const struct imx_pll14xx_clk *pll_clk)
376 struct clk_pll14xx *pll;
378 struct clk_init_data init;
381 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
383 return ERR_PTR(-ENOMEM);
386 init.flags = pll_clk->flags;
387 init.parent_names = &parent_name;
388 init.num_parents = 1;
390 switch (pll_clk->type) {
392 if (!pll_clk->rate_table)
393 init.ops = &clk_pll1416x_min_ops;
395 init.ops = &clk_pll1416x_ops;
398 init.ops = &clk_pll1443x_ops;
401 pr_err("%s: Unknown pll type for pll clk %s\n",
406 pll->hw.init = &init;
407 pll->type = pll_clk->type;
408 pll->rate_table = pll_clk->rate_table;
409 pll->rate_count = pll_clk->rate_count;
411 val = readl_relaxed(pll->base + GNRL_CTL);
413 writel_relaxed(val, pll->base + GNRL_CTL);
415 clk = clk_register(NULL, &pll->hw);
417 pr_err("%s: failed to register pll %s %lu\n",
418 __func__, name, PTR_ERR(clk));