1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2017-2018 NXP.
6 #include <linux/bitops.h>
7 #include <linux/clk-provider.h>
10 #include <linux/iopoll.h>
11 #include <linux/slab.h>
12 #include <linux/jiffies.h>
18 #define LOCK_STATUS BIT(31)
19 #define LOCK_SEL_MASK BIT(29)
20 #define CLKE_MASK BIT(11)
21 #define RST_MASK BIT(9)
22 #define BYPASS_MASK BIT(4)
24 #define MDIV_MASK GENMASK(21, 12)
26 #define PDIV_MASK GENMASK(9, 4)
28 #define SDIV_MASK GENMASK(2, 0)
30 #define KDIV_MASK GENMASK(15, 0)
32 #define LOCK_TIMEOUT_US 10000
37 enum imx_pll14xx_type type;
38 const struct imx_pll14xx_rate_table *rate_table;
42 #define to_clk_pll14xx(_hw) container_of(_hw, struct clk_pll14xx, hw)
44 static const struct imx_pll14xx_rate_table *imx_get_pll_settings(
45 struct clk_pll14xx *pll, unsigned long rate)
47 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
50 for (i = 0; i < pll->rate_count; i++)
51 if (rate == rate_table[i].rate)
52 return &rate_table[i];
57 static long clk_pll14xx_round_rate(struct clk_hw *hw, unsigned long rate,
60 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
61 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table;
64 /* Assumming rate_table is in descending order */
65 for (i = 0; i < pll->rate_count; i++)
66 if (rate >= rate_table[i].rate)
67 return rate_table[i].rate;
69 /* return minimum supported value */
70 return rate_table[i - 1].rate;
73 static unsigned long clk_pll1416x_recalc_rate(struct clk_hw *hw,
74 unsigned long parent_rate)
76 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
77 u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div;
78 u64 fvco = parent_rate;
80 pll_gnrl = readl_relaxed(pll->base);
81 pll_div = readl_relaxed(pll->base + 4);
82 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT;
83 pdiv = (pll_div & PDIV_MASK) >> PDIV_SHIFT;
84 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT;
87 do_div(fvco, pdiv << sdiv);
92 static unsigned long clk_pll1443x_recalc_rate(struct clk_hw *hw,
93 unsigned long parent_rate)
95 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
96 u32 mdiv, pdiv, sdiv, pll_gnrl, pll_div_ctl0, pll_div_ctl1;
98 u64 fvco = parent_rate;
100 pll_gnrl = readl_relaxed(pll->base);
101 pll_div_ctl0 = readl_relaxed(pll->base + 4);
102 pll_div_ctl1 = readl_relaxed(pll->base + 8);
103 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT;
104 pdiv = (pll_div_ctl0 & PDIV_MASK) >> PDIV_SHIFT;
105 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT;
106 kdiv = pll_div_ctl1 & KDIV_MASK;
108 /* fvco = (m * 65536 + k) * Fin / (p * 65536) */
109 fvco *= (mdiv * 65536 + kdiv);
112 do_div(fvco, pdiv << sdiv);
117 static inline bool clk_pll1416x_mp_change(const struct imx_pll14xx_rate_table *rate,
120 u32 old_mdiv, old_pdiv;
122 old_mdiv = (pll_div >> MDIV_SHIFT) & MDIV_MASK;
123 old_pdiv = (pll_div >> PDIV_SHIFT) & PDIV_MASK;
125 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv;
128 static inline bool clk_pll1443x_mpk_change(const struct imx_pll14xx_rate_table *rate,
129 u32 pll_div_ctl0, u32 pll_div_ctl1)
131 u32 old_mdiv, old_pdiv, old_kdiv;
133 old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
134 old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
135 old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
137 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
138 rate->kdiv != old_kdiv;
141 static inline bool clk_pll1443x_mp_change(const struct imx_pll14xx_rate_table *rate,
142 u32 pll_div_ctl0, u32 pll_div_ctl1)
144 u32 old_mdiv, old_pdiv, old_kdiv;
146 old_mdiv = (pll_div_ctl0 >> MDIV_SHIFT) & MDIV_MASK;
147 old_pdiv = (pll_div_ctl0 >> PDIV_SHIFT) & PDIV_MASK;
148 old_kdiv = (pll_div_ctl1 >> KDIV_SHIFT) & KDIV_MASK;
150 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv ||
151 rate->kdiv != old_kdiv;
154 static int clk_pll14xx_wait_lock(struct clk_pll14xx *pll)
158 return readl_poll_timeout(pll->base, val, val & LOCK_TIMEOUT_US, 0,
162 static int clk_pll1416x_set_rate(struct clk_hw *hw, unsigned long drate,
165 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
166 const struct imx_pll14xx_rate_table *rate;
170 rate = imx_get_pll_settings(pll, drate);
172 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
173 drate, clk_hw_get_name(hw));
177 tmp = readl_relaxed(pll->base + 4);
179 if (!clk_pll1416x_mp_change(rate, tmp)) {
180 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
181 tmp |= rate->sdiv << SDIV_SHIFT;
182 writel_relaxed(tmp, pll->base + 4);
187 /* Bypass clock and set lock to pll output lock */
188 tmp = readl_relaxed(pll->base);
189 tmp |= LOCK_SEL_MASK;
190 writel_relaxed(tmp, pll->base);
194 writel_relaxed(tmp, pll->base);
196 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
197 (rate->sdiv << SDIV_SHIFT);
198 writel_relaxed(div_val, pll->base + 0x4);
201 * According to SPEC, t3 - t2 need to be greater than
202 * 1us and 1/FREF, respectively.
203 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
210 writel_relaxed(tmp, pll->base);
213 ret = clk_pll14xx_wait_lock(pll);
219 writel_relaxed(tmp, pll->base);
224 static int clk_pll1443x_set_rate(struct clk_hw *hw, unsigned long drate,
227 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
228 const struct imx_pll14xx_rate_table *rate;
232 rate = imx_get_pll_settings(pll, drate);
234 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
235 drate, clk_hw_get_name(hw));
239 tmp = readl_relaxed(pll->base + 4);
240 div_val = readl_relaxed(pll->base + 8);
242 if (!clk_pll1443x_mpk_change(rate, tmp, div_val)) {
243 tmp &= ~(SDIV_MASK) << SDIV_SHIFT;
244 tmp |= rate->sdiv << SDIV_SHIFT;
245 writel_relaxed(tmp, pll->base + 4);
251 tmp = readl_relaxed(pll->base);
253 writel_relaxed(tmp, pll->base);
255 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
256 (rate->sdiv << SDIV_SHIFT);
257 writel_relaxed(div_val, pll->base + 0x4);
258 writel_relaxed(rate->kdiv << KDIV_SHIFT, pll->base + 0x8);
261 * According to SPEC, t3 - t2 need to be greater than
262 * 1us and 1/FREF, respectively.
263 * FREF is FIN / Prediv, the prediv is [1, 63], so choose
270 writel_relaxed(tmp, pll->base);
273 ret = clk_pll14xx_wait_lock(pll);
279 writel_relaxed(tmp, pll->base);
284 static int clk_pll14xx_prepare(struct clk_hw *hw)
286 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
290 * RESETB = 1 from 0, PLL starts its normal
291 * operation after lock time
293 val = readl_relaxed(pll->base + GNRL_CTL);
295 writel_relaxed(val, pll->base + GNRL_CTL);
297 return clk_pll14xx_wait_lock(pll);
300 static int clk_pll14xx_is_prepared(struct clk_hw *hw)
302 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
305 val = readl_relaxed(pll->base + GNRL_CTL);
307 return (val & RST_MASK) ? 1 : 0;
310 static void clk_pll14xx_unprepare(struct clk_hw *hw)
312 struct clk_pll14xx *pll = to_clk_pll14xx(hw);
316 * Set RST to 0, power down mode is enabled and
317 * every digital block is reset
319 val = readl_relaxed(pll->base + GNRL_CTL);
321 writel_relaxed(val, pll->base + GNRL_CTL);
324 static const struct clk_ops clk_pll1416x_ops = {
325 .prepare = clk_pll14xx_prepare,
326 .unprepare = clk_pll14xx_unprepare,
327 .is_prepared = clk_pll14xx_is_prepared,
328 .recalc_rate = clk_pll1416x_recalc_rate,
329 .round_rate = clk_pll14xx_round_rate,
330 .set_rate = clk_pll1416x_set_rate,
333 static const struct clk_ops clk_pll1416x_min_ops = {
334 .recalc_rate = clk_pll1416x_recalc_rate,
337 static const struct clk_ops clk_pll1443x_ops = {
338 .prepare = clk_pll14xx_prepare,
339 .unprepare = clk_pll14xx_unprepare,
340 .is_prepared = clk_pll14xx_is_prepared,
341 .recalc_rate = clk_pll1443x_recalc_rate,
342 .round_rate = clk_pll14xx_round_rate,
343 .set_rate = clk_pll1443x_set_rate,
346 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
348 const struct imx_pll14xx_clk *pll_clk)
350 struct clk_pll14xx *pll;
352 struct clk_init_data init;
354 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
356 return ERR_PTR(-ENOMEM);
359 init.flags = pll_clk->flags;
360 init.parent_names = &parent_name;
361 init.num_parents = 1;
363 switch (pll_clk->type) {
365 if (!pll->rate_table)
366 init.ops = &clk_pll1416x_min_ops;
368 init.ops = &clk_pll1416x_ops;
371 init.ops = &clk_pll1443x_ops;
374 pr_err("%s: Unknown pll type for pll clk %s\n",
379 pll->hw.init = &init;
380 pll->type = pll_clk->type;
381 pll->rate_table = pll_clk->rate_table;
382 pll->rate_count = pll_clk->rate_count;
384 clk = clk_register(NULL, &pll->hw);
386 pr_err("%s: failed to register pll %s %lu\n",
387 __func__, name, PTR_ERR(clk));