drivers/clk/imx/clk-imx8qxp-lpcg.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018 NXP
   4  *      Dong Aisheng <aisheng.dong@nxp.com>
   5  */
   6
   7 #include <linux/clk-provider.h>
   8 #include <linux/err.h>
   9 #include <linux/io.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16
  17 #include "clk-scu.h"
  18 #include "clk-imx8qxp-lpcg.h"
  19
  20 #include <dt-bindings/clock/imx8-clock.h>
  21
  22 /*
  23  * struct imx8qxp_lpcg_data - Description of one LPCG clock
  24  * @id: clock ID
  25  * @name: clock name
  26  * @parent: parent clock name
  27  * @flags: common clock flags
  28  * @offset: offset of this LPCG clock
  29  * @bit_idx: bit index of this LPCG clock
  30  * @hw_gate: whether supports HW autogate
  31  *
  32  * This structure describes one LPCG clock
  33  */
  34 struct imx8qxp_lpcg_data {
  35         int id;
  36         char *name;
  37         char *parent;
  38         unsigned long flags;
  39         u32 offset;
  40         u8 bit_idx;
  41         bool hw_gate;
  42 };
  43
  44 /*
  45  * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
  46  * @lpcg: LPCG clocks array of one subsystem
  47  * @num_lpcg: the number of LPCG clocks
  48  * @num_max: the maximum number of LPCG clocks
  49  *
  50  * This structure describes each subsystem LPCG clocks information
  51  * which then will be used to create respective LPCGs clocks
  52  */
  53 struct imx8qxp_ss_lpcg {
  54         const struct imx8qxp_lpcg_data *lpcg;
  55         u8 num_lpcg;
  56         u8 num_max;
  57 };
  58
  59 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
  60         { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, },
  61         { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, },
  62         { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, },
  63         { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, },
  64         { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, },
  65         { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, },
  66         { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, },
  67         { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, },
  68         { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, },
  69         { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, },
  70         { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, },
  71         { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, },
  72         { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, },
  73         { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
  74         { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
  75         { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
  76
  77         { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
  78         { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
  79         { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
  80         { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
  81 };
  82
  83 static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
  84         .lpcg = imx8qxp_lpcg_adma,
  85         .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma),
  86         .num_max = IMX_ADMA_LPCG_CLK_END,
  87 };
  88
  89 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = {
  90         { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, },
  91         { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, },
  92         { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, },
  93         { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, },
  94         { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, },
  95         { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, },
  96         { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, },
  97         { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, },
  98         { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, },
  99         { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, },
 100         { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, },
 101         { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, },
 102         { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, },
 103         { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, },
 104         { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, },
 105         { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, },
 106         { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, },
 107         { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, },
 108         { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, },
 109 };
 110
 111 static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
 112         .lpcg = imx8qxp_lpcg_conn,
 113         .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn),
 114         .num_max = IMX_CONN_LPCG_CLK_END,
 115 };
 116
 117 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
 118         { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
 119         { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
 120         { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, },
 121         { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, },
 122         { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, },
 123         { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, },
 124         { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, },
 125         { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, },
 126         { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, },
 127         { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, },
 128         { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, },
 129         { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, },
 130         { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, },
 131         { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, },
 132         { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, },
 133         { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, },
 134         { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, },
 135         { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, },
 136         { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, },
 137         { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, },
 138         { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, },
 139         { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, },
 140         { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, },
 141         { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, },
 142         { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, },
 143         { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, },
 144         { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, },
 145         { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, },
 146         { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, },
 147         { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, },
 148         { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, },
 149         { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, },
 150         { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, },
 151         { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, },
 152         { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
 153 };
 154
 155 static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
 156         .lpcg = imx8qxp_lpcg_lsio,
 157         .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
 158         .num_max = IMX_LSIO_LPCG_CLK_END,
 159 };
 160
 161 #define IMX_LPCG_MAX_CLKS       8
 162
 163 static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec,
 164                                               void *data)
 165 {
 166         struct clk_hw_onecell_data *hw_data = data;
 167         unsigned int idx = clkspec->args[0] / 4;
 168
 169         if (idx >= hw_data->num) {
 170                 pr_err("%s: invalid index %u\n", __func__, idx);
 171                 return ERR_PTR(-EINVAL);
 172         }
 173
 174         return hw_data->hws[idx];
 175 }
 176
 177 static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
 178                                        struct device_node *np)
 179 {
 180         const char *output_names[IMX_LPCG_MAX_CLKS];
 181         const char *parent_names[IMX_LPCG_MAX_CLKS];
 182         unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
 183         struct clk_hw_onecell_data *clk_data;
 184         struct clk_hw **clk_hws;
 185         struct resource *res;
 186         void __iomem *base;
 187         int count;
 188         int idx;
 189         int ret;
 190         int i;
 191
 192         if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
 193                 return -EINVAL;
 194
 195         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 196         base = devm_ioremap_resource(&pdev->dev, res);
 197         if (IS_ERR(base))
 198                 return PTR_ERR(base);
 199
 200         count = of_property_count_u32_elems(np, "clock-indices");
 201         if (count < 0) {
 202                 dev_err(&pdev->dev, "failed to count clocks\n");
 203                 return -EINVAL;
 204         }
 205
 206         /*
 207          * A trick here is that we set the num of clks to the MAX instead
 208          * of the count from clock-indices because one LPCG supports up to
 209          * 8 clock outputs which each of them is fixed to 4 bits. Then we can
 210          * easily get the clock by clk-indices (bit-offset) / 4.
 211          * And the cost is very limited few pointers.
 212          */
 213
 214         clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
 215                                 IMX_LPCG_MAX_CLKS), GFP_KERNEL);
 216         if (!clk_data)
 217                 return -ENOMEM;
 218
 219         clk_data->num = IMX_LPCG_MAX_CLKS;
 220         clk_hws = clk_data->hws;
 221
 222         ret = of_property_read_u32_array(np, "clock-indices", bit_offset,
 223                                          count);
 224         if (ret < 0) {
 225                 dev_err(&pdev->dev, "failed to read clock-indices\n");
 226                 return -EINVAL;
 227         }
 228
 229         ret = of_clk_parent_fill(np, parent_names, count);
 230         if (ret != count) {
 231                 dev_err(&pdev->dev, "failed to get clock parent names\n");
 232                 return count;
 233         }
 234
 235         ret = of_property_read_string_array(np, "clock-output-names",
 236                                             output_names, count);
 237         if (ret != count) {
 238                 dev_err(&pdev->dev, "failed to read clock-output-names\n");
 239                 return -EINVAL;
 240         }
 241
 242         for (i = 0; i < count; i++) {
 243                 idx = bit_offset[i] / 4;
 244                 if (idx > IMX_LPCG_MAX_CLKS) {
 245                         dev_warn(&pdev->dev, "invalid bit offset of clock %d\n",
 246                                  i);
 247                         ret = -EINVAL;
 248                         goto unreg;
 249                 }
 250
 251                 clk_hws[idx] = imx_clk_lpcg_scu(output_names[i],
 252                                                 parent_names[i], 0, base,
 253                                                 bit_offset[i], false);
 254                 if (IS_ERR(clk_hws[idx])) {
 255                         dev_warn(&pdev->dev, "failed to register clock %d\n",
 256                                  idx);
 257                         ret = PTR_ERR(clk_hws[idx]);
 258                         goto unreg;
 259                 }
 260         }
 261
 262         ret = devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get,
 263                                           clk_data);
 264         if (!ret)
 265                 return 0;
 266
 267 unreg:
 268         while (--i >= 0) {
 269                 idx = bit_offset[i] / 4;
 270                 if (clk_hws[idx])
 271                         imx_clk_lpcg_scu_unregister(clk_hws[idx]);
 272         }
 273
 274         return ret;
 275 }
 276
 277 static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
 278 {
 279         struct device *dev = &pdev->dev;
 280         struct device_node *np = dev->of_node;
 281         struct clk_hw_onecell_data *clk_data;
 282         const struct imx8qxp_ss_lpcg *ss_lpcg;
 283         const struct imx8qxp_lpcg_data *lpcg;
 284         struct resource *res;
 285         struct clk_hw **clks;
 286         void __iomem *base;
 287         int ret;
 288         int i;
 289
 290         /* try new binding to parse clocks from device tree first */
 291         ret = imx_lpcg_parse_clks_from_dt(pdev, np);
 292         if (!ret)
 293                 return 0;
 294
 295         ss_lpcg = of_device_get_match_data(dev);
 296         if (!ss_lpcg)
 297                 return -ENODEV;
 298
 299         /*
 300          * Please don't replace this with devm_platform_ioremap_resource.
 301          *
 302          * devm_platform_ioremap_resource calls devm_ioremap_resource which
 303          * differs from devm_ioremap by also calling devm_request_mem_region
 304          * and preventing other mappings in the same area.
 305          *
 306          * On imx8 the LPCG nodes map entire subsystems and overlap
 307          * peripherals, this means that using devm_platform_ioremap_resource
 308          * will cause many devices to fail to probe including serial ports.
 309          */
 310         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 311         if (!res)
 312                 return -EINVAL;
 313         base = devm_ioremap(dev, res->start, resource_size(res));
 314         if (!base)
 315                 return -ENOMEM;
 316
 317         clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
 318                                 ss_lpcg->num_max), GFP_KERNEL);
 319         if (!clk_data)
 320                 return -ENOMEM;
 321
 322         clk_data->num = ss_lpcg->num_max;
 323         clks = clk_data->hws;
 324
 325         for (i = 0; i < ss_lpcg->num_lpcg; i++) {
 326                 lpcg = ss_lpcg->lpcg + i;
 327                 clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,
 328                                                   lpcg->flags, base + lpcg->offset,
 329                                                   lpcg->bit_idx, lpcg->hw_gate);
 330         }
 331
 332         for (i = 0; i < clk_data->num; i++) {
 333                 if (IS_ERR(clks[i]))
 334                         pr_warn("i.MX clk %u: register failed with %ld\n",
 335                                 i, PTR_ERR(clks[i]));
 336         }
 337
 338         return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 339 }
 340
 341 static const struct of_device_id imx8qxp_lpcg_match[] = {
 342         { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
 343         { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
 344         { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
 345         { .compatible = "fsl,imx8qxp-lpcg", NULL },
 346         { /* sentinel */ }
 347 };
 348
 349 static struct platform_driver imx8qxp_lpcg_clk_driver = {
 350         .driver = {
 351                 .name = "imx8qxp-lpcg-clk",
 352                 .of_match_table = imx8qxp_lpcg_match,
 353                 .suppress_bind_attrs = true,
 354         },
 355         .probe = imx8qxp_lpcg_clk_probe,
 356 };
 357
 358 builtin_platform_driver(imx8qxp_lpcg_clk_driver);
 359
 360 MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
 361 MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
 362 MODULE_LICENSE("GPL v2");