drivers/clk/imx/clk-imx7ulp.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Freescale Semiconductor, Inc.
   4  * Copyright 2017~2018 NXP
   5  *
   6  * Author: Dong Aisheng <aisheng.dong@nxp.com>
   7  *
   8  */
   9
  10 #include <dt-bindings/clock/imx7ulp-clock.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/err.h>
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/of_address.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19
  20 #include "clk.h"
  21
  22 static const char * const pll_pre_sels[]        = { "sosc", "firc", };
  23 static const char * const spll_pfd_sels[]       = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", };
  24 static const char * const spll_sels[]           = { "spll", "spll_pfd_sel", };
  25 static const char * const apll_pfd_sels[]       = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
  26 static const char * const apll_sels[]           = { "apll", "apll_pfd_sel", };
  27 static const char * const scs_sels[]            = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "dummy", };
  28 static const char * const ddr_sels[]            = { "apll_pfd_sel", "dummy", "dummy", "dummy", };
  29 static const char * const nic_sels[]            = { "firc", "ddr_clk", };
  30 static const char * const periph_plat_sels[]    = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
  31 static const char * const periph_bus_sels[]     = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
  32 static const char * const arm_sels[]            = { "core", "dummy", "dummy", "hsrun_core", };
  33
  34 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
  35 static const struct clk_div_table ulp_div_table[] = {
  36         { .val = 1, .div = 1, },
  37         { .val = 2, .div = 2, },
  38         { .val = 3, .div = 4, },
  39         { .val = 4, .div = 8, },
  40         { .val = 5, .div = 16, },
  41         { .val = 6, .div = 32, },
  42         { .val = 7, .div = 64, },
  43         { /* sentinel */ },
  44 };
  45
  46 static const int pcc2_uart_clk_ids[] __initconst = {
  47         IMX7ULP_CLK_LPUART4,
  48         IMX7ULP_CLK_LPUART5,
  49 };
  50
  51 static const int pcc3_uart_clk_ids[] __initconst = {
  52         IMX7ULP_CLK_LPUART6,
  53         IMX7ULP_CLK_LPUART7,
  54 };
  55
  56 static struct clk **pcc2_uart_clks[ARRAY_SIZE(pcc2_uart_clk_ids) + 1] __initdata;
  57 static struct clk **pcc3_uart_clks[ARRAY_SIZE(pcc3_uart_clk_ids) + 1] __initdata;
  58
  59 static void __init imx7ulp_clk_scg1_init(struct device_node *np)
  60 {
  61         struct clk_hw_onecell_data *clk_data;
  62         struct clk_hw **hws;
  63         void __iomem *base;
  64
  65         clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END),
  66                            GFP_KERNEL);
  67         if (!clk_data)
  68                 return;
  69
  70         clk_data->num = IMX7ULP_CLK_SCG1_END;
  71         hws = clk_data->hws;
  72
  73         hws[IMX7ULP_CLK_DUMMY]          = imx_clk_hw_fixed("dummy", 0);
  74
  75         hws[IMX7ULP_CLK_ROSC]           = imx_obtain_fixed_clk_hw(np, "rosc");
  76         hws[IMX7ULP_CLK_SOSC]           = imx_obtain_fixed_clk_hw(np, "sosc");
  77         hws[IMX7ULP_CLK_SIRC]           = imx_obtain_fixed_clk_hw(np, "sirc");
  78         hws[IMX7ULP_CLK_FIRC]           = imx_obtain_fixed_clk_hw(np, "firc");
  79         hws[IMX7ULP_CLK_UPLL]           = imx_obtain_fixed_clk_hw(np, "upll");
  80
  81         /* SCG1 */
  82         base = of_iomap(np, 0);
  83         WARN_ON(!base);
  84
  85         /* NOTE: xPLL config can't be changed when xPLL is enabled */
  86         hws[IMX7ULP_CLK_APLL_PRE_SEL]   = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
  87         hws[IMX7ULP_CLK_SPLL_PRE_SEL]   = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
  88
  89         /*                                                         name             parent_name    reg                  shift   width   flags */
  90         hws[IMX7ULP_CLK_APLL_PRE_DIV]   = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508,        8,      3,      CLK_SET_RATE_GATE);
  91         hws[IMX7ULP_CLK_SPLL_PRE_DIV]   = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608,        8,      3,      CLK_SET_RATE_GATE);
  92
  93         /*                                              name     parent_name     base */
  94         hws[IMX7ULP_CLK_APLL]           = imx_clk_hw_pllv4("apll",  "apll_pre_div", base + 0x500);
  95         hws[IMX7ULP_CLK_SPLL]           = imx_clk_hw_pllv4("spll",  "spll_pre_div", base + 0x600);
  96
  97         /* APLL PFDs */
  98         hws[IMX7ULP_CLK_APLL_PFD0]      = imx_clk_hw_pfdv2("apll_pfd0", "apll", base + 0x50c, 0);
  99         hws[IMX7ULP_CLK_APLL_PFD1]      = imx_clk_hw_pfdv2("apll_pfd1", "apll", base + 0x50c, 1);
 100         hws[IMX7ULP_CLK_APLL_PFD2]      = imx_clk_hw_pfdv2("apll_pfd2", "apll", base + 0x50c, 2);
 101         hws[IMX7ULP_CLK_APLL_PFD3]      = imx_clk_hw_pfdv2("apll_pfd3", "apll", base + 0x50c, 3);
 102
 103         /* SPLL PFDs */
 104         hws[IMX7ULP_CLK_SPLL_PFD0]      = imx_clk_hw_pfdv2("spll_pfd0", "spll", base + 0x60C, 0);
 105         hws[IMX7ULP_CLK_SPLL_PFD1]      = imx_clk_hw_pfdv2("spll_pfd1", "spll", base + 0x60C, 1);
 106         hws[IMX7ULP_CLK_SPLL_PFD2]      = imx_clk_hw_pfdv2("spll_pfd2", "spll", base + 0x60C, 2);
 107         hws[IMX7ULP_CLK_SPLL_PFD3]      = imx_clk_hw_pfdv2("spll_pfd3", "spll", base + 0x60C, 3);
 108
 109         /* PLL Mux */
 110         hws[IMX7ULP_CLK_APLL_PFD_SEL]   = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
 111         hws[IMX7ULP_CLK_SPLL_PFD_SEL]   = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
 112         hws[IMX7ULP_CLK_APLL_SEL]       = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
 113         hws[IMX7ULP_CLK_SPLL_SEL]       = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
 114
 115         hws[IMX7ULP_CLK_SPLL_BUS_CLK]   = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);
 116
 117         /* scs/ddr/nic select different clock source requires that clock to be enabled first */
 118         hws[IMX7ULP_CLK_SYS_SEL]        = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
 119         hws[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
 120         hws[IMX7ULP_CLK_NIC_SEL]        = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
 121         hws[IMX7ULP_CLK_DDR_SEL]        = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
 122
 123         hws[IMX7ULP_CLK_CORE_DIV]       = imx_clk_hw_divider_flags("divcore",   "scs_sel",  base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
 124         hws[IMX7ULP_CLK_CORE]           = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk);
 125         hws[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);
 126         hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk);
 127
 128         hws[IMX7ULP_CLK_DDR_DIV]        = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
 129                                                                0, ulp_div_table, &imx_ccm_lock);
 130
 131         hws[IMX7ULP_CLK_NIC0_DIV]       = imx_clk_hw_divider_flags("nic0_clk",          "nic_sel",  base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 132         hws[IMX7ULP_CLK_NIC1_DIV]       = imx_clk_hw_divider_flags("nic1_clk",          "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 133         hws[IMX7ULP_CLK_NIC1_BUS_DIV]   = imx_clk_hw_divider_flags("nic1_bus_clk",      "nic0_clk", base + 0x40, 4,  4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
 134
 135         hws[IMX7ULP_CLK_GPU_DIV]        = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);
 136
 137         hws[IMX7ULP_CLK_SOSC_BUS_CLK]   = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
 138                                                                CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
 139         hws[IMX7ULP_CLK_FIRC_BUS_CLK]   = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
 140                                                                CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
 141
 142         imx_check_clk_hws(hws, clk_data->num);
 143
 144         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 145 }
 146 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
 147
 148 static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
 149 {
 150         struct clk_hw_onecell_data *clk_data;
 151         struct clk_hw **hws;
 152         void __iomem *base;
 153         int i;
 154
 155         clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
 156                            GFP_KERNEL);
 157         if (!clk_data)
 158                 return;
 159
 160         clk_data->num = IMX7ULP_CLK_PCC2_END;
 161         hws = clk_data->hws;
 162
 163         /* PCC2 */
 164         base = of_iomap(np, 0);
 165         WARN_ON(!base);
 166
 167         hws[IMX7ULP_CLK_DMA1]           = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30);
 168         hws[IMX7ULP_CLK_RGPIO2P1]       = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30);
 169         hws[IMX7ULP_CLK_DMA_MUX1]       = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
 170         hws[IMX7ULP_CLK_CAAM]           = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30);
 171         hws[IMX7ULP_CLK_LPTPM4]         = imx7ulp_clk_hw_composite("lptpm4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
 172         hws[IMX7ULP_CLK_LPTPM5]         = imx7ulp_clk_hw_composite("lptpm5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
 173         hws[IMX7ULP_CLK_LPIT1]          = imx7ulp_clk_hw_composite("lpit1",   periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
 174         hws[IMX7ULP_CLK_LPSPI2]         = imx7ulp_clk_hw_composite("lpspi2",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4);
 175         hws[IMX7ULP_CLK_LPSPI3]         = imx7ulp_clk_hw_composite("lpspi3",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8);
 176         hws[IMX7ULP_CLK_LPI2C4]         = imx7ulp_clk_hw_composite("lpi2c4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac);
 177         hws[IMX7ULP_CLK_LPI2C5]         = imx7ulp_clk_hw_composite("lpi2c5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0);
 178         hws[IMX7ULP_CLK_LPUART4]        = imx7ulp_clk_hw_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4);
 179         hws[IMX7ULP_CLK_LPUART5]        = imx7ulp_clk_hw_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8);
 180         hws[IMX7ULP_CLK_FLEXIO1]        = imx7ulp_clk_hw_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4);
 181         hws[IMX7ULP_CLK_USB0]           = imx7ulp_clk_hw_composite("usb0",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xcc);
 182         hws[IMX7ULP_CLK_USB1]           = imx7ulp_clk_hw_composite("usb1",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xd0);
 183         hws[IMX7ULP_CLK_USB_PHY]        = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xd4, 30);
 184         hws[IMX7ULP_CLK_USDHC0]         = imx7ulp_clk_hw_composite("usdhc0",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xdc);
 185         hws[IMX7ULP_CLK_USDHC1]         = imx7ulp_clk_hw_composite("usdhc1",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xe0);
 186         hws[IMX7ULP_CLK_WDG1]           = imx7ulp_clk_hw_composite("wdg1",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xf4);
 187         hws[IMX7ULP_CLK_WDG2]           = imx7ulp_clk_hw_composite("wdg2",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0x10c);
 188
 189         imx_check_clk_hws(hws, clk_data->num);
 190
 191         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 192
 193         for (i = 0; i < ARRAY_SIZE(pcc2_uart_clk_ids); i++) {
 194                 int index = pcc2_uart_clk_ids[i];
 195
 196                 pcc2_uart_clks[i] = &hws[index]->clk;
 197         }
 198
 199         imx_register_uart_clocks(pcc2_uart_clks);
 200 }
 201 CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
 202
 203 static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
 204 {
 205         struct clk_hw_onecell_data *clk_data;
 206         struct clk_hw **hws;
 207         void __iomem *base;
 208         int i;
 209
 210         clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
 211                            GFP_KERNEL);
 212         if (!clk_data)
 213                 return;
 214
 215         clk_data->num = IMX7ULP_CLK_PCC3_END;
 216         hws = clk_data->hws;
 217
 218         /* PCC3 */
 219         base = of_iomap(np, 0);
 220         WARN_ON(!base);
 221
 222         hws[IMX7ULP_CLK_LPTPM6] = imx7ulp_clk_hw_composite("lptpm6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
 223         hws[IMX7ULP_CLK_LPTPM7] = imx7ulp_clk_hw_composite("lptpm7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
 224
 225         hws[IMX7ULP_CLK_MMDC]           = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
 226                                                                base + 0xac, 30, 0, &imx_ccm_lock);
 227         hws[IMX7ULP_CLK_LPI2C6] = imx7ulp_clk_hw_composite("lpi2c6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
 228         hws[IMX7ULP_CLK_LPI2C7] = imx7ulp_clk_hw_composite("lpi2c7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
 229         hws[IMX7ULP_CLK_LPUART6]        = imx7ulp_clk_hw_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
 230         hws[IMX7ULP_CLK_LPUART7]        = imx7ulp_clk_hw_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
 231         hws[IMX7ULP_CLK_DSI]            = imx7ulp_clk_hw_composite("dsi",     periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xa4);
 232         hws[IMX7ULP_CLK_LCDIF]          = imx7ulp_clk_hw_composite("lcdif",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xa8);
 233
 234         hws[IMX7ULP_CLK_VIU]            = imx_clk_hw_gate("viu",   "nic1_clk",     base + 0xa0, 30);
 235         hws[IMX7ULP_CLK_PCTLC]          = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30);
 236         hws[IMX7ULP_CLK_PCTLD]          = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30);
 237         hws[IMX7ULP_CLK_PCTLE]          = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
 238         hws[IMX7ULP_CLK_PCTLF]          = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
 239
 240         hws[IMX7ULP_CLK_GPU3D]          = imx7ulp_clk_hw_composite("gpu3d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
 241         hws[IMX7ULP_CLK_GPU2D]          = imx7ulp_clk_hw_composite("gpu2d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
 242
 243         imx_check_clk_hws(hws, clk_data->num);
 244
 245         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 246
 247         for (i = 0; i < ARRAY_SIZE(pcc3_uart_clk_ids); i++) {
 248                 int index = pcc3_uart_clk_ids[i];
 249
 250                 pcc3_uart_clks[i] = &hws[index]->clk;
 251         }
 252
 253         imx_register_uart_clocks(pcc3_uart_clks);
 254 }
 255 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
 256
 257 static void __init imx7ulp_clk_smc1_init(struct device_node *np)
 258 {
 259         struct clk_hw_onecell_data *clk_data;
 260         struct clk_hw **hws;
 261         void __iomem *base;
 262
 263         clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SMC1_END),
 264                            GFP_KERNEL);
 265         if (!clk_data)
 266                 return;
 267
 268         clk_data->num = IMX7ULP_CLK_SMC1_END;
 269         hws = clk_data->hws;
 270
 271         /* SMC1 */
 272         base = of_iomap(np, 0);
 273         WARN_ON(!base);
 274
 275         hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT);
 276
 277         imx_check_clk_hws(hws, clk_data->num);
 278
 279         of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
 280 }
 281 CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init);