1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Gated clock implementation
9 #include <linux/clk-provider.h>
10 #include <linux/module.h>
11 #include <linux/slab.h>
13 #include <linux/err.h>
14 #include <linux/string.h>
18 * DOC: basic gatable clock which can gate and ungate it's ouput
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parent is (un)prepared
22 * enable - clk_enable and clk_disable are functional & control gating
23 * rate - inherits rate from parent. No clk_set_rate support
24 * parent - fixed parent. No clk_set_parent support
34 unsigned int *share_count;
37 #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
39 static int clk_gate2_enable(struct clk_hw *hw)
41 struct clk_gate2 *gate = to_clk_gate2(hw);
46 spin_lock_irqsave(gate->lock, flags);
48 if (gate->share_count && (*gate->share_count)++ > 0)
51 if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
52 ret = clk_gate_ops.enable(hw);
54 reg = readl(gate->reg);
55 reg &= ~(3 << gate->bit_idx);
56 reg |= gate->cgr_val << gate->bit_idx;
57 writel(reg, gate->reg);
61 spin_unlock_irqrestore(gate->lock, flags);
66 static void clk_gate2_disable(struct clk_hw *hw)
68 struct clk_gate2 *gate = to_clk_gate2(hw);
72 spin_lock_irqsave(gate->lock, flags);
74 if (gate->share_count) {
75 if (WARN_ON(*gate->share_count == 0))
77 else if (--(*gate->share_count) > 0)
81 if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT) {
82 clk_gate_ops.disable(hw);
84 reg = readl(gate->reg);
85 reg &= ~(3 << gate->bit_idx);
86 writel(reg, gate->reg);
90 spin_unlock_irqrestore(gate->lock, flags);
93 static int clk_gate2_reg_is_enabled(void __iomem *reg, u8 bit_idx)
97 if (((val >> bit_idx) & 1) == 1)
103 static int clk_gate2_is_enabled(struct clk_hw *hw)
105 struct clk_gate2 *gate = to_clk_gate2(hw);
107 if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
108 return clk_gate_ops.is_enabled(hw);
110 return clk_gate2_reg_is_enabled(gate->reg, gate->bit_idx);
113 static void clk_gate2_disable_unused(struct clk_hw *hw)
115 struct clk_gate2 *gate = to_clk_gate2(hw);
119 if (gate->flags & IMX_CLK_GATE2_SINGLE_BIT)
122 spin_lock_irqsave(gate->lock, flags);
124 if (!gate->share_count || *gate->share_count == 0) {
125 reg = readl(gate->reg);
126 reg &= ~(3 << gate->bit_idx);
127 writel(reg, gate->reg);
130 spin_unlock_irqrestore(gate->lock, flags);
133 static const struct clk_ops clk_gate2_ops = {
134 .enable = clk_gate2_enable,
135 .disable = clk_gate2_disable,
136 .disable_unused = clk_gate2_disable_unused,
137 .is_enabled = clk_gate2_is_enabled,
140 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
141 const char *parent_name, unsigned long flags,
142 void __iomem *reg, u8 bit_idx, u8 cgr_val,
143 u8 clk_gate2_flags, spinlock_t *lock,
144 unsigned int *share_count)
146 struct clk_gate2 *gate;
148 struct clk_init_data init;
151 gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
153 return ERR_PTR(-ENOMEM);
155 /* struct clk_gate2 assignments */
157 gate->bit_idx = bit_idx;
158 gate->cgr_val = cgr_val;
159 gate->flags = clk_gate2_flags;
161 gate->share_count = share_count;
164 init.ops = &clk_gate2_ops;
166 init.parent_names = parent_name ? &parent_name : NULL;
167 init.num_parents = parent_name ? 1 : 0;
169 gate->hw.init = &init;
172 ret = clk_hw_register(dev, hw);